transistor structure

Abstract

A transistor structure includes a substrate of a semiconductor device, a first source / drain region, a second source / drain region, a gate structure, and a composite gate dielectric layer. The first source / drain region is located within the substrate of the semiconductor device. The second source / drain region is located within the substrate. The gate structure is located above the substrate, wherein the gate structure is laterally positioned between the first source / drain region and the second source / drain region. The composite gate dielectric layer is located between the gate structure and the substrate, wherein the composite gate dielectric layer comprises multiple laterally arranged portions.

Description

Technical Field

[0001] This disclosure pertains to a transistor structure. Background Technology

[0002] High-voltage transistors include transistors designed to operate at higher voltages (e.g., high gate voltage, high drain voltage) compared to medium-voltage and low-voltage transistors, and medium-voltage transistors include transistors designed to operate at higher voltages (e.g., high gate voltage, high drain voltage) compared to low-voltage transistors. The maximum voltage that a medium-voltage transistor can withstand (without damage) may be lower than the maximum voltage that a high-voltage transistor can withstand (without damage), and the maximum voltage that a low-voltage transistor can withstand (without damage) is lower than the maximum voltage that a medium-voltage transistor can withstand (without damage).

[0003] High-voltage and medium-voltage transistors can be used in applications such as integrated circuit (IC) drivers, power ICs, converter circuits, image sensors, power management, radio frequency (RF) power amplifiers, display driver ICs (DDICs), bipolar complementary metal oxide semiconductor (CMOS) diffused metal oxide semiconductor (DMOS) ICs (BCDICs), and / or image signal processing (ISP) ICs, etc. Utility Model Content

[0004] In some embodiments, a transistor structure includes: a substrate of a semiconductor device, a first source / drain region, a second source / drain region, a gate structure, and a composite gate dielectric layer. The first source / drain region is located in the substrate of the semiconductor device. The second source / drain region is located in the substrate. The gate structure is located above the substrate, wherein the gate structure is laterally positioned between the first source / drain region and the second source / drain region. The composite gate dielectric layer is located between the gate structure and the substrate, wherein the composite gate dielectric layer includes different plurality of laterally arranged portions.

[0005] In some embodiments, a transistor structure includes: a substrate of a semiconductor device, a first source / drain region, a second source / drain region, a gate structure, and a gate dielectric layer. The first source / drain region is located in the substrate of the semiconductor device. The second source / drain region is located in the substrate. The gate structure is located above the substrate, wherein the gate structure is laterally positioned between the first source / drain region and the second source / drain region. The gate dielectric layer is located between the gate structure and the substrate. The gate structure includes a plurality of laterally arranged doped regions.

[0006] In some embodiments, a transistor structure includes: a substrate, a gate dielectric layer, a gate structure, a first source / drain region, and a second source / drain region. The gate dielectric layer is located on the substrate and includes one or more laterally arranged first portions, one or more second portions, and one or more third portions, which are different from each other. The gate structure is located above the gate dielectric layer. The first source / drain region and the second source / drain region are laterally adjacent to opposite sides of the gate structure. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a schematic diagram of an exemplary semiconductor device described herein.

[0009] Figures 2A to 2C A schematic diagram illustrating an exemplary embodiment of the integrated circuit device described herein;

[0010] Figures 3A to 3W A schematic diagram illustrating an exemplary embodiment of an integrated circuit device including the composite gate dielectric layer described herein;

[0011] Figures 4A to 4C A schematic diagram illustrating an exemplary embodiment of the integrated circuit device described herein;

[0012] Figures 5A to 5C A schematic diagram illustrating an exemplary embodiment of the integrated circuit device described herein;

[0013] Figures 6A to 6Z A schematic diagram illustrating an exemplary embodiment of an integrated circuit device including the composite gate structure described herein;

[0014] Figures 7A to 7C A schematic diagram illustrating an exemplary embodiment of the integrated circuit device described herein;

[0015] Figures 8A to 8CA schematic diagram illustrating an exemplary embodiment of the integrated circuit device described herein;

[0016] Figure 9 A schematic diagram illustrating an exemplary embodiment of the integrated circuit device described herein;

[0017] Figure 10 A flowchart illustrating the exemplary process associated with forming the transistor structure described herein.

[0018] [Symbol Explanation]

[0019] 100: Semiconductor devices

[0020] 102: Device Layer

[0021] 104: Interconnection Layer

[0022] 106:Substrate

[0023] 108, 108a, 108b: Integrated circuit devices

[0024] 110: Dielectric layer

[0025] 112, 112a~112c: Contact structure

[0026] 114: Interlayer dielectric layer (ILD layer)

[0027] 116: Etching Stop Layer (ESL)

[0028] 118: Metallized Structure

[0029] 120: Interconnection Structure

[0030] 200, 300, 400, 500, 600, 700, 800, 900: Exemplary Implementation

[0031] 202: Active Area

[0032] 204a, 204b: Source / Drain Regions

[0033] 206: Gate structure

[0034] 208: Gate dielectric layer

[0035] 210a~210c, 502a~502c: Column

[0036] 212a~212c, 504a~504c: lines

[0037] 214, 216, 218, 220, 222, 224, 226, 228, 230: Partial

[0038] 232: Quarantine Zone

[0039] 234: Sidewall spacers

[0040] 236a, 236b: Metal silicide layers

[0041] 238: Edge portion

[0042] 240: Central Part

[0043] 506, 508, 510, 512, 514, 516, 518, 520, 522, 528: Doped regions

[0044] 510a~510c: Column

[0045] 512a~512c: lines

[0046] 1000: Process

[0047] 1010, 1020, 1030, 1040, 1050: Blocks AA, BB: Lines Detailed Implementation

[0048] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0049] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0050] High-voltage transistors can be integrated with low-voltage transistors into a semiconductor device, allowing power management circuitry, display driver circuitry, sensor circuitry, and / or other high-voltage circuitry to be integrated with the low-voltage logic circuitry of the semiconductor device. While this allows high-voltage and low-voltage transistors to be manufactured using similar semiconductor manufacturing processes and share manufacturing operations, this manufacturing integration can lead to performance defects in high-voltage transistors.

[0051] For example, electrical isolation in the form of isolation regions (e.g., shallow trench isolation (STI) regions, local oxidation of silicon (LOCOS) regions) can be provided around high-voltage transistors in a manner similar to that used for low-voltage transistors. The abrupt transition between the isolation and channel regions of a high-voltage transistor can lead to a phenomenon known as the subcritical hump effect (or double hump effect). For example, the critical voltage (V0) of a high-voltage transistor... t The voltage threshold voltage (V0) of a high-voltage transistor may be lowest near the edge of the channel region (e.g., due to field crowding and / or surface doping concentration, etc.) and may increase towards the center of the channel region, resulting in the high-voltage transistor's threshold voltage (V0). t A subcritical peak appears. This is due to the critical voltage (V) of the high-voltage transistor. t The subcritical swing and subcritical closed-state current leakage are lower at the edges of the channel region than near the center of the channel region.

[0052] In some embodiments described herein, the high-voltage transistor may include a composite gate dielectric layer having multiple regions with different dielectric constant values ​​(e.g., different k values) to achieve a threshold voltage (Vc) on the channel region of the high-voltage transistor. t The uniformity is higher than when using a uniform gate dielectric layer. Regions with different k values ​​can be arranged along the length of the channel region between the source / drain regions of the high-voltage transistor, and / or along the width of the channel region. Using regions with different k values ​​can compensate for the subcritical hump effect at the edge of the channel region by adjusting the critical voltage at the edge of the channel region. Alternatively and / or, the critical voltage uniformity can be increased by forming the gate structure of the high-voltage transistor with multiple regions having different work function values ​​(e.g., individually or in addition to adjusting the critical voltage by regions with different k values ​​in the gate dielectric layer). Therefore, the gate structure can be called a composite gate structure. In a composite gate structure, regions with different work function values ​​can compensate for the subcritical hump effect at the edge of the channel region by adjusting the critical voltage at the edge of the channel region.

[0053] In this way, composite dielectric layers with multiple regions having different dielectric constant values ​​and / or composite gate structures with multiple regions having different work functions increase the critical voltage uniformity in the channel region of the high-voltage transistor. This increased critical voltage uniformity enables the high-voltage transistor to achieve lower subcritical swing and lower subcritical off-state current leakage, which increases the operating efficiency of the high-voltage transistor and allows for a reduction in its size without increasing (or minimally increasing) the subcritical swing and / or subcritical off-state current leakage.

[0054] Figure 1 This is a schematic diagram of an exemplary semiconductor device 100 described herein. The semiconductor device 100 may include a system-on-chip (SoC) device, a logic device (such as a central processing unit (CPU) or a graphics processing unit (GPU)), a memory device (e.g., a high bandwidth memory (HBM) device), a panel driver device, an integrated circuit (IC) driver, a radio frequency (RF) power amplifier, a display driver IC (DDIC), and / or another type of semiconductor device.

[0055] like Figure 1 As shown, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104 located above the device layer 102 along the z-direction in the semiconductor device 100. The device layer 102 may also be referred to as the front end of line (FEOL) region of the semiconductor device 100. The interconnect layer 104 may also be referred to as the back end of line (BEOL) region of the semiconductor device 100.

[0056] Device layer 102 includes substrate 106. Substrate 106 may correspond to a portion of a semiconductor wafer on which semiconductor device 100 is formed. Substrate 106 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates. Substrate 106 may extend in the semiconductor device 100 along the x-direction and / or y-direction.

[0057] Integrated circuit device 108 may be included in and / or on substrate 106 in device layer 102 of semiconductor device 100. Integrated circuit device 108 includes front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (finFET) structures, front-end gate all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices. The front-end semiconductor device is a semiconductor device formed in device layer 102 of semiconductor device 100 (e.g., in and / or on substrate 106).

[0058] In some implementations, one or more integrated circuit devices 108 include high-voltage transistors (or medium-voltage transistors). A "high-voltage transistor" is a transistor designed to operate at a higher operating voltage (e.g., a higher gate voltage, a higher source / drain voltage) than a low-voltage transistor. For example, a high-voltage transistor may be used to operate in a drain voltage range of about 9 volts to about 36 volts, while a low-voltage transistor may be used to operate in a drain voltage range of about 0 volts to about 1.8 volts. However, other values ​​within these ranges are also within the scope of this disclosure.

[0059] In some implementations, high-voltage transistors (or medium-voltage transistors) may include laterally diffused (or laterally double-diffused) metal-oxide-semiconductor (LDMOS) transistors having drift regions in which charge carriers diffuse laterally to facilitate the electric field distribution between the gate structure and the source / drain regions of the high-voltage transistor. The lateral diffusion of charge carriers in the drift regions enables the high-voltage transistor to withstand higher gate and source / drain voltages than low-voltage transistors (e.g., by increasing the breakdown voltage of the high-voltage transistor).

[0060] A dielectric layer 110 is included above substrate 106. Dielectric layer 110 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or another type of dielectric layer. Dielectric layer 110 includes a dielectric material that allows for selective etching or protection from etching of various portions of substrate 106 and / or integrated circuit device 108, and / or electrically isolates integrated circuit device 108 in device layer 102. Dielectric layer 110 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) x(and / or another oxide material) and / or another type of dielectric material. The dielectric layer 110 may extend in the semiconductor device 100 along the x-direction and / or y-direction.

[0061] An interconnect layer 104 of the semiconductor device 100 is included above a substrate 106 along the z-direction and above an integrated circuit device 108. The integrated circuit device 108 can be electrically coupled to the interconnect layer 104 via a contact structure 112. In some embodiments, the integrated circuit device 108 can be electrically coupled to gate contacts and source / drain contacts. The contact structure 112 may include contact plugs, vias, pillars, contact pads, and / or other types of conductive contacts. The contact structure 112 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti) and their alloys, metal nitrides containing one or more metals, and / or other conductive materials. In some embodiments, a pad is included between the contact structure 112 and the dielectric layer 110. The pad may include an attachment pad, a barrier pad, and / or another type of pad, and may include pad materials such as tantalum (Ta), tantalum nitride (TaN), and / or titanium nitride (TiN), etc.

[0062] Interconnect layer 104 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged in a direction approximately perpendicular to substrate 106 (e.g., the z-direction). The dielectric layers may include ILD layers 114 and ESL layers 116 arranged alternately along the z-direction. ILD layers 114 and ESL layers 116 may extend in the semiconductor device 100 along the x-direction and / or y-direction.

[0063] ILD layers 114 may each comprise oxides (e.g., silicon oxide (SiO2)). x The dielectric material can be an undoped silicate glass (USG), a boron-containing silicate glass (BSG), a fluorine-containing silicate glass (FSG), a tetraethyl orthosilicate (TEOS), a hydrosilsesquioxane (HSQ), and / or another suitable dielectric material. In some embodiments, the ILD layer 114 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x ), amorphous fluorinated carbon (aC) x F y), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbonate (SiOC) polymers, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silica (SiO2). x ),etc.

[0064] ESL 116 may each include silicon nitride (Si) x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some implementations, ILD layers 114 and ESL 116 include different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in interconnect layer 104.

[0065] Interconnect layer 104 includes multiple conductive structures. One or more conductive structures are electrically coupled and / or physically coupled to one or more integrated circuit devices 108 in device layer 102 (e.g., to contact structures 112 of integrated circuit devices 108). The conductive structures provide circuit wiring capable of providing signals and / or power to and / or from integrated circuit devices 108. The conductive structures may include combinations of metallization structures 118 and interconnect structures 120. Metallization structure 118 may include trenches, metallization layers, conductive traces, and / or other types of metallization structures. Interconnect structure 120 may include vias, plugs, interconnects, and / or other types of interconnect structures. Metallization structure 118 and interconnect structure 120 may be one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials. In some implementations, the metallized structure 118 and the interconnect structure 120 include one or more pad layers. The one or more pad layers may include barrier pads, adhesion pads, and / or another type of pad. Examples of materials for the one or more pads include tantalum nitride (TaN) and / or titanium nitride (TiN), etc.

[0066] In some implementations, the metallization structures 118 and interconnect structures 120 of interconnect layer 104 may be vertically aligned (e.g., along the z-direction). In other words, multiple stacked metallization structures 118 and interconnect structures 120 extend between the top of device layer 102 and interconnect layer 104 to facilitate the transmission of electrical signals and / or power between device layer 102 and the connection structure (not shown) of semiconductor device 100. These stacked metallization structures 118 may be arranged in a layer referred to as an M layer. For example, a metal-O (MO) layer may be located at the bottom of interconnect layer 104 and may be directly coupled to device layer 102 (e.g., coupled to contact structure 112 of integrated circuit device 108 in device layer 102). A via-1 (V1) layer may be included above the MO layer, the V1 layer including one or more interconnect structures 120. Metal-1 (M1) layer may be located above V1 layer in interconnect layer 104, via-2 (V2) layer may be included above M1 layer, metal-2 (M2) layer may be included above V2 layer, and so on. In addition, via layers may be included between vertically arranged M layers.

[0067] As mentioned above, providing Figure 1 As an example, other examples may be similar to the reference. Figure 1 The instances described are different.

[0068] Figures 2A to 2C This is a schematic diagram of an exemplary embodiment 200 of the integrated circuit device 108 described herein. In exemplary embodiment 200, the integrated circuit device 108 includes a high-voltage transistor structure. Figure 2A A top view illustrating the integrated circuit device 108. Figure 2B Description of integrated circuit device 108 along Figure 2A An illustrative cross-section of line AA (e.g., along the x-direction) in the diagram. Figure 2C Description of integrated circuit device 108 along Figure 2A An illustrative cross-sectional view of line BB (e.g., along the y-direction) in the diagram.

[0069] like Figure 2A As shown, the integrated circuit device 108 includes an active region 202. The active region 202 may also be referred to as an operation domain (OD), and may include a portion of the substrate 106 of the semiconductor device 100 used for active operation of the integrated circuit device 108.

[0070] Integrated circuit device 108 may include source / drain regions 204a and 204b in active region 202 (e.g., in substrate 106 of semiconductor device 100). A source / drain region may refer to a source region, a drain region, or a combination of both, depending on the context. In some implementations, source / drain region 204a is the source region of integrated circuit device 108, and source / drain region 204b is the drain region of integrated circuit device 108, for operation at relatively high voltages (e.g., up to about 36 volts or higher).

[0071] Source / drain regions 204a and 204b may each include one or more doped regions of the substrate 106 of the semiconductor device 100. In some embodiments, source / drain regions 204a and 204b may include the same type of dopant. For example, source / drain regions 204a and 204b may each include silicon doped with one or more p-type dopants (such as boron (B) and / or gallium (Ga)), etc. Alternatively, source / drain regions 204a and 204b may each include silicon doped with one or more n-type dopants (such as arsenic (A) and / or phosphorus (P)), etc. In some embodiments, source / drain regions 204a and 204b include different types of dopant. For example, source / drain region 204a may include silicon doped with one or more p-type dopants, while source / drain region 204b may include silicon doped with one or more n-type dopants.

[0072] The integrated circuit device 108 may include a gate structure 206 extending along the y-direction through the active region 202. The gate structure 206 may be located above and / or around one or more sides of the active region 202. The gate structure 206 may be laterally located between source / drain regions 204a and 204b. The source / drain region 204a may be located on a first side of the gate structure 206 (e.g., laterally adjacent to the first side), while the source / drain region 204b may be located on a second side of the gate structure 206 opposite to the first side (e.g., laterally adjacent to the second side). Therefore, the source / drain regions 204a, the gate structure 206, and the source / drain regions 204b may be laterally arranged in the x-direction. The portion of the active region 202 located below the gate structure 206 may be referred to as the channel region of the integrated circuit device 108.

[0073] In some embodiments, the gate structure 206 includes a polysilicon gate. In some embodiments, the gate structure 206 includes a metal gate and includes one or more metal materials, such as tungsten (W), titanium (Ti), titanium aluminum (TiAl), and / or other suitable metal materials.

[0074] Integrated circuit device 108 includes a gate dielectric layer 208. The gate dielectric layer 208 may be included on an active region 202 (e.g., on a substrate 106 of semiconductor device 100) such that the gate dielectric layer is located between the active region 202 and the gate structure 206. The gate dielectric layer 208 may provide electrical isolation between the gate structure 206 and the active region 202, allowing a voltage applied to the gate structure 206 to generate an electric field in the active region 202. The electric field alters the conductivity of the active region 202, thereby selectively forming a conductive channel between source / drain regions 204a and 204b.

[0075] like Figure 2A As shown, the gate dielectric layer 208 is a composite gate dielectric layer, wherein the gate dielectric layer 208 includes multiple portions with different k values. The threshold voltage (V) near the edge of the active region 202 and / or the source / drain regions 204a and 204b is adjusted. t The different k values ​​in these parts can compensate for the subcritical hump effect at the edge of the active region 202 of the integrated circuit device 108. This enables the integrated circuit device 108 to achieve a larger threshold voltage (V) on the active region 202. t Uniformity.

[0076] These portions of the gate dielectric layer 208 can be arranged in a grid, which includes a plurality of columns 210a to 210c arranged in the x direction and extending in the y direction, and a plurality of rows 212a to 212c arranged in the y direction and extending in the x direction. Figure 2A The number of columns, rows, and sections described herein are examples, and other numbers are within the scope of this disclosure.

[0077] Row 212a may include portions 214, 216, and 218 of the gate dielectric layer 208. Row 212b may include portions 220, 222, and 224 of the gate dielectric layer 208. Row 212c may be located along the y-direction between rows 212a and 212b, and may include portions 226, 228, and 230. Rows 212a and 212b may be located at the outer edge of the active region 202 of the integrated circuit device 108, and the material composition of portions 214, 216, 218, 220, 222, and 224 included in rows 212a and 212b may be selected to adjust the critical voltage of the integrated circuit device 108 at the edge of the active region 202. The material composition of portions 226, 228, and 230 included in row 212c may be selected to adjust the critical voltage of the integrated circuit device 108 at the center of the active region 202.

[0078] In row 212a, portions 214, 216, and 218 can be arranged along the x-direction, and portion 216 can be located laterally along the x-direction between portions 214 and 218. In row 212b, portions 220, 222, and 224 can be arranged along the x-direction, and portion 222 can be located laterally along the x-direction between portions 220 and 224. In row 212c, portions 226, 228, and 230 can be arranged along the x-direction, and portion 228 can be located laterally along the x-direction between portions 226 and 230.

[0079] Column 210a may include portions 214, 220, and 226 of the gate dielectric layer 208. Column 210b may include portions 218, 224, and 230 of the gate dielectric layer 208. Column 210c may be located between columns 210a and 210b along the x-direction and may include portions 216, 222, and 228. Columns 210a and 210b may be located at opposite ends of the channel region below the gate structure 206 of the integrated circuit device 108, and the material composition of portions 214, 218, 220, 224, 226, and 230 included in columns 210a and 210b may be selected to adjust the critical voltage of the integrated circuit device 108 at both ends of the channel region. The material composition of portions 216, 222, and 228 included in column 210c may be selected to adjust the critical voltage of the integrated circuit device 108 at the center of the channel region.

[0080] In column 210a, portions 214, 220, and 226 can be arranged along the y-direction, with portion 226 positioned laterally along the y-direction between portions 214 and 220. In column 210b, portions 218, 224, and 230 can be arranged along the y-direction, with portion 230 positioned laterally along the y-direction between portions 218 and 224. In column 210c, portions 216, 222, and 228 can be arranged along the y-direction, with portion 228 positioned laterally along the y-direction between portions 216 and 222.

[0081] Two or more of portions 214-230 may have substantially the same k value. For example, portions 214, 218, 220, and 224 may have substantially the same k value. These portions 214, 218, 220, and 224 may comprise the same material or the same material composition to achieve substantially the same k value. For example, portions 214, 218, 220, and 224 may each comprise silicon dioxide (SiO2). As another example, portions 214, 218, 220, and 224 may each comprise silicon nitride (SiO2). x N y (e.g., Si3N4). Similarly, portions 216 and 222 may have substantially the same k value and may include the same material or the same material composition, and / or portions 226 and 230 may have substantially the same k value and may include the same material or the same material composition.

[0082] The k-values ​​of portions 214, 218, 220, and 224 may differ from those of portions 226 and 230 to compensate for field accumulation and / or surface doping concentration at the edges of the active region 202. For example, the k-values ​​of portions 214, 218, 220, and 224 may be greater than those of portions 226 and 230. The larger k-values ​​of portions 214, 218, 220, and 224 provide a higher threshold voltage (V0) at the edges of the active region 202 than the k-values ​​of portions 214, 218, 220, and 224, which are approximately equal to the k-values ​​of portions 226 and 230. t This provides a greater critical voltage uniformity in the active region 202 along the y-direction than when the k-values ​​of portions 214, 218, 220, and 224 are approximately equal to the k-values ​​of portions 226 and 230. Therefore, portions 214, 218, 220, and 224 can be made of materials with higher k-values ​​(e.g., hafnium oxide (HfO)) than the materials of portions 226 and 230 (e.g., silicon dioxide (SiO2)). x Composed of, for example, HfO2).

[0083] Similarly, the k-values ​​of portions 216 and 222 may differ from that of portion 228 to compensate for field accumulation and / or surface doping concentration at the edges of the active region 202. For example, the k-values ​​of portions 216 and 222 may be greater than that of portion 228, which provides greater critical voltage uniformity along the y-direction in the active region 202 than when the k-values ​​of portions 216 and 222 are approximately equal to that of portion 228. Therefore, portions 216 and 222 may be composed of materials with higher k-values ​​than those of portion 228.

[0084] Along the x-direction (e.g., along the length of the channel region of integrated circuit device 108), the k-values ​​of portions 214, 218, 220, and 224 may differ from the k-values ​​of portions 216 and 222 to compensate for field accumulation and / or surface doping concentration at the ends of the channel region. For example, the k-values ​​of portions 214, 218, 220, and 224 may be greater than the k-values ​​of portions 216 and 222. Therefore, at the edges of the active region 202, the critical voltage uniformity provided along the x-direction in the channel region is greater than when the k-values ​​of portions 214, 218, 220, and 224 are approximately equal to the k-values ​​of portions 216 and 222. Therefore, portions 214, 218, 220, and 224 may be composed of materials having higher k-values ​​than the materials of portions 216 and 222.

[0085] Similarly, the k-values ​​of portions 226 and 230 may differ from that of portion 228 to compensate for field accumulation and / or surface doping concentration at the edges of the channel region. For example, the k-values ​​of portions 226 and 230 may be greater than that of portion 228, which provides greater critical voltage uniformity along the x-direction in the channel region than when the k-values ​​of portions 226 and 230 are approximately equal to that of portion 228. Therefore, portions 226 and 230 may be composed of materials with higher k-values ​​than those of portion 228.

[0086] The arrangement, associated k-values, and associated material composition of portions 214-230 are examples, and other arrangements, associated k-values, and associated material compositions of portions 214-230 are within the scope of this disclosure. Portions 214-230 of the gate dielectric layer 208 may include various dielectric materials to achieve a specific k-value layout of the gate dielectric layer 208, such as silicon oxide (SiO2). x Such as SiO2), silicon nitride (Si x N y Such as Si3N4), hafnium oxide (HfO) x Such as HfO2), aluminum oxide (Al x O y Such as Al2O3), lanthanum oxide (La x O y Such as La2O3), tantalum oxide (Ta x O y Such as Ta2O5), titanium dioxide (TiO2) x Such as TiO2), strontium titanium oxide (SrTiO2) x Such as SrTiO3), hafnium silicon oxide (HfSiO) x Such as HfSiO4), yttrium oxide (Y) x O y Such as Y2O3) and / or zirconium oxide (ZrO) x Examples of such dielectric materials include titanium hafnium oxide (HfO2), etc. In some embodiments, one or more of portions 214-230 include oxide materials, which include two or more of hafnium (Hf), titanium (Ti), lanthanum (La), silicon (Si), and / or zirconium (Zr). x Ti y O z ), hafnium oxide lanthanum (Hf) x La y O z ), hafnium silicon oxide (Hf) x Si y O z ) and / or hafnium zirconium oxide (Hf x Zr y Oz )etc.

[0087] like Figure 2A As further shown, the source / drain region 204a may include one or more contact structures 112a (e.g., source / drain contacts) such that the one or more contact structures 112a are electrically connected and / or physically connected to the source / drain region 204a. The source / drain region 204b may include one or more contact structures 112b (e.g., source / drain contacts) such that the one or more contact structures 112b are electrically connected and / or physically connected to the source / drain region 204b. The gate structure 206 may include one or more contact structures 112c (e.g., gate contacts) such that the one or more contact structures 112c are electrically connected and / or physically connected to the gate structure 206.

[0088] like Figure 2B and Figure 2C As shown, the active region 202 of the integrated circuit device 108 may be included in the substrate 106 of the semiconductor device 100. Source / drain regions 204a and 204b may be included in the substrate 106, the gate structure 206 may be included above the substrate 106, and the gate dielectric layer 208 (and portions 214-230 included therein) may be included between the gate structure 206 and the substrate 106.

[0089] like Figure 2B and Figure 2C As further shown, isolation regions 232 (e.g., STI regions, LOCOS regions) may be included in the substrate 106 located on one or more sides of the active region 202. In some embodiments, isolation regions 232 are formed in trenches in the substrate 106 such that isolation regions 232 laterally surround the active region 202 and provide a continuous isolation barrier layer around the active region 202. Isolation regions 232 may include dielectric materials such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), fluorine-doped silicon glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. Additionally and / or alternatively, isolation region 232 may include one or more doped regions of substrate 106.

[0090] like Figure 2B As shown, sidewall spacers 234 may be included above and / or on the sidewalls of the gate structure 206. Sidewall spacers 234 provide electrical isolation for the gate structure 206 and reduce the likelihood of an electrical short circuit between the gate structure 206 and contact structures 112a and / or 112b. Sidewall spacers 234 may include one or more electrically insulating materials, such as silicon oxycarbide (SiOC), nitrogen-free SiOC, and / or other suitable materials.

[0091] like Figure 2B As further shown, dielectric layer 110 may be included above integrated circuit device 108. Contact structures 112a and 112b may extend through dielectric layer 110 and reach source / drain regions 204a and 204b, respectively. Metal silicide layers 236a and 236b may be included on source / drain regions 204a and 204b of integrated circuit device 108, respectively. Metal silicide layers 236a and 236b may each include titanium silicide (TiSi), ruthenium silicide (RuSi), and / or another type of metal silicide material. Metal silicide layers 236a and 236b provide a transition between the semiconductor material of source / drain regions 204a and 204b and the metal material of contact structures 112a and 112b formed on source / drain regions 204a and 204b, respectively. The metal silicide layers 236a and 236b enable a low contact resistance between the contact structures 112a and 112b and the source / drain regions 204a and 204b.

[0092] like Figure 2C As shown, the gate structure 206 may extend along the substrate 106 and extend in the y-direction over one or more portions of the isolation region 232. The contact structure 112c may extend through the dielectric layer 110 and may make electrical and / or physical contact with the gate structure 206.

[0093] like Figure 2C Further, portions 214 and 220 of the gate dielectric layer 208 may be located above the edge portion 238 of the active region 202 along the y-direction, and portion 226 of the gate dielectric layer 208 may be located above the center portion 240 of the active region 202. The materials of portions 214 and 220 may be selected such that portions 214 and 220 have specific k values ​​for adjusting the threshold voltage of the integrated circuit device 108 in the edge portion 238. Portions 216, 218, 222, and 224 ( Figure 2C The material of portions 216, 218, 222, and 224 (not shown in the cross-section) can be similarly selected such that portions 216, 218, 222, and 224 have specific k values ​​for adjusting the critical voltage of the integrated circuit device 108 in the edge portion 238. The material of portion 226 can be selected such that portion 226 has a specific k value for adjusting the critical voltage of the integrated circuit device 108 in the central portion 240. Similarly, portions 228 and 230 (not shown in the cross-section) can be selected... Figure 2C The material (not shown in the cross-section) is such that portions 228 and 230 have a k value for adjusting the critical voltage of the integrated circuit device 108 in the central portion 240.

[0094] As mentioned above, providing Figures 2A to 2C As an example, other examples may be similar to the reference. Figures 2A to 2CThe instances described are different.

[0095] Figures 3A to 3W This is a schematic diagram of an exemplary embodiment 300 of an integrated circuit device 108 comprising the composite gate dielectric layer 208 described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, ion implantation tools, planarization tools, and / or another suitable semiconductor processing tool) may be used to perform one or more of the described operations.

[0096] See Figures 3A to 3C One or more operations in the exemplary implementation 300 may be performed together with the substrate 106 of the semiconductor device 100. The substrate 106 may be provided in the form of a semiconductor wafer or another type of substrate.

[0097] like Figure 3D and Figure 3E As shown, isolation region 232 may be formed in substrate 106. Isolation region 232 may define active region 202 of integrated circuit device 108. In some embodiments, a recess may be formed in substrate 106, and isolation region 232 may be formed in the recess.

[0098] In some embodiments, the pattern in the photoresist layer is used to etch the substrate 106 to form grooves. In these embodiments, the photoresist layer can be formed on the substrate 106 using a deposition tool (e.g., using spin coating and / or another suitable deposition technique). The photoresist layer can be exposed to a radiation source using an exposure tool to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The substrate 106 can be etched based on the pattern using an etching tool to form grooves. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the substrate 106. The deposition tool can be used to deposit isolation regions 232 in the trench using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques and / or another suitable deposition technique.

[0099] Optionally, one or more regions of the substrate 106 may be doped to form isolation regions 232. An ion implantation tool may be used to perform the ion implantation operation to implant dopant into the substrate 106 to form isolation regions 232.

[0100] like Figure 3F and Figure 3G As shown, portions 214, 218, 220, and / or 224 of the gate dielectric layer 208 may be formed over the active region 202 of the substrate 106. In some embodiments, a dielectric material layer is deposited over the substrate 106, a patterned masking layer (e.g., a photoresist layer, a hard masking layer) may be formed on the dielectric material layer, and the dielectric material layer may be etched to form portions 214, 218, 220, and / or 224 of the gate dielectric layer 208. In some embodiments, a patterned masking layer is formed on the substrate 106, and portions 214, 218, 220, and / or 224 of the gate dielectric layer 208 are deposited based on the pattern in the masking layer.

[0101] Portions 214, 218, 220 and / or 224 may be formed at the edge portion 238 of the active region 202. Furthermore, two or more of portions 214, 218, 220 and / or 224 may be formed of the same dielectric material and may have substantially the same k value.

[0102] like Figures 3H to 3J As shown, portions 226 and / or 230 of the gate dielectric layer 208 may be formed over the active region 202 of the substrate 106. In some embodiments, a dielectric material layer is deposited over the substrate 106, a patterned masking layer (e.g., a photoresist layer, a hard masking layer) may be formed on the dielectric material layer, and the dielectric material layer may be etched to form portions 226 and / or 230 of the gate dielectric layer 208. In some embodiments, a patterned masking layer is formed on the substrate 106, and portions 226 and / or 230 of the gate dielectric layer 208 are deposited based on a pattern in the masking layer.

[0103] Portions 226 and / or 230 may be formed at the central portion 240 of the active region 202. Furthermore, portions 226 and 230 may be formed of the same dielectric material and may have substantially the same k-value. Portion 226 may be formed such that portion 226 is laterally located in the y-direction between portions 214 and 220. Portion 230 may be formed such that portion 230 is laterally located in the y-direction between portions 218 and 224. In some embodiments, portions 226 and / or 230 may be formed after portions 214, 218, 220 and / or 224. In some embodiments, portions 214, 218, 220 and / or 224 may be formed after portions 226 and / or 230.

[0104] like Figure 3KAs shown, portions 216 and 222 of the gate dielectric layer 208 may be formed over the active region 202 of the substrate 106. In some embodiments, a dielectric material layer is deposited over the substrate 106, a patterned masking layer (e.g., a photoresist layer, a hard masking layer) may be formed on the dielectric material layer, and the dielectric material layer may be etched to form portions 216 and / or 222 of the gate dielectric layer 208. In some embodiments, a patterned masking layer is formed on the substrate 106, and portions 216 and / or 222 of the gate dielectric layer 208 are deposited based on the pattern in the masking layer.

[0105] Portions 216 and / or 222 may be formed at the edge portion 238 of the active region 202. Furthermore, portions 216 and 222 may be formed of the same dielectric material and may have substantially the same k-value. Portion 216 may be formed such that portion 216 is laterally located in the x-direction between portions 214 and 218. Portion 222 may be formed such that portion 222 is laterally located in the x-direction between portions 220 and 224. In some embodiments, portions 216 and / or 218 may be formed after portions 214, 218, 220, 224, 226, and / or 230. In some embodiments, portions 214, 218, 220, 224, 226, and / or 230 may be formed after portions 216 and / or 222.

[0106] like Figure 3L and Figure 3M As shown, a portion 228 of the gate dielectric layer 208 may be formed over the active region 202 of the substrate 106. In some embodiments, a dielectric material layer is deposited over the substrate 106, a patterned masking layer (e.g., a photoresist layer, a hard masking layer) is formed on the dielectric material layer, and the dielectric material layer is etched to form a portion 228 of the gate dielectric layer 208. In some embodiments, a patterned masking layer is formed on the substrate 106, and a portion 228 of the gate dielectric layer 208 is deposited based on a pattern in the masking layer.

[0107] Part 228 may be formed at the central part 240 of the active region 202. Part 228 may be formed such that part 228 is laterally located between parts 216 and 222 along the y-direction. Furthermore, part 228 may be formed such that part 228 is laterally located between parts 226 and 230 along the x-direction. In some embodiments, part 228 may be formed after parts 214, 216, 218, 220, 222, 224, 226, and / or 230. In some embodiments, parts 214, 216, 218, 220, 222, 224, 226, and / or 230 may be formed after part 228.

[0108] like Figures 3N to 3PAs shown, a gate structure 206 may be formed over a gate dielectric layer 208. The gate structure 206 may extend along the substrate 106 in the y-direction. A deposition tool may be used to deposit a material layer of the gate structure 206 using PVD, CVD, ALD, electroplating, and / or another suitable deposition technique. The material layer may be etched (e.g., using an etching tool) to define the gate structure 206.

[0109] In some implementations, a dummy gate structure is formed in place of the gate structure 206. In these implementations, the dummy gate structure can be removed after the source / drain regions of the integrated circuit device 108 have been formed. This can be referred to as a gate replacement process. The gate structure 206 can be formed in the space left after the dummy gate structure is removed.

[0110] The sidewall spacers 234 can be deposited using CVD, ALD, PVD, and / or another type of deposition technique (e.g., using a deposition tool). In some implementations, a sidewall spacer layer is deposited on the sidewalls of the gate structure 206 and along the surface of the substrate 106. The sidewall spacer layer can then be etched using an etching tool to define the sidewall spacers 234.

[0111] like Figure 3Q and Figure 3R As shown, source / drain regions 204a and 204b can be formed in the substrate 106. Source / drain region 204a can be formed on a first side of the gate structure 206, and source / drain region 204b can be formed on a second side of the gate structure 206 opposite to the first side. Therefore, the gate structure 206 is laterally located between source / drain regions 204a and 204b along the x-direction. This allows the gate structure 206 to selectively control the conductivity of the channel region located between source / drain regions 204a and 204b in the substrate 106.

[0112] In some implementations, source / drain regions 204a and 204b can be formed by doping portions of substrate 106. For example, a first portion of substrate 106 may be doped with one or more types of dopants (e.g., n-type dopants, p-type dopants) to form source / drain regions 204a, and a second portion of substrate 106 may be doped with one or more types of dopants (e.g., n-type dopants, p-type dopants) to form source / drain regions 204b. Dopant ions can be implanted to the first and / or second portions of substrate 106 using an ion implantation tool to form source / drain regions 204a and / or source / drain regions 204b. Alternatively and / or another doping technique, such as diffusion, can be used to form source / drain regions 204a and 204b.

[0113] In some embodiments, source / drain regions 204a and 204b are formed by epitaxial growth of source / drain regions 204a and 204b in a groove in substrate 106. The substrate 106 can be etched using an etching tool to form the groove in the substrate 106. The etching operation may be referred to as a strained source / drain (SSD) etching operation, and the groove may be referred to as a strained source / drain groove. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique.

[0114] Source / drain regions 204a and 204b can be formed in a trench using a deposition tool. The deposition tool can be used to form source / drain regions 204a and 204b by epitaxial growth, wherein an epitaxial material layer is deposited in the trench, such that a semiconductor material layer is formed by epitaxial growth with a specific crystal orientation.

[0115] The materials used to form the source / drain regions 204a and 204b (e.g., silicon (Si), gallium (Ga), or another type of semiconductor material) may be doped with p-type dopants (e.g., dopants that include electron acceptor atoms that create pores in the material), n-type dopants (e.g., dopants that include electron donor atoms that generate mobile electrons in the material), and / or another type of dopant. The material can be doped by adding impurities (e.g., p-type dopants, n-type dopants) to the source gas used during epitaxial operations. Examples of p-type dopants that can be used in epitaxial operations include boron (B) or germanium (Ge), etc. Examples of n-type dopants that can be used in epitaxial operations include phosphorus (P) or arsenic (As), etc.

[0116] like Figure 3R As further shown, metal silicide layers 236a and 236b can be formed on source / drain regions 204a and 204b, respectively. A metal silicide deposition process can be performed to form the metal silicide layers 236a and 236b. The metal silicide deposition process may include depositing a metal material (e.g., titanium (Ti), cobalt (Co), ruthenium (Ru)) layer on the source / drain regions 204a and 204b using a deposition tool, followed by an annealing operation to allow the metal material to diffuse into the top surfaces of the source / drain regions 204a and 204b to form the metal silicide layers 236a and 236b. In some embodiments, another technique is used to form the metal silicide layers 236a and 236b.

[0117] like Figure 3S and Figure 3TAs shown, a dielectric layer 110 may be formed over and / or on the integrated circuit device 108. Deposition tools may be used to deposit the dielectric layer 110 using PVD, CVD, ALD, oxidation, and / or other suitable deposition techniques. In some embodiments, a planarization tool is used to perform a chemical-mechanical planarization (CMP) operation to planarize the dielectric layer 110.

[0118] like Figures 3U to 3W As shown, contact structure 112a may be formed above source / drain region 204a, such that contact structure 112a rests on metal silicide layer 236a on source / drain region 204a. Contact structure 112b may be formed above source / drain region 204b, such that contact structure 112b rests on metal silicide layer 236b on source / drain region 204b. Contact structure 112c may be formed above gate structure 206, such that contact structure 112c rests on gate structure 206.

[0119] Contact structures 112a-112c may be formed in grooves in the dielectric layer 110. For example, a groove may be formed above the source / drain region 204a to expose the metal silicide layer 236a on the source / drain region 204a. Alternatively, a groove may be formed above the source / drain region 204b to expose the metal silicide layer 236b on the source / drain region 204b. Furthermore, a groove may be formed above the gate structure 206 to expose the gate structure 206.

[0120] In some embodiments, the pattern in the photoresist layer is used to form grooves in the dielectric layer 110. In these embodiments, the photoresist layer can be formed over the dielectric layer 110 using a deposition tool. The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch through the dielectric layer 110 to form grooves. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another etching technique. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based groove formation.

[0121] Deposition tools can be used to deposit contact structures 112a-112c using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. Contact structures 112a-112c can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then contact structures 112a-112c are deposited on the seed layer. In some embodiments, a liner is deposited in a trench, and contact structures 112a-112c are deposited on the liner in the trench. The liner may include a barrier liner, an adhesion liner, and / or another suitable liner. Examples of liner materials include tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liner materials. In some embodiments, after depositing contact structures 112a-112c, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize the contact structures 112a-112c.

[0122] As mentioned above, providing Figures 3A to 3W As an example, other examples may be similar to the reference. Figures 3A to 3W The instances described are different.

[0123] Figures 4A to 4C This is a schematic diagram of an exemplary embodiment 400 of the integrated circuit device 108 described herein. In exemplary embodiment 400, the integrated circuit device 108 includes a high-voltage transistor structure. Figure 4A A top view illustrating the integrated circuit device 108. Figure 4B Description of integrated circuit device 108 along Figure 4A An illustrative cross-section of line AA (e.g., along the x-direction) in the diagram. Figure 4C Description of integrated circuit device 108 along Figure 4A An illustrative cross-sectional view of line BB (e.g., along the y-direction) in the diagram.

[0124] like Figures 4A to 4C As shown, an exemplary embodiment 400 of the integrated circuit device 108 includes... Figures 2A to 2CThe exemplary embodiment 200 of the integrated circuit device 108 uses a combination and arrangement of layers and / or structures similar to those in the example embodiment 400. However, in the example embodiment 400 of the integrated circuit device 108, portion 226 of the gate dielectric layer 208 has a material composition that differs from that of portion 230 of the gate dielectric layer 208. In the central portion of the active region 202, the critical voltage may be asymmetrical along the x-direction between the source / drain regions 204a and 204b. For example, if the gate dielectric layer 208 has a uniform k value between the source / drain regions 204a and 204b, the critical voltage near the source / drain region 204a may be higher than that near the source / drain region 204b. Therefore, portions 226 and 230 may have different material compositions, such that portions 226 and 230 have different k values ​​to compensate for the originally asymmetrical critical voltage, thereby achieving a substantially uniform critical voltage between the source / drain regions 204a and 204b.

[0125] As mentioned above, providing Figures 4A to 4C As an example, other examples may be similar to the reference. Figures 4A to 4C The instances described are different.

[0126] Figures 5A to 5C This is a schematic diagram of an exemplary embodiment 500 of the integrated circuit device 108 described herein. In exemplary embodiment 500, the integrated circuit device 108 includes a high-voltage transistor structure. Figure 5A A top view illustrating the integrated circuit device 108. Figure 5B Description of integrated circuit device 108 along Figure 5A An illustrative cross-section of line AA (e.g., along the x-direction) in the diagram. Figure 5C Description of integrated circuit device 108 along Figure 5A An illustrative cross-sectional view of line BB (e.g., along the y-direction) in the diagram.

[0127] like Figures 5A to 5C As shown, an exemplary embodiment 500 of the integrated circuit device 108 includes... Figures 5A to 5C The exemplary embodiment 200 of the integrated circuit device 108 is similar to the combination and arrangement of layers and / or structures. However, in the exemplary embodiment 500 of the integrated circuit device 108, the gate structure 206 is a composite gate structure, and the gate dielectric layer 208 is a composite gate dielectric layer.

[0128] like Figure 5AAs shown, the gate structure 206 is a composite gate structure, comprising multiple doped regions with different work function values. The work function value refers to the bandgap energy level of the gate structure 206 (in electron volts (eV)). The critical voltage of the integrated circuit device 108 can be based on the work function values ​​of the gate structure 206 and the substrate 106. The greater the difference between the work function values ​​of the gate structure 206 and the substrate 106, the higher the critical voltage of the integrated circuit device 108. Conversely, the smaller the difference between the work function values ​​of the gate structure 206 and the substrate 106, the lower the critical voltage of the integrated circuit device 108. Therefore, the gate structure 206 with multiple doped regions having different work function values ​​can compensate for the subcritical peak effect at the edge of the active region 202 of the integrated circuit device 108, because the work function value can be selected to adjust the critical voltage (V) at the edge of the active region 202. t This is in the vicinity of the source / drain regions 204a and 204b. This enables the integrated circuit device 108 to achieve a higher threshold voltage (V) across the entire active region 202. t Uniformity.

[0129] These doped regions of the gate structure 206 can be arranged into a grid, which includes a plurality of columns 502a to 502c arranged along the x direction and extending along the y direction, and a plurality of rows 504a to 504c arranged along the y direction and extending along the x direction. Figure 5A The number of columns, rows, and portions shown are examples, and other numbers are within the scope of this disclosure.

[0130] Row 504a may include doped regions 506, 508, and 510 of gate structure 206. Row 504b may include doped regions 512, 516, and 518 of gate structure 206. Row 504c may be located between rows 504a and 504b in the y-direction and may include doped regions 518, 520, and 522. Rows 504a and 504b may be located at the outer edge of the active region 202 of integrated circuit device 108, and the material composition of doped regions 506, 508, 510, 512, 514, and 516 included in rows 504a and 504b may be selected to adjust the critical voltage of integrated circuit device 108 at the edge of active region 202. The material composition of doped regions 518, 520, and 522 included in row 504c may be selected to adjust the critical voltage of integrated circuit device 108 at the center of active region 202.

[0131] Doped regions 506, 508, and 510 in row 504a can be arranged along the x-direction, and doped region 508 can be laterally located between doped regions 506 and 510 along the x-direction. Doped regions 512, 514, and 516 in row 504b can be arranged along the x-direction, and doped region 514 can be laterally located between doped regions 512 and 516 along the x-direction. Doped regions 518, 520, and 522 in row 504c can be arranged along the x-direction, and doped region 520 can be laterally located between doped regions 518 and 522 along the x-direction.

[0132] Column 502a may include doped regions 506, 512, and 518 of gate structure 206. Column 502b may include doped regions 510, 516, and 522 of gate structure 206. Column 502c may be located between columns 502a and 502b in the x-direction and may include doped regions 508, 514, and 520. Columns 502a and 502b may be located at opposite ends of the channel region below the gate structure 206 of integrated circuit device 108, and the material composition of the doped regions 506, 510, 512, 516, 518, and 522 included in columns 502a and 502b may be selected to adjust the critical voltage of integrated circuit device 108 at both ends of the channel region. The material composition of the doped regions 508, 514, and 520 included in column 502c may be selected to adjust the critical voltage of integrated circuit device 108 at the center of the channel region.

[0133] Doped regions 506, 512, and 518 in column 502a can be arranged along the y-direction, and doped region 518 can be laterally located between doped regions 506 and 512 along the y-direction. Doped regions 510, 516, and 522 in column 502b can be arranged along the y-direction, and doped region 522 can be laterally located between doped regions 510 and 516 along the y-direction. Doped regions 508, 514, and 520 in column 502c can be arranged along the y-direction, and doped region 520 can be laterally located between doped regions 508 and 514 along the y-direction.

[0134] Two or more doped regions 506-522 may have substantially the same work function value. For example, doped regions 506, 510, 512, and 516 may have substantially the same work function value. These doped regions 506, 510, 512, and 516 may comprise the same material or the same material composition to achieve substantially the same work function value. For example, doped regions 506, 510, 512, and 516 may each comprise polysilicon doped with the same type of dopant (e.g., n-type dopant, p-type dopant), and / or may be doped with substantially the same concentration of a particular dopant, such that doped regions 506, 510, 512, and 516 have substantially the same work function value. For example, doped regions 506, 510, 512, and 516 may each be doped with substantially the same concentration of boron (B) (p-type dopant). As another example, doped regions 506, 510, 512, and 516 may each be doped with substantially the same concentration of phosphorus (P) (n-type dopant). Similarly, doped regions 508 and 514 may have substantially the same work function value and may include the same material or the same material composition (e.g., the same doped material with substantially the same doping concentration), and / or doped regions 518 and 522 may have substantially the same work function value and may include the same material or the same material composition (e.g., the same doped material with substantially the same doping concentration).

[0135] The work function values ​​of doped regions 506, 510, 512, and 516 may differ from those of doped regions 518 and 522 to compensate for field accumulation and / or surface doping concentration at the edges of active region 202. For example, the work function values ​​of doped regions 506, 510, 512, and 516 may be greater than those of doped regions 518 and 522. The larger work function values ​​of doped regions 506, 510, 512, and 516 provide a critical voltage (V0) at the edges of active region 202. t The work function value in doped regions 506, 510, 512, and 516 is larger than that in doped regions 518 and 522, resulting in greater critical voltage uniformity in active region 202 along the y-direction. Therefore, doped regions 506, 510, 512, and 516 may be composed of a material (e.g., polysilicon) doped with dopants having higher work function values ​​than those in doped regions 518 and 520. Additionally and / or alternatively, doped regions 506, 510, 512, and 516 may include higher doping concentrations than those in doped regions 518 and 520.

[0136] Similarly, the work function values ​​of doped regions 508 and 514 may differ from that of doped region 520 to compensate for field accumulation and / or surface doping concentration at the edges of active region 202. For example, the work function values ​​of doped regions 508 and 514 may be greater than that of doped region 520, which provides greater critical voltage uniformity in active region 202 along the y-direction than when the work function values ​​of doped regions 508 and 514 are approximately equal to those of doped region 520. Therefore, doped regions 508 and 514 may be composed of a material (e.g., polysilicon) doped with dopants having a higher work function value than that of the doped material in doped region 520. Additionally and / or alternatively, doped regions 508 and 514 may include a higher doping concentration than that of doped region 520.

[0137] Along the x-direction (e.g., along the length of the channel region of integrated circuit device 108), the work function values ​​of doped regions 506, 510, 512, and 516 may differ from those of doped regions 508 and 514 to compensate for field accumulation and / or surface doping concentration at the ends of the channel region. For example, the work function values ​​of doped regions 506, 510, 512, and 516 may be greater than those of doped regions 508 and 514. Therefore, at the edge of active region 202, this provides greater critical voltage uniformity along the x-direction throughout the channel region than when the work function values ​​of doped regions 506, 510, 512, and 516 are approximately equal to those of doped regions 508 and 514. Therefore, doped regions 506, 510, 512, and 516 may be composed of a material (e.g., polysilicon) doped with dopants having higher work function values ​​than the doped material (e.g., doped polysilicon) of doped regions 508 and 514. Additionally and / or alternatively, doped regions 506, 510, 512 and 516 may include a higher doping concentration than doped regions 508 and 514.

[0138] Similarly, the work function values ​​of doped regions 518 and 522 may differ from that of doped region 520 to compensate for field accumulation and / or surface doping concentration at both ends of the channel region. For example, the work function values ​​of doped regions 518 and 522 may be greater than that of doped region 522, which provides greater critical voltage uniformity in the channel region along the x-direction than when the work function values ​​of doped regions 518 and 522 are approximately equal to that of doped region 522. Therefore, doped regions 518 and 522 may be composed of a material (e.g., polysilicon) doped with dopants having a higher work function value than that of the doped material (e.g., doped polysilicon) of doped region 520. Additionally and / or alternatively, doped regions 518 and 522 may include a higher doping concentration than that of doped region 520.

[0139] The arrangement, work function value, and material composition of the doped regions 506-522 are examples, and other arrangements, work function values, and material compositions of the doped regions 506-522 are within the scope of this disclosure. The doped regions 506-522 of the gate dielectric layer 208 may include various types of dopants (e.g., p-type dopants, such as boron (B) and / or gallium (Ga); n-type dopants, such as arsenic (As) and / or phosphorus (P)) and / or various doping concentrations.

[0140] like Figure 5B As shown, the doped region 518 of the gate structure 206 (and Figure 5B The doped regions 506 and 512 (not shown in the cross-section) are closest to the source / drain region 204a. The doped regions 522 (and...) of the gate structure 206... Figure 5B The doped regions 510 and 516, which are not shown in the cross-section, are closest to the source / drain region 204b.

[0141] like Figure 5C As shown, the doped regions 506 and 512 of the gate structure 206 may be located above the edge portion 238 of the active region 202 along the y-direction, and the doped region 518 of the gate dielectric layer 208 may be located above the center portion 240 of the active region 202. The material, dopant type, dopant, and / or doping concentration of the doped regions 506 and 512 may be selected to give the doped regions 506 and 512 specific work function values ​​to adjust the critical voltage of the integrated circuit device 108 in the edge portion 238. Doped regions 508, 510, 514, and 516 ( Figure 5C The material, dopant type, dopant and / or doping concentration (not shown in the cross-section) can be similarly selected so that the doped regions 508, 510, 514 and 516 have work function values ​​to adjust the critical voltage of the integrated circuit device 108 in the edge portion 238.

[0142] The material, dopant type, dopant, and / or doping concentration of doped region 518 can be selected to give doped region 518 a specific work function value to adjust the critical voltage of integrated circuit device 108 in central portion 240. Doped regions 520 and 522 ( Figure 5C The material, dopant type, dopant and / or doping concentration (not shown in the cross-section) can be similarly selected to give doped regions 520 and 522 work function values ​​to adjust the critical voltage of integrated circuit device 108 in central portion 240.

[0143] As mentioned above, providing Figures 5A to 5C As an example, other examples may be similar to the reference. Figures 5A to 5C The instances described differ. For example, although Figures 5A to 5CThe gate structure 206 is described as having doped regions 506-522 of doped polysilicon, but the work function values ​​of the doped regions 506-522 can be implemented as regions of metals with different work functions. Examples of work function metals used to adjust the work function values ​​of different regions of the gate structure 206 may include p-type work function metals (e.g., metals that increase the work function of the gate structure 206, such as tungsten (W), cobalt (Co), titanium nitride (TiN), and / or tungsten nitride (WN)) and / or n-type work function metals (e.g., metals that decrease the work function of the gate structure 206, such as titanium aluminum (TiAl) and / or titanium aluminum carbon (TiAlC)).

[0144] Figures 6A to 6Z This is a schematic diagram of an exemplary embodiment 600 of an integrated circuit device 108 comprising the composite gate structure 206 described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, ion implantation tools, planarization tools, and / or another suitable semiconductor processing tool) may be used to perform one or more of the described operations.

[0145] See Figures 6A to 6C One or more of the operations in the exemplary implementation 300 can be performed together with the substrate 106 of the semiconductor device 100. The substrate 106 may also be provided in the form of a semiconductor wafer or another type of substrate.

[0146] like Figure 6D and Figure 6E As shown, an isolation region 232 can be formed in the substrate 106. The isolation region 232 can define the active region 202 of the integrated circuit device 108. This can be achieved by combining... Figures 3A to 3W One or more instances described form an isolated region 232.

[0147] like Figures 6F to 6H As shown, a gate dielectric layer 208 may be formed over the active region 202 of the substrate 106. Deposition tools may be used to deposit the gate dielectric layer 208 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The gate dielectric layer 208 may be deposited in one or more deposition operations. In some embodiments, a planarization tool may be used to perform a planarization operation (e.g., CMP operation) to planarize the gate dielectric layer 208 after deposition.

[0148] like Figures 6I to 6KAs shown, a gate structure 206 may be formed over a gate dielectric layer 208. The gate structure 206 may extend along the substrate 106 in the y-direction. Deposition tools may be used to deposit a material layer for the gate structure 206 using PVD, CVD, ALD, electroplating, and / or another suitable deposition technique. The material layer may be etched (e.g., using an etching tool) to define the gate structure 206. Sidewall spacers 234 may be deposited (e.g., using a deposition tool) using CVD, ALD, PVD, and / or another type of deposition technique. In some embodiments, a sidewall spacer layer is deposited on the sidewalls of the gate structure 206 and along the surface of the substrate 106. The sidewall spacer layer may then be etched using an etching tool to define the sidewall spacers 234.

[0149] like Figure 6L and Figure 6M As shown, doped regions 506, 510, 512, and 516 may be formed in the gate structure 206. Dopant can be implanted into the gate structure 206 using an ion implantation tool to form doped regions 506, 510, 512, and 516. In some embodiments, an implantation mask is used to define the ion-doped portions of the gate structure 206 to form doped regions 506, 510, 512, and 516. Doped regions 506, 510, 512, and / or 516 may be formed at the edge portion 238 of the active region 202. Furthermore, two or more of the doped regions 506, 510, 512, and / or 516 may be of the same dopant type, dopant, and / or the same doping concentration to have substantially the same work function value.

[0150] like Figures 6N to 6P As shown, doped regions 518 and 522 can be formed in the gate structure 206. Dopant can be implanted into the gate structure 206 using an ion implantation tool to form the doped regions 518 and 522. In some embodiments, an implantation mask is used to define the ion-doped portions of the gate structure 206 to form the doped regions 518 and 522.

[0151] Doped regions 518 and / or 522 may be formed at the central portion 240 of active region 202. Furthermore, doped regions 518 and 522 may be formed of the same dopant type, dopant, and / or the same doping concentration to have substantially the same work function value. Doped region 518 may be formed such that it is laterally located along the y-direction between doped regions 506 and 512. Doped region 522 may be formed such that it is laterally located along the y-direction between doped regions 510 and 516.

[0152] In some embodiments, doped regions 518 and / or 522 are formed after doped regions 506, 510, 512 and / or 516. In some embodiments, doped regions 518 and / or 522 are formed before doped regions 506, 510, 512 and / or 516.

[0153] like Figure 6Q As shown, doped regions 508 and 514 can be formed in the gate structure 206. Dopant can be implanted into the gate structure 206 using an ion implantation tool to form doped regions 508 and 514. In some embodiments, an implantation mask is used to define the ion-doped portions of the gate structure 206 to form doped regions 508 and 514.

[0154] Doped regions 508 and / or 514 may be formed at the edge portion 238 of the active region 202. Furthermore, doped regions 508 and / or 514 may be formed of the same dopant type, dopant, and / or the same doping concentration to have substantially the same work function value. Doped region 508 may be formed such that it is laterally located between doped regions 506 and 510 along the x-direction. Doped region 514 may be formed such that it is laterally located between doped regions 512 and 516 along the x-direction.

[0155] In some embodiments, doped regions 508 and / or 514 are formed after doped regions 506, 510, 512, 516, 518 and / or 522. In some embodiments, doped regions 508 and / or 514 are formed before doped regions 506, 510, 512, 516, 518 and / or 522.

[0156] like Figure 6R and Figure 6S As shown, a doped region 520 may be formed in the gate structure 206. An ion-implanting tool can be used to implant dopant into portions of the gate structure 206 to form the doped region 520. In some embodiments, a implantation mask is used to define the ion-doped portions of the gate structure 206 to form the doped region 520.

[0157] The doped region 520 may be formed at the center portion 240 of the active region 202. The doped region 520 may be formed such that the doped region 520 is laterally located between the doped regions 518 and 522 along the x-direction. Furthermore, the doped region 520 may be formed such that the doped region 520 is laterally located between the doped regions 508 and 514 along the y-direction.

[0158] In some embodiments, doped region 520 is formed after doped regions 506, 508, 510, 512, 514, 516, 518 and / or 522. In some embodiments, doped region 520 is formed before doped regions 506, 508, 510, 512, 514, 516, 518 and / or 522.

[0159] like Figure 6T and Figure 6U As shown, source / drain regions 204a and 204b can be formed in the substrate 106. Figure 6U As further shown, metal silicide layers 236a and 236b can be formed on source / drain regions 204a and 204b, respectively. Source / drain regions 204a and 204b and metal silicide layers 236a and 236b can be bonded to... Figure 3Q and Figure 3R Related descriptions are formed in a similar manner.

[0160] like Figure 6V and Figure 6W As shown, a dielectric layer 110 can be formed on the integrated circuit device 108. The dielectric layer 110 can be bonded to... Figure 3S and Figure 3T Related descriptions are formed in a similar manner.

[0161] like Figures 6X to 6Z As shown, contact structure 112a can be formed above source / drain region 204a, such that contact structure 112a rests on metal silicide layer 236a on source / drain region 204a. Contact structure 112b can be formed above source / drain region 204b, such that contact structure 112b rests on metal silicide layer 236b on source / drain region 204b. Contact structure 112c can be formed above gate structure 206, such that contact structure 112c rests on gate structure 206. Contact structures 112a-112c can be coupled to... Figures 3U to 3W Related descriptions are formed in a similar manner.

[0162] As mentioned above, providing Figures 6A to 6Z As an example, other examples may be similar to the reference. Figures 6A to 6Z The instances described are different.

[0163] Figures 7A to 7C This is a schematic diagram of an exemplary embodiment 700 of the integrated circuit device 108 described herein. In exemplary embodiment 700, the integrated circuit device 108 includes a high-voltage transistor structure. Figure 7A A top view illustrating the integrated circuit device 108. Figure 7B Description of integrated circuit device 108 along Figure 7A An illustrative cross-section of line AA (e.g., along the x-direction) in the diagram. Figure 7C Description of integrated circuit device 108 along Figure 7A An illustrative cross-sectional view of line BB (e.g., along the y-direction) in the diagram.

[0164] like Figures 7A to 7C As shown, an exemplary embodiment 700 of the integrated circuit device 108 includes... Figures 5A to 5C The exemplary embodiment 200 of the integrated circuit device 108 uses a combination and arrangement of layers and / or structures similar to those in the example embodiment 700. However, in the exemplary embodiment 700 of the integrated circuit device 108, the doped region 518 of the gate structure 206 has a different material composition (e.g., doping concentration, dopant type, dopant material) than the doped region 522 of the gate structure 206. In the central portion of the active region 202, the critical voltage may be asymmetrical along the x-direction between the source / drain regions 204a and 204b. For example, if the gate structure 206 has a work function value between the source / drain regions 204a and 204b, the critical voltage near the source / drain region 204a may be higher than the critical voltage near the source / drain region 204b. Therefore, the material compositions of the doped regions 518 and 522 can be different, such that the doped regions 518 and 528 have different work function values ​​to compensate for the originally asymmetrical critical voltage, thereby achieving a substantially uniform critical voltage between the source / drain regions 204a and 204b.

[0165] As mentioned above, providing Figures 7A to 7C As an example, other examples may be similar to the reference. Figures 7A to 7C The instances described are different.

[0166] Figures 8A to 8C This is a schematic diagram of an exemplary embodiment 800 of the integrated circuit device 108 described herein. In exemplary embodiment 800, the integrated circuit device 108 includes a high-voltage transistor structure. Figure 8A A top view illustrating the integrated circuit device 108. Figure 8B Description of integrated circuit device 108 along Figure 8A An illustrative cross-section of line AA (e.g., along the x-direction) in the diagram. Figure 8C Description of integrated circuit device 108 along Figure 8A An illustrative cross-sectional view of line BB (e.g., along the y-direction) in the diagram.

[0167] like Figures 8A to 8C As shown, an exemplary embodiment 800 of the integrated circuit device 108 includes... Figures 2A to 2CThe exemplary embodiment 200 of the integrated circuit device 108 uses a similar combination and arrangement of layers and / or structures. However, in the exemplary embodiment 800 of the integrated circuit device 108, the gate structure 206 is a composite gate structure, except that the gate dielectric layer 208 is a composite gate dielectric layer. The inclusion of the composite gate dielectric layer and the composite gate structure allows for further threshold voltage adjustment of the integrated circuit device 108 via k-value adjustment in the gate dielectric layer 208 and work function value adjustment in the gate structure 206.

[0168] like Figure 8A As shown, the gate structure 206 is a composite gate structure, wherein the gate structure 206 includes multiple doped regions 506-522 with different work function values. These doped regions 506-522 of the gate structure 206 can be arranged in a grid, which includes multiple columns 502a-502c arranged along the x-direction and extending along the y-direction, and multiple rows 504a-504c arranged along the y-direction and extending along the x-direction. The work function values ​​of the doped regions 506-522 can be determined according to the bonding... Figures 5A to 5C Choose from examples described above.

[0169] like Figure 8A As further shown, columns 510a to 510c of the gate structure 206 may be located above columns 210a to 210c of the gate dielectric layer 208, respectively. Rows 512a to 512c of the gate structure 206 may be located above rows 212a to 212c of the gate dielectric layer 208, respectively.

[0170] like Figure 8B As shown, the doped region 518 of the gate structure 206 may be located above a portion 226 of the gate dielectric layer 208, the doped region 520 of the gate structure 206 may be located above a portion 228 of the gate dielectric layer 208, and the doped region 522 of the gate structure 206 may be located above a portion 230 of the gate dielectric layer 208.

[0171] like Figure 8C As shown, the doped region 506 of the gate structure 206 may be located above a portion 214 of the gate dielectric layer 208, the doped region 512 of the gate structure 206 may be located above a portion 220 of the gate dielectric layer 208, and the doped region 518 of the gate structure 206 may be located above a portion 226 of the gate dielectric layer 208.

[0172] Furthermore, the doped region 508 of the gate structure 206 may be located above a portion 216 of the gate dielectric layer 208, the doped region 510 of the gate structure 206 may be located above a portion 218 of the gate dielectric layer 208, the doped region 514 of the gate structure 206 may be located above a portion 222 of the gate dielectric layer 208, and the doped region 516 of the gate structure 206 may be located above a portion 224 of the gate dielectric layer 208.

[0173] As mentioned above, providing Figures 8A to 8C As an example, other examples may be similar to the reference. Figures 8A to 8C The instances described are different.

[0174] Figure 9 This is a schematic diagram of an exemplary embodiment 900 of the integrated circuit devices 108a and 108b described herein. In exemplary embodiment 900, integrated circuit devices 108a and 108b each include a high-voltage transistor structure. Integrated circuit device 108a may include a p-type high-voltage transistor structure (e.g., a p-type metal-oxide-semiconductor (PMOS) high-voltage transistor), while integrated circuit device 108b may include an n-type high-voltage transistor structure (e.g., an n-type metal-oxide-semiconductor (NMOS) high-voltage transistor).

[0175] Figure 9 A top view illustrating integrated circuit devices 108a and 108b. (See attached image.) Figure 9 As shown, each of the integrated circuit devices 108a and 108b may include a composite gate structure 206 having a plurality of doped regions 506-522 having two or more different work function values, and / or a composite gate dielectric layer 208 having a plurality of portions 214-230 having two or more different k values. The work function values ​​of the doped regions 506-522 of the integrated circuit device 108a and / or the k values ​​of the portions 214-230 of the integrated circuit device 108a may be selected to achieve a substantially uniform and low threshold voltage (e.g., the work function of the gate structure 206 and the valence band (E)). V The work function values ​​of the doped regions 506-522 of the integrated circuit device 108b and / or the k values ​​of portions 214-230 of the integrated circuit device 108b can be selected to achieve a substantially uniform and low threshold voltage of the integrated circuit device 108b (e.g., the work function of the gate structure 206 and the condition band). C (the small band gap between)

[0176] As mentioned above, providing Figure 9 As an example, other examples may be similar to the reference. Figure 9 The instances described are different.

[0177] Figure 10This is a flowchart illustrating an exemplary process 1000 related to the formation of the transistor structure described herein. In some implementations, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform the process. Figure 10 One or more process blocks.

[0178] like Figure 10 As shown, process 1000 may include: forming one or more first portions (block 1010) of a gate dielectric layer of a transistor structure. For example, one or more semiconductor processing tools may be used to form one or more first portions (e.g., portions 214, 218, 220, and / or 224) of a gate dielectric layer (e.g., gate dielectric layer 208) of a transistor structure (e.g., integrated circuit device 108), as described herein. In some embodiments, one or more first portions are composed of a first material having a first k value.

[0179] like Figure 10 As further shown, process 1000 may include forming one or more second portions (block 1020) of a gate dielectric layer. For example, one or more semiconductor processing tools may be used to form one or more second portions of the gate dielectric layer (e.g., portions 226 and / or 230), as described herein. In some embodiments, one or more second portions are composed of a second material having a second k value that is different from a first k value.

[0180] like Figure 10 As further shown, process 1000 may include forming one or more third portions (block 1030) of a gate dielectric layer. For example, one or more semiconductor processing tools may be used to form one or more third portions of the gate dielectric layer (e.g., portions 216 and / or 222), as described herein. In some embodiments, one or more third portions are composed of a third material having a third k value that is different from the first and second k values.

[0181] like Figure 10 As further shown, process 1000 may include: forming a gate structure of a transistor structure over the gate dielectric layer (block 1040). For example, the gate structure of the transistor structure (e.g., gate structure 206) may be formed over the gate dielectric layer using one or more semiconductor processing tools, as described herein.

[0182] like Figure 10As further shown, process 1000 may include: forming a first source / drain region and a second source / drain region such that the first source / drain region and the second source / drain region are laterally adjacent to opposite sides of the gate structure (block 1050). For example, the first source / drain region (e.g., source / drain region 204a) and the second source / drain region (e.g., source / drain region 204b) may be formed using one or more semiconductor processing tools such that the first source / drain region and the second source / drain region are laterally adjacent to opposite sides of the gate structure, as described herein.

[0183] Process 1000 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or in conjunction with those described elsewhere in this document.

[0184] In a first embodiment, forming one or more second portions includes: a fourth portion (e.g., portion 226) forming one or more second portions, such that the fourth portion is laterally located between a first subset of one or more first portions (e.g., portions 214 and / or 220); and a fifth portion (e.g., portion 230) forming one or more second portions, such that the fifth portion is laterally located between a second subset of one or more first portions (e.g., portions 218 and / or 224).

[0185] In the second embodiment, either alone or in combination with the first embodiment, process 1000 includes forming a fourth portion (e.g., portion 228) of a gate dielectric layer, wherein the fourth portion is composed of a fourth k-value having a different k-value from the first, second, and third k-values.

[0186] In the third embodiment, the fourth portion forming the gate dielectric layer, either alone or in combination with one or more of the first and second embodiments, comprises: the fourth portion being laterally formed between a fifth portion (e.g., portion 226) of one or more second portions and a sixth portion (e.g., portion 230) of one or more second portions.

[0187] In the fourth embodiment, the fourth portion forming the gate dielectric layer, either alone or in combination with one or more of the first to third embodiments, comprises: the fourth portion being laterally formed between a seventh portion (e.g., portion 216) of one or more third portions and an eighth portion (e.g., portion 222) of one or more third portions.

[0188] In the fifth embodiment, forming a gate structure, either alone or in combination with one or more of the first to fourth embodiments, comprises: forming one or more first doped regions (e.g., doped regions 506, 510, 512, and / or 516) of the gate structure over one or more first portions of the gate dielectric layer, wherein the one or more first doped regions have a first work function value; forming one or more second doped regions (e.g., doped regions 518 and / or 522) of the gate structure over one or more second portions of the gate dielectric layer, wherein the one or more second doped regions have a second work function value different from the first work function value; and forming one or more third doped regions (e.g., doped regions 508 and / or 514) of the gate structure over one or more third portions of the gate dielectric layer, wherein the one or more third doped regions have a third work function value different from the first and second work function values.

[0189] although Figure 10 The diagram illustrates an exemplary block of process 1000, but in some implementations, process 1000 may include more... Figure 10 The blocks shown can be more blocks, fewer blocks, different blocks, or blocks with different arrangements. Alternatively, two or more blocks of process 1000 can be executed in parallel.

[0190] In this manner, a high-voltage transistor may include a composite gate dielectric layer comprising multiple regions with different dielectric constant values ​​(e.g., different k values), thereby achieving a critical voltage (Vc) on the channel region of the high-voltage transistor. t The uniformity is higher than when using a uniform gate dielectric layer. Regions with different k values ​​can be arranged along the length of the channel region between the source / drain regions of the high-voltage transistor, and / or along the width of the channel region. Using regions with different k values ​​can compensate for the subcritical hump effect at the edge of the channel region by adjusting the critical voltage at the edge of the channel region. Alternatively and / or, the critical voltage uniformity can be increased by forming the gate structure of the high-voltage transistor with multiple regions having different work function values ​​(e.g., individually or in addition to adjusting the critical voltage by regions with different k values ​​in the gate dielectric layer). Therefore, the gate structure can be called a composite gate structure. Regions with different work function values ​​in the composite gate structure can compensate for the subcritical hump effect at the edge of the channel region.

[0191] As described in more detail above, some embodiments described herein provide a transistor structure. The transistor structure includes a first source / drain region located in a substrate of a semiconductor device. The transistor structure includes a second source / drain region located in the substrate. The transistor structure includes a gate structure located above the substrate, wherein the gate structure is laterally positioned between the first source / drain region and the second source / drain region. The transistor structure includes a composite gate dielectric layer between the gate structure and the substrate, wherein the composite gate dielectric layer includes a plurality of laterally arranged portions, each portion having a different dielectric constant.

[0192] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged along a first direction in a semiconductor device. These laterally arranged portions include: a first portion having a first dielectric constant, a second portion having a second dielectric constant, and a third portion having a first dielectric constant. The first, second, and third portions are arranged along a second direction in the semiconductor device, which is approximately perpendicular to the first direction. The first and second dielectric constants are different dielectric constants.

[0193] In some embodiments, these laterally arranged portions include: a fourth portion laterally adjacent to the first portion and having a third dielectric constant; a fifth portion laterally adjacent to the second portion and having a fourth dielectric constant; and a sixth portion laterally adjacent to the third portion and having a third dielectric constant. The fourth, fifth, and sixth portions are arranged along a second direction, and the third and fourth dielectric constants are different dielectric constants.

[0194] In some implementations, the first dielectric constant, the second dielectric constant, the third dielectric constant, and the fourth dielectric constant are different dielectric constants.

[0195] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged along a first direction in a semiconductor device. The gate structure extends along a second direction in the semiconductor device between the first and second source / drain regions, the second direction being approximately perpendicular to the first direction. These laterally arranged portions include: a first portion having a first dielectric constant, a second portion having a second dielectric constant, and a third portion having a first dielectric constant. The first, second, and third portions are arranged along the first direction. The first and second dielectric constants are different dielectric constants.

[0196] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged along a first direction in a semiconductor device. The gate structure extends along a second direction in the semiconductor device between the first and second source / drain regions, the second direction being approximately perpendicular to the first direction. These laterally arranged portions include: a first portion having a first dielectric constant, a second portion having a second dielectric constant, and a third portion having a third dielectric constant. The first, second, and third portions are arranged along the first direction. The first, second, and third dielectric constants are different dielectric constants.

[0197] In some embodiments, these laterally arranged portions include: a fourth portion adjacent to a first end of the first portion and having a fourth dielectric constant, and a fifth portion adjacent to a second end of the first portion and having a fourth dielectric constant. The fourth portion, the first portion, and the fifth portion are arranged along a second direction. The first dielectric constant, the second dielectric constant, the third dielectric constant, and the fourth dielectric constant are different dielectric constants.

[0198] As described in more detail above, some embodiments described herein provide a transistor structure. The transistor structure includes a first source / drain region located in a substrate of a semiconductor device. The transistor structure includes a second source / drain region located in the substrate. The transistor structure includes a gate structure located above the substrate, wherein the gate structure is laterally positioned between the first source / drain region and the second source / drain region. The transistor structure includes a gate dielectric layer between the gate structure and the substrate, wherein the gate structure includes a plurality of laterally arranged doped regions, each doped region having a different work function value.

[0199] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged along a first direction in a semiconductor device. These laterally arranged doped regions include: a first doped region having a first work function value, a second doped region having a second work function value, and a third doped region having a first work function value. The first, second, and third doped regions are arranged along a second direction in the semiconductor device, which is approximately perpendicular to the first direction. The first and second work function values ​​are different work function values.

[0200] In some embodiments, these laterally arranged doped regions include: a fourth doped region laterally adjacent to the first doped region and having a third work function value; a fifth doped region laterally adjacent to the second doped region and having a fourth work function value; and a sixth doped region laterally adjacent to the third doped region and having a third work function value. The fourth, fifth, and sixth doped regions are arranged along a second direction. The third and fourth work function values ​​are different work function values.

[0201] In some implementations, the first work function value, the second work function value, the third work function value, and the fourth work function value are different work function values.

[0202] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged along a first direction in a semiconductor device. The gate structure extends along a second direction in the semiconductor device between the first and second source / drain regions, the second direction being approximately perpendicular to the first direction. These laterally arranged doped regions include: a first doped region having a first work function value, a second doped region having a second work function value, and a third doped region having a first work function value. The first, second, and third doped regions are arranged along the first direction. The first and second work function values ​​are different work function values.

[0203] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged along a first direction in a semiconductor device. The gate structure extends along a second direction in the semiconductor device between the first and second source / drain regions, the second direction being approximately perpendicular to the first direction. These laterally arranged doped regions include: a first doped region having a first work function value, a second doped region having a second work function value, and a third doped region having a third work function value. The first, second, and third doped regions are arranged along the first direction. The first, second, and third work function values ​​are different work function values.

[0204] In some embodiments, these laterally arranged doped regions include: a fourth doped region adjacent to a first end of a first doped region and having a fourth work function value, and a fifth doped region adjacent to a second end of the first doped region and having a fourth work function value. The fourth doped region, the first doped region, and the fifth doped region are arranged along a second direction. The first work function value, the second work function value, the third work function value, and the fourth work function value are different work function values.

[0205] As described in more detail above, some embodiments described herein provide a method for forming a transistor structure. The method includes: forming one or more first portions of a gate dielectric layer of the transistor structure, wherein the one or more first portions are composed of a first material having a first dielectric constant. The method includes: forming one or more second portions of the gate dielectric layer, wherein the one or more second portions are composed of a second material having a second dielectric constant, which is different from the first dielectric constant. The method includes: forming one or more third portions of the gate dielectric layer, wherein the one or more third portions are composed of a third material having a third dielectric constant, which is different from both the first and second dielectric constants. The method includes: forming a gate structure of the transistor structure above the gate dielectric layer. The method includes: forming a first source / drain region and a second source / drain region such that the first source / drain region and the second source / drain region are laterally adjacent to opposite sides of the gate structure.

[0206] In some embodiments, forming one or more second portions includes: forming a fourth portion of the one or more second portions such that the fourth portion is laterally located between a first subset of the one or more first portions; and forming a fifth portion of the one or more second portions such that the fifth portion is laterally located between a second subset of the one or more first portions.

[0207] In some embodiments, the method further includes forming a fourth portion of a gate dielectric layer, wherein the fourth portion is composed of a material having a fourth dielectric constant, which is different from the first dielectric constant, the second dielectric constant, and the third dielectric constant.

[0208] In some embodiments, forming a fourth portion of the gate dielectric layer includes: forming the fourth portion laterally between a fifth portion of one or more second portions and a sixth portion of one or more second portions.

[0209] In some embodiments, forming a fourth portion of the gate dielectric layer includes: the fourth portion being laterally formed between a seventh portion of one or more third portions and an eighth portion of one or more third portions.

[0210] In some embodiments, forming the gate structure includes: forming one or more first doped regions of the gate structure over one or more first portions of the gate dielectric layer, wherein the one or more first doped regions have a first work function value; forming one or more second doped regions of the gate structure over one or more second portions of the gate dielectric layer, wherein the one or more second doped regions have a second work function value, the second work function value being different from the first work function value; and forming one or more third doped regions of the gate structure over one or more third portions of the gate dielectric layer, wherein the one or more third doped regions have a third work function value, the third work function value being different from both the first and second work function values.

[0211] In some embodiments, a transistor structure includes: a substrate of a semiconductor device, a first source / drain region, a second source / drain region, a gate structure, and a composite gate dielectric layer. The first source / drain region is located in the substrate of the semiconductor device. The second source / drain region is located in the substrate. The gate structure is located above the substrate, wherein the gate structure is laterally positioned between the first source / drain region and the second source / drain region. The composite gate dielectric layer is located between the gate structure and the substrate, wherein the composite gate dielectric layer includes different plurality of laterally arranged portions.

[0212] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged in a semiconductor device along a first direction. These laterally arranged portions include a first portion, a second portion, and a third portion, which are arranged in a second direction in the semiconductor device, the second direction being approximately perpendicular to the first direction.

[0213] In some embodiments, these laterally arranged portions include: a fourth portion laterally adjacent to the first portion, a fifth portion laterally adjacent to the second portion, and a sixth portion laterally adjacent to the third portion, wherein the fourth, fifth, and sixth portions are arranged along a second direction.

[0214] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged in a semiconductor device along a first direction. The gate structure extends in the semiconductor device along a second direction between the first and second source / drain regions, the second direction being approximately perpendicular to the first direction. These laterally arranged portions include a first portion, a second portion, and a third portion, which are arranged along the first direction.

[0215] In some embodiments, these laterally arranged portions include: a fourth portion adjacent to a first end of the first portion and a fifth portion adjacent to a second end of the first portion, wherein the fourth portion, the first portion, and the fifth portion are arranged along a second direction.

[0216] In some embodiments, a transistor structure includes: a substrate of a semiconductor device, a first source / drain region, a second source / drain region, a gate structure, and a gate dielectric layer. The first source / drain region is located in the substrate of the semiconductor device. The second source / drain region is located in the substrate. The gate structure is located above the substrate, wherein the gate structure is laterally positioned between the first source / drain region and the second source / drain region. The gate dielectric layer is located between the gate structure and the substrate. The gate structure includes a plurality of laterally arranged doped regions.

[0217] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged in a semiconductor device along a first direction. These laterally arranged doped regions include a first doped region, a second doped region, and a third doped region, which are arranged in a second direction in the semiconductor device, approximately perpendicular to the first direction.

[0218] In some embodiments, these laterally arranged doped regions include: a fourth doped region laterally adjacent to the first doped region, a fifth doped region laterally adjacent to the second doped region, and a sixth doped region laterally adjacent to the third doped region, wherein the fourth, fifth, and sixth doped regions are arranged along a second direction.

[0219] In some embodiments, a first source / drain region, a gate structure, and a second source / drain region are arranged in a semiconductor device along a first direction. The gate structure extends in the semiconductor device along a second direction between the first and second source / drain regions, the second direction being approximately perpendicular to the first direction. These laterally arranged doped regions include a first doped region, a second doped region, and a third doped region, which are arranged along the first direction.

[0220] In some embodiments, a transistor structure includes: a substrate, a gate dielectric layer, a gate structure, a first source / drain region, and a second source / drain region. The gate dielectric layer is located on the substrate and includes one or more laterally arranged first portions, one or more second portions, and one or more third portions, which are different from each other. The gate structure is located above the gate dielectric layer. The first source / drain region and the second source / drain region are laterally adjacent to opposite sides of the gate structure.

[0221] The terms “approximately” and “substantially” can mean that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, in accordance with this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0222] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A transistor structure, characterized in that, Include: A first source / drain region is located in a substrate of a semiconductor device; A second source / drain region is located in the substrate; A gate structure is located above the substrate. The gate structure is laterally located between the first source / drain region and the second source / drain region; and A composite gate dielectric layer is located between the gate structure and the substrate. The composite gate dielectric layer comprises multiple laterally arranged portions.

2. The transistor structure of claim 1, wherein the first source / drain region, the gate structure, and the second source / drain region are arranged along a first direction in the semiconductor device; and The plurality of laterally arranged portions include a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are arranged in the semiconductor device along a second direction, which is approximately perpendicular to the first direction.

3. The transistor structure of claim 2, wherein the plurality of laterally arranged portions comprise: A fourth part, which is horizontally adjacent to the first part; A fifth part, which is laterally adjacent to the second part; and A sixth part is laterally adjacent to the third part, wherein the fourth part, the fifth part, and the sixth part are arranged along the second direction.

4. The transistor structure of claim 1, wherein the first source / drain region, the gate structure, and the second source / drain region are arranged along a first direction in the semiconductor device; The gate structure extends in the semiconductor device along a second direction between the first source / drain region and the second source / drain region, and the second direction is approximately perpendicular to the first direction; and The plurality of horizontally arranged portions include: a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are arranged along the first direction.

5. The transistor structure of claim 4, wherein the plurality of laterally arranged portions comprise: A fourth part, adjacent to a first end of the first part; and A fifth portion, adjacent to a second end of the first portion, wherein the fourth portion, the first portion, and the fifth portion are arranged along the second direction.

6. A transistor structure, characterized in that, Include: A first source / drain region is located in a substrate of a semiconductor device; A second source / drain region is located in the substrate; A gate structure is located above the substrate. The gate structure is laterally located between the first source / drain region and the second source / drain region; and A gate dielectric layer is located between the gate structure and the substrate. The gate structure contains multiple laterally arranged doped regions.

7. The transistor structure of claim 6, wherein the first source / drain region, the gate structure, and the second source / drain region are arranged along a first direction in the semiconductor device; and The plurality of laterally arranged doped regions include a first doped region, a second doped region, and a third doped region, wherein the first doped region, the second doped region, and the third doped region are arranged along a second direction in the semiconductor device, the second direction being approximately perpendicular to the first direction.

8. The transistor structure of claim 7, wherein the plurality of laterally arranged doped regions comprise: A fourth doped region is laterally adjacent to the first doped region; A fifth doped region, laterally adjacent to the second doped region; and A sixth doped region is laterally adjacent to the third doped region, wherein the fourth, fifth, and sixth doped regions are arranged along the second direction.

9. The transistor structure of claim 6, wherein the first source / drain region, the gate structure, and the second source / drain region are arranged along a first direction in the semiconductor device; The gate structure extends in the semiconductor device along a second direction between the first source / drain region and the second source / drain region, and the second direction is approximately perpendicular to the first direction; and The plurality of laterally arranged doped regions include a first doped region, a second doped region, and a third doped region, wherein the first doped region, the second doped region, and the third doped region are arranged along the first direction.

10. A transistor structure, characterized in that, Include: One substrate; A gate dielectric layer is located on the substrate. The gate dielectric layer includes one or more first portions, one or more second portions, and one or more third portions arranged laterally. The one or more first portions, the one or more second portions, and the one or more third portions are different. A gate structure is located above the gate dielectric layer; and A first source / drain region and a second source / drain region are laterally adjacent to opposite sides of the gate structure.

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