A solar cell and photovoltaic module with a PN junction

Abstract

This invention provides a solar cell and photovoltaic module with a PN junction. The solar cell includes a silicon substrate. At least one sidewall along the length of the silicon substrate has a cut surface. One surface along the thickness of the silicon substrate has an emitter region, an isolation region, and a buffer zone. An emitter is provided on the emitter region, forming a PN junction with the silicon substrate. The isolation region is located at the edge of the silicon substrate, with the isolation region located at least near the edge of the cut surface. The surface of the isolation region has no emitter, and its height is lower than that of the emitter region. The isolation region and the emitter region are connected by a buffer zone, which has a sloping structure. By setting an isolation region lower than the emitter region and without an emitter on its surface, and by using a buffer zone to connect the emitter region and the isolation region, this solar cell can reduce the impact of edge recombination on the cell's working area and lower the probability of recombination centers, thereby optimizing cell performance.

Description

Technical Field

[0001] This utility model relates to the field of crystalline silicon solar cell fabrication technology, and more specifically, to a solar cell and photovoltaic module with a PN junction. Background Technology

[0002] Laser dicing is a common technique used in the fabrication of half-cell solar cells and their modules. Reducing recombination losses at the dicing edges has been a key focus in the industry. Patent document CN202410971803.5 discloses an edge-isolated sliced ​​solar cell and its fabrication method. This method involves setting PN-junction-free isolation regions on both sides of the laser-diced edge of the cell, ensuring the dicing edge is located within these PN-junction-free isolation regions. By introducing these PN-junction-free isolation regions, the recombination effect at the dicing edge can be effectively suppressed, reducing the carrier recombination rate and improving the cell's performance.

[0003] However, research has found that the substrate surface with the introduced isolation region exhibits an approximately vertical drop structure. During the process of covering the isolation region with the passivation layer, voids are easily formed, affecting the passivation quality. These voids can form new recombination centers, leading to intensified carrier recombination and consequently affecting battery efficiency. Utility Model Content

[0004] In view of the shortcomings of the existing technology, the technical problem to be solved by this utility model is how to optimize the structure of the isolation zone, improve the composite effect of the passivation layer, and avoid the appearance of voids.

[0005] To achieve the above objectives, this utility model provides a solar cell with a PN junction, comprising a silicon substrate, at least one sidewall of the silicon substrate along its length having a cut surface, and one side surface of the silicon substrate along its thickness having an emitter region, an isolation region, and a buffer zone. An emitter is provided on the emitter region, and a PN junction is formed between the emitter and the silicon substrate. The isolation region is disposed at the edge of the silicon substrate, and the isolation region is provided at least near the edge of the cut surface in the silicon substrate. The surfaces of the isolation region and the buffer zone have no emitter, and the surface height of the isolation region is lower than that of the emitter region. The isolation region and the emitter region are connected through the buffer zone, which has a sloping structure. The surfaces of the emitter, the isolation region, and the buffer zone are covered with a passivation layer.

[0006] This patent provides a novel solar cell structure. By setting an isolation region below the emitter region and without emitters on its surface, and using a buffer zone to connect the emitter region and the isolation region, this unique structure cuts off the transport path of minority carriers from the emitter region to the cut surface, reduces the impact of edge recombination on the working area of ​​the cell, and improves the cell efficiency. The sloping structure of the buffer zone helps the passivation layer to cover more evenly, reduces the formation of voids, lowers the probability of recombination centers, and further optimizes the cell performance.

[0007] Furthermore, the slope angle of the buffer zone is 20° to 60°. This angle range ensures that the passivation layer adheres better when the buffer zone transitions between the emitter and isolation zones. It avoids both an unnatural transition due to an excessively small slope angle affecting the passivation layer coverage and material waste due to an excessively large slope angle, thereby effectively improving the passivation layer composite effect and enhancing battery performance.

[0008] Furthermore, the vertical height of the buffer zone is 1~10μm. This height range ensures effective edge isolation while providing sufficient transition space between the emission region and the isolation region, allowing for smoother carrier transport and reducing recombination.

[0009] Furthermore, the width of the isolation region is 20~1000μm. Sufficient width can effectively isolate the cutting surface from the emitter region, suppress the influence of minority carrier recombination dark current at the cutting part on the battery working area, and this width range can be flexibly adjusted according to different battery designs and application scenarios, taking into account both battery efficiency improvement and cost control.

[0010] Furthermore, both the surface of the isolation zone and the surface of the emission zone have a pyramidal structure, with the pyramids being square pyramids. The pyramid size of the isolation zone is smaller than that of the emission zone. The use of a small-sized pyramidal structure on the isolation zone surface reduces optical reflection loss.

[0011] Furthermore, the pyramid height of the surface of the isolation zone is 0.2~2μm, and the base side length is 0.5~5μm. This small-sized pyramid surface structure can significantly increase the light absorption area, improve light capture efficiency, and reduce light reflection loss.

[0012] Furthermore, the surface pyramid distribution density of the isolation zone is 3×10⁻⁶. 5 ~1×10 6 pcs / mm 2 The high density of the pyramid distribution helps to increase the contact area between the passivation layer and the isolation region, further suppressing carrier recombination.

[0013] Furthermore, the surface of the isolation zone has a tower-based structure, and the tower base is a truncated quadrangular shape. Compared with a planar structure, the tower-based structure can reduce optical reflection loss and provide a good adhesion base for the passivation layer.

[0014] Furthermore, the height of the base of the isolation zone is less than 0.2 μm, and the side length of the base is 10~50 μm. Limiting the base size optimizes the device's light utilization efficiency and helps improve device performance.

[0015] Furthermore, the passivation layer is a multilayer film of aluminum oxide and silicon nitride. This composite passivation layer has a good passivation effect, which can reduce surface carrier recombination and improve the photoelectric conversion efficiency of solar cells.

[0016] This invention also provides a photovoltaic module, including the aforementioned solar cell with a PN junction, which can fully utilize the high-efficiency photoelectric conversion performance of the cell and improve the overall output power and conversion efficiency of the photovoltaic module.

[0017] In summary, the present invention has the following advantages over the prior art:

[0018] (1) Reduce edge recombination: An isolation region is set on the surface of the silicon substrate below the emitter region. The emitter region is connected by a buffer slope structure to cut off the carrier transmission channel to the cut surface. The isolation region has no emitter, which suppresses carrier recombination caused by defects in the cut surface, reduces dark current loss, improves open circuit voltage and fill factor, and improves photoelectric conversion efficiency.

[0019] (2) Optimize the quality of passivation layer coverage: The buffer slope provides a smooth transition basis for passivation layer deposition, avoiding coverage gaps and defects; the pyramid structure or base structure on the surface of the isolation zone increases the contact area, closely adheres to the passivation layer, reduces the interface recombination center, and improves the surface passivation effect and electrical performance.

[0020] (3) Reduce optical reflection loss: The surface of the isolation area is a pyramid structure or a base structure, which can increase the absorption and scattering of light, effectively reduce optical reflection loss, and improve the device's efficiency in utilizing light energy.

[0021] (4) Adaptable to multiple segmentation modes and advanced battery technologies: The battery structure can be flexibly adapted to segmentation modes such as "segmentation of two" and "segmentation of three" to meet the design requirements of different components; and is compatible with TOPCon, BC battery and other technology routes, adapting to different battery structures, which can promote the large-scale application of high-efficiency batteries. Attached Figure Description

[0022] Figure 1 This is a structural diagram of the cut portion of a solar cell in one specific embodiment.

[0023] Figure 2 This is a structural diagram of the cut portion of the solar cell in another specific embodiment.

[0024] Figure 3 This is a cross-sectional view of a solar cell structure according to a specific embodiment.

[0025] Figure 4 This is a cross-sectional view of a solar cell structure according to another specific embodiment.

[0026] Figure 5This is a PL diagram of the sample from Example 1.

[0027] Figure 6 PL plot of sample 1

[0028] Figure 7 This is a surface morphology diagram of the isolation region of the sample in Example 2.

[0029] Figure 8 This is a side view of the isolation zone edge of the sample in Example 2.

[0030] Figure 9 This is a frontal feature image of the edge of the isolation zone of the sample in Example 3.

[0031] Figure 10 This is a side view of the isolation zone edge of the sample in Example 3.

[0032] Figure 11 This is a surface morphology diagram of the isolation region of the sample in Example 5.

[0033] Figure 12 This is a frontal topographic image of the edge of the isolation zone of the sample in Example 5.

[0034] Figure 13 This is a frontal topographic image of the edge of the isolation zone of the sample in Example 6.

[0035] Figure 14 This is a photograph showing the features of the edge of the isolation zone of the sample in Comparative Example 4.

[0036] Explanation of reference numerals in the attached figures:

[0037] 1-Silicon substrate, 2-Cut surface, 3-Emitter region, 4-Buffer zone, 5-Isolation region, 6-Emitter, 7-First passivation layer, 8-First electrode, 9-Tunneling oxide layer, 10-Doped polysilicon layer, 11-Second passivation layer, 12-Second electrode. Detailed Implementation

[0038] To make the above-mentioned objectives, features, and advantages of this utility model more apparent and understandable, specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation methods and typical parameters of this utility model, and are not intended to limit the parameter range described in this utility model. Reasonable variations derived therefrom are still within the protection scope of the claims of this utility model.

[0039] It should be noted that the endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

[0040] A specific embodiment of this utility model provides a solar cell with a PN junction, combined with... Figure 1 As shown, the solar cell includes a silicon substrate 1. One or both sidewalls of the silicon substrate 1 along its length have a cut surface 2 created by laser slicing. One surface of the silicon substrate 1 along its thickness has an emitter region 3, an isolation region 5, and a buffer zone 4. An emitter 6 is provided on the emitter region 3, forming a PN junction with the silicon substrate 1. The surface of the emitter region 3 has a pyramidal structure. The isolation region 5 is located near the edge of the cut surface 2. The surface height of the isolation region 5 is lower than that of the emitter region 3. It has no emitter 6 on its surface and has a pyramidal structure, with the pyramid size smaller than that of the emitter region 3. The isolation region 5 can cut off the minority carrier transport channel from the emitter region 3 to the cut surface 2, reducing the impact of recombination at the cut edge on the working area of ​​the cell. The small-sized pyramidal structure of the isolation region 5 helps to reduce optical reflection losses. The buffer zone 4 is located between the emitter region 3 and the isolation region 5. It has no emitter 6 on its surface and has a sloping structure, forming a transition connection. A first passivation layer 7 is provided on the surface of the silicon substrate 1 with an emitter 6. The passivation layer covers the emitter 6, the isolation region 5 and the buffer zone 4. The slope structure of the buffer zone 4 helps the first passivation layer 7 to cover more evenly, avoid gaps, and improve the passivation layer composite effect.

[0041] In some specific embodiments, the size of the buffer zone 4 is optimized, controlling the slope angle of the buffer zone 4 to be 20°~60° and the vertical height to be 1~10μm. By limiting the size of the buffer zone 4, the edge isolation effect is ensured, while also providing sufficient transition space between the emission region 3 and the isolation region 5, ensuring the coverage effect of the first passivation layer 7 and avoiding gaps.

[0042] In some specific embodiments, the surface of the isolation zone 5 is optimized to have a pyramid structure. The pyramid is a square pyramid with a height of 0.2~2μm, a base side length of 0.5~5μm, and a pyramid distribution density of 3×10⁻⁶. 5 ~1×10 6 pcs / mm 2 This surface structure significantly increases the light absorption area, improves light capture efficiency, and reduces light reflection loss; at the same time, it can increase the contact area between the passivation layer and the isolation region 5, further suppressing carrier recombination.

[0043] In some specific embodiments, the size of the isolation region 5 is optimized and the width of the isolation region 5 is controlled to be 20~1000μm. Sufficient width can effectively isolate the cutting surface 2 and the emission region 3, and suppress the influence of minority carrier recombination dark current at the cutting part on the battery working area.

[0044] In some specific embodiments, the structure of the first passivation layer 7 is optimized, and the first passivation layer 7 is limited to an aluminum oxide and silicon nitride stacked thin film. This composite passivation layer can reduce surface carrier recombination and improve the photoelectric conversion efficiency of solar cells.

[0045] In a specific embodiment, the aforementioned solar cell with a PN junction can be fabricated using the following process: A silicon substrate 1 is provided, and an emitter 6 is formed on one side of the silicon substrate 1 along its thickness direction, forming a PN junction between the emitter 6 and the silicon substrate 1. The emitter 6 is subjected to picosecond laser surface treatment, including acid etching and alkaline etching of the laser-treated area to remove the corresponding portion of the emitter 6 and alter the surface structure of the silicon substrate 1, forming an isolation region 5 and a buffer zone 4. A passivation layer is deposited on the side of the silicon substrate 1 with the emitter 6. Laser non-destructive cutting is performed, with the cutting line located within the isolation region 5. In a specific embodiment, to form a high-quality isolation region 5 and buffer zone 4, the laser spot type is selected as a Gaussian spot or a flat-top spot, and the laser process parameters are adjusted according to the different spot types.

[0046] In a specific embodiment, to form a high-quality isolation zone 5 and buffer zone 4, the laser spot type is selected as either a Gaussian spot or a flat-top spot, and the laser process parameters are adjusted according to the different spot types. Specifically, when the laser spot type is a Gaussian spot, the laser frequency is controlled at 400~6000kHz, the power at 10~80W, and the speed at 1000~40000mm / s; when the laser spot type is a flat-top spot, the laser frequency is controlled at 3000~6000kHz, the power at 10~100W, and the speed at 2000~40000mm / s.

[0047] In some embodiments, flat-top light spots and Gaussian light spots can be used in combination. The main part of the isolation area 5 uses a flat-top light spot to achieve a uniform etching effect, while the edge part uses a Gaussian light spot for etching to form a buffer zone 4 with a natural transition.

[0048] In a specific embodiment, in order to form a pyramid structure on the surface of the isolation region 5, an alkaline solution with added texturing aid is used for alkaline etching. By adjusting the etching process, the isolation region 5 with the ideal surface structure can be obtained.

[0049] Combination Figure 2As shown, this is another embodiment of a solar cell with a PN junction. The main difference from the above embodiment is that the surface of the isolation region 5 is a tower-based structure. The tower-based structure also has the effect of reducing light reflection loss compared to the planar structure.

[0050] In a specific embodiment, the tower base structure is optimized, with the base being a frustum shape, less than 0.2 μm in height, and the base side length being 10~50 μm. This effectively reduces optical reflection loss, optimizes the device's light utilization efficiency, and provides a good adhesion foundation for the passivation layer.

[0051] The above-mentioned battery structure is applicable to various high-efficiency photovoltaic cells such as TOPCon cells and BC cells, and can be flexibly adapted to slicing modes such as "slice in two" and "slice in three". The isolation structure is located on the side of the cell with the PN junction, which can isolate the recombination loss at the cutting edge to the greatest extent, thereby improving the efficiency of the sliced ​​cells and increasing the overall power of the photovoltaic module.

[0052] Combination Figure 3 As shown, taking a two-segment TOPCon cell as an example, the cell includes a silicon substrate 1. Most of the front surface of the silicon substrate 1 has an emitter 6, and the area covering the emitter 6 is the emitter region 3. The surface of the emitter region 3 has a pyramid structure. A first passivation layer 7 covers the entire front surface of the silicon substrate 1, and a first electrode 8 passes through the first passivation layer 7 to contact the emitter 6. The back surface of the silicon substrate 1 is sequentially covered with a tunneling oxide layer 9, a doped polycrystalline silicon layer 10, and a second passivation layer 11. A second electrode 12 passes through the second passivation layer 11 to contact the doped polycrystalline silicon layer 10. One side of the silicon substrate 1 is a cut surface 2. Near the cut surface 2 on the front surface of the silicon substrate 1, there is an isolation structure. The surface of the isolation structure has no emitter 6 and includes an isolation region 5 and a buffer zone 4. The surface height of the isolation region 5 is lower than that of the emitter region 3, and the isolation region 5 and the emitter region 3 are connected by a sloped buffer zone 4.

[0053] In some embodiments, an isolation region 5 may also be formed on the silicon substrate 1 at an edge not close to the cut surface 2. Taking a two-segment TOPCon cell as an example, the structure is as follows: Figure 4 As shown, an isolation region 5 is provided on the edge of the silicon substrate 1 near the cut surface 2, and isolation regions 5 are also provided on other edges. This can reduce carrier recombination in the non-cut edge areas of the cell, further improving the cell efficiency. The isolation regions 5 around the perimeter are connected to the corresponding buffer zones 4, and the first passivation layer 7 is uniformly covered on the entire front surface of the silicon substrate 1.

[0054] The technical solution and effects of this utility model are illustrated by specific embodiments below.

[0055] Example 1

[0056] Prepare an n-type silicon substrate, perform front-side texturing, and standard RCA cleaning. Boron diffusion is performed on the front side of the silicon substrate to form a boron emitter. A groove is created in the central area of ​​the passivation wafer's front side to remove the corresponding emitter portion, forming an isolation region. The edges of the isolation region are sloped buffer zones, with the slope angle controlled at 50°–60° and the vertical height at 3–5 μm. An aluminum oxide film and a silicon nitride film are deposited on the front side of the passivation wafer to form the front passivation layer.

[0057] The PL test was performed on the sample prepared in this embodiment, and the results are as follows: Figure 5 As shown.

[0058] Comparative Example 1

[0059] Prepare an n-type silicon substrate, perform front-side texturing, and standard RCA cleaning. Boron diffusion is performed on the front side of the silicon substrate to form a boron emitter. A groove is created in the central area of ​​the passivation wafer's front side to remove the corresponding emitter portion, forming an isolation region. The edges of the isolation region have a near-vertical structure with a vertical height of 3-5 μm. An aluminum oxide film and a silicon nitride film are deposited on the front side of the passivation wafer to form the front passivation layer.

[0060] The PL test was performed on the sample prepared in this embodiment, and the results are as follows: Figure 6 As shown, with Figure 5 In comparison, it can be seen that setting up a slope buffer zone at the edge of the isolation zone is beneficial to improving the passivation layer coverage quality and reducing the interface composite center.

[0061] Example 2

[0062] An n-type silicon substrate was prepared, with texturing on the front side and polishing on the back side, followed by standard RCA cleaning. Boron diffusion was performed on the front side of the silicon substrate to form a boron emitter; the back side was etched to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon were sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. A groove was cut into the area with a certain width corresponding to the pre-cut lines on the passivation wafer to remove the corresponding emitter, forming an isolation region approximately 200 μm wide. The surface structure of the isolation region is shown below. Figure 7 As shown, the surface has a truncated pyramidal base structure with a base height of less than 0.1 μm and a base side length of approximately 20 μm. The two sides of the isolation zone form a buffer zone with a sloping structure, the morphology of which is as follows: Figure 8 As shown, the buffer zone has a vertical height of approximately 3.2 μm and a slope angle of approximately 30°. An aluminum oxide film is prepared on the front side of the passivation sheet, followed by double-sided deposition of silicon nitride films. The passivation sheet undergoes double-sided metallization. Laser cutting is performed along pre-defined cutting lines to obtain two sliced ​​cells.

[0063] 2000 identical sliced ​​solar cells were prepared using the above method. The performance of the sliced ​​solar cells was tested using Suns-Voc. The average performance test results of the samples are as follows: Open circuit voltage ( Voc ) = 737.2mV, short-circuit current density ( J sc = 41.13 mA / cm 2 Fill factor ( FF =86.15%, efficiency ( Eff =26.42%.

[0064] Ten 108-cell TOPCon solar cell modules were fabricated using the sliced ​​solar cells prepared in Example 2. Each module measures 9.1 cm × 18.2 cm. The average power of the modules was measured to be 445.9 W.

[0065] Example 3

[0066] An n-type silicon substrate was prepared, with texturing on the front side and polishing on the back side, followed by standard RCA cleaning. Boron diffusion was performed on the front side of the silicon substrate to form a boron emitter; the back side was etched to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon were sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. A groove was cut into a region of a certain width corresponding to the pre-cut lines on the passivation wafer to remove the corresponding emitter, forming an isolation region approximately 200 μm wide. The surface of the isolation region has a tower-based structure with a height of less than 0.1 μm and a base side length of approximately 20 μm. The two sides of the isolation region form a buffer zone with a sloping structure, and its front morphology is as follows. Figure 9 As shown, the edges of the buffer zone and isolation zone are smooth. The side profile is as follows. Figure 10 As shown, the buffer zone has a vertical height of approximately 3.6 μm and a slope angle of approximately 55°. An aluminum oxide film is prepared on the front side of the passivation sheet, followed by double-sided deposition of silicon nitride films. The passivation sheet undergoes double-sided metallization. Laser cutting is performed along pre-defined cutting lines to obtain two sliced ​​cells.

[0067] 2000 identical sliced ​​solar cells were prepared using the above method. The performance of the sliced ​​solar cells was tested using Suns-Voc. The average performance test results of the samples are as follows: Open circuit voltage ( V oc =738.0mV, short-circuit current density ( J sc =41.10mA / cm 2 Fill factor ( FF =86.64%, efficiency ( Eff =26.46%.

[0068] Ten 108-cell TOPCon solar cell modules were fabricated using the sliced ​​solar cells prepared in Example 3. Each module measures 9.1 cm × 18.2 cm. The average power output of the modules was measured to be 446.7 W.

[0069] Example 4

[0070] An n-type silicon substrate is prepared, with texturing on the front side and polishing on the back side, followed by standard RCA cleaning. Boron diffusion is performed on the front side of the silicon substrate to form a boron emitter. The back side is etched to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. A groove is created in the area corresponding to the pre-cut lines on the passivation wafer, removing the corresponding emitter and forming an isolation region approximately 100 μm wide. The surface of the isolation region has a tower-like structure with a height less than 0.2 μm and a base side length of approximately 10 μm. The two edges of the isolation region form a sloped buffer zone with a vertical height of approximately 5.0 μm and a slope angle of approximately 60°. An alumina film is prepared on the front side of the passivation wafer, followed by double-sided deposition of silicon nitride films. The passivation wafer is then double-sided metallized. Laser cutting is performed along the pre-cut lines to obtain two sliced ​​cells.

[0071] 2000 identical sliced ​​solar cells were prepared using the above method. The performance of the sliced ​​solar cells was tested using Suns-Voc. The average performance test results of the samples are as follows: Open circuit voltage ( V oc ) = 737.8mV, short-circuit current density ( J sc =41.12mA / cm 2 Fill factor ( FF =86.53%, efficiency ( Eff =26.45%.

[0072] Example 5

[0073] Prepare an n-type silicon substrate, texturing the front side and polishing the back side, followed by standard RCA cleaning. Boron diffusion is performed on the front side of the silicon substrate to form a boron emitter; the back side is etched to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. A groove is cut into the area with a certain width corresponding to the pre-cut lines on the passivation wafer to remove the corresponding emitter, forming an isolation region approximately 200 μm wide. The surface of the isolation region has a pyramid structure, such as... Figure 11 and Figure 12 As shown, the pyramid is a square pyramid shape, approximately 1 μm high, with a base side length of approximately 2 μm, and a distribution density of approximately 6 × 10⁻⁶. 5 pcs / mm 2 The isolation zone has sloping buffer zones on both sides, with a vertical height of approximately 4 μm and a slope angle of approximately 25°. An aluminum oxide film is prepared on the front side of the passivation sheet, followed by double-sided deposition of silicon nitride films. The passivation sheet undergoes double-sided metallization. Laser cutting is performed along pre-defined cutting lines to obtain two sliced ​​cells.

[0074] 2000 identical sliced ​​solar cells were prepared using the above method. The performance of the sliced ​​solar cells was tested using Suns-Voc. The average performance test results of the samples are as follows: Open circuit voltage ( V oc =737.5mV, short-circuit current density ( J sc = 41.11 mA / cm 2 Fill factor ( FF =86.37%, efficiency ( Eff =26.43%.

[0075] Ten 108-cell half-cell battery modules were fabricated using the sliced ​​battery prepared in Example 5. Each battery module measures 9.1 cm × 18.2 cm. The average power of the modules was tested to be 446.2 W.

[0076] Example 6

[0077] Prepare an n-type silicon substrate, texturing the front side and polishing the back side, followed by standard RCA cleaning. Boron diffusion is performed on the front side of the silicon substrate to form a boron emitter. The back side is etched to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. A groove of a certain width is cut at the pre-cut lines on the passivation wafer to remove the corresponding emitter, forming an isolation region approximately 100 μm wide. The surface of the isolation region has a pyramidal structure, such as... Figure 13 As shown, the pyramid is a square pyramid shape, approximately 1 μm high, with a base side length of approximately 2 μm, and a distribution density of approximately 6 × 10⁻⁶. 5 pcs / mm 2 The isolation zone has sloping buffer zones on both sides, with a vertical height of approximately 4 μm and a slope angle of approximately 55°. An alumina film is prepared on the front side of the passivation sheet, followed by double-sided deposition of silicon nitride films. The passivation sheet undergoes double-sided metallization. Laser cutting is performed along pre-defined cutting lines to obtain two sliced ​​cells.

[0078] 2000 identical sliced ​​solar cells were prepared using the above method. The performance of the sliced ​​solar cells was tested using Suns-Voc. The average performance test results of the samples are as follows: Open circuit voltage ( V oc =738.3mV, short-circuit current density ( J sc =41.06mA / cm 2 Fill factor ( FF =87.02%, efficiency ( Eff =26.51%.

[0079] Ten 108-cell half-cell battery modules were fabricated using the sliced ​​battery prepared in Example 6. Each battery module measures 9.1 cm × 18.2 cm. The average power of the modules was tested to be 447.0 W.

[0080] Example 7

[0081] Prepare an n-type silicon substrate, texturing the front side and polishing the back side, followed by standard RCA cleaning. Boron diffusion is performed on the front side of the silicon substrate to form a boron emitter. The back side is etched to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. A groove is cut into a region of a certain width corresponding to the pre-cut lines on the passivation wafer to remove the corresponding emitter, forming an isolation region approximately 200 μm wide. The surface of the isolation region has a pyramid structure, approximately 2 μm high, with a base side length of approximately 4 μm and a distribution density of approximately 2 × 10⁻⁶. 5 pcs / mm 2 The isolation zone has sloping buffer zones on both sides, with a vertical height of approximately 5 μm and a slope angle of approximately 45°. An aluminum oxide film is prepared on the front side of the passivation sheet, followed by double-sided deposition of silicon nitride films. The passivation sheet undergoes double-sided metallization. Laser cutting is performed along pre-defined cutting lines to obtain two sliced ​​cells.

[0082] 2000 identical sliced ​​solar cells were prepared using the above method. The performance of the sliced ​​solar cells was tested using Suns-Voc. The average performance test results of the samples are as follows: Open circuit voltage ( V oc ) = 738.1mV, short-circuit current density ( J sc =41.08mA / cm 2 Fill factor ( FF =86.81%, efficiency ( Eff =26.48%.

[0083] Comparative Example 2

[0084] An n-type silicon substrate was prepared, with texturing on the front side and polishing on the back side, followed by standard RCA cleaning. Boron diffusion was performed on the front side of the silicon substrate to form a boron emitter; the back side was etched to remove the borosilicate glass. Nanoscale silicon oxide and phosphorus-doped amorphous silicon were sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. An alumina film was prepared on the front side of the passivation wafer, followed by double-sided deposition of silicon nitride films. The passivation wafer underwent double-sided metallization. Laser cutting was performed along pre-defined cutting lines to obtain two sliced ​​cells. ALD was used to deposit a 30nm thick alumina on the cut surfaces.

[0085] 2000 identical solar cells were prepared using the above method. The performance of the solar cells was tested using Suns-Voc, and the average performance test results of the samples are as follows: Open circuit voltage (…). V oc ) = 732.1mV, short-circuit current density ( J sc =41.80mA / cm 2 Fill factor ( FF =85.26%, efficiency ( Eff =25.71%.

[0086] Using the sliced ​​solar cells prepared in Comparative Example 2, ten 108 half-cell TOPCon solar cell modules were fabricated, each module measuring 9.1 cm × 18.2 cm. The average power output of the modules was measured to be 439.7 W.

[0087] Comparative Example 3

[0088] An n-type silicon substrate is prepared, with texturing on the front side and polishing on the back side, followed by standard RCA cleaning. Boron diffusion is performed on the front side of the silicon substrate to form a boron emitter; the back side is etched to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. A groove is created in the area with a certain width corresponding to the pre-cut line on the passivation wafer to remove the corresponding emitter, forming an isolation region with a width of approximately 200 μm. The surface of the isolation region is planar, while the two edges are nearly vertical with a vertical height of less than 1 μm. An aluminum oxide film is prepared on the front side of the passivation wafer, followed by double-sided deposition of silicon nitride films. The passivation wafer is then double-sided metallized. Laser cutting is performed along the pre-cut line to obtain two sliced ​​cells.

[0089] 2000 identical solar cells were prepared using the above method. The performance of the solar cells was tested using Suns-Voc, and the average performance test results of the samples are as follows: Open circuit voltage (…). V oc =734.6mV, short-circuit current density ( J sc =41.58mA / cm 2 Fill factor ( FF =85.66%, efficiency ( Eff =25.88%.

[0090] Using the sliced ​​cells prepared in Comparative Example 3, ten 108 half-cell battery modules were fabricated, each module measuring 9.1 cm × 18.2 cm. The average power output of the modules was measured to be 441.5 W.

[0091] Comparative Example 4

[0092] An n-type silicon substrate was prepared, with texturing on the front side and polishing on the back side, followed by standard RCA cleaning. Boron diffusion was performed on the front side of the silicon substrate to form a boron emitter; the back side was etched to remove the borosilicate glass. Nano-sized silicon oxide and phosphorus-doped amorphous silicon were sequentially deposited on the back side, followed by annealing at 900℃ for 30 minutes to obtain a TOPCon structure passivation wafer. A groove was cut into a region of a certain width corresponding to the pre-cut lines on the passivation wafer to remove the corresponding emitter, forming an isolation region approximately 100 μm wide. The surface of the isolation region has a tower-based structure, with the base being a truncated pyramid shape, less than 0.1 μm high, and a base side length of approximately 20 μm. The two edges of the isolation region have a nearly vertical structure, with the morphology as shown in the image. Figure 14 As shown, the vertical height is approximately 5 μm. An aluminum oxide film is prepared on the front side of the passivation sheet, followed by double-sided deposition of silicon nitride films. The passivation sheet undergoes double-sided metallization. Laser cutting is performed along pre-defined cutting lines to obtain two sliced ​​cells.

[0093] 2000 identical sliced ​​solar cells were prepared using the above method. The performance of the sliced ​​solar cells was tested using Suns-Voc. The average performance test results of the samples are as follows: Open circuit voltage ( V oc =735.4mV, short-circuit current density ( J sc =41.37mA / cm 2 Fill factor ( FF =85.95%, efficiency ( Eff =26.14%.

[0094] Using the sliced ​​solar cells prepared in Comparative Example 4, ten 108 half-cell TOPCon solar cell modules were fabricated, each module measuring 9.1 cm × 18.2 cm. The average power output of the modules was measured to be 442.6 W.

[0095] Although the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A solar cell having a PN junction, characterized by, The device includes a silicon substrate, at least one sidewall along the length direction of the silicon substrate has a diced surface, and one side surface along the thickness direction of the silicon substrate has an emitter region, an isolation region, and a buffer zone. An emitter is provided on the emitter region, and a PN junction is formed between the emitter and the silicon substrate. The isolation region is located at the edge of the silicon substrate, and the isolation region is located at least near the edge of the diced surface. The surfaces of the isolation region and the buffer zone have no emitter. The surface height of the isolation region is lower than that of the emitter region. The isolation region and the emitter region are connected through the buffer zone, which has a sloping structure. The surfaces of the emitter, the isolation region, and the buffer zone are covered with a passivation layer.

2. The solar cell with a PN junction according to claim 1, characterized in that, The slope angle of the buffer zone is 20° to 60°.

3. The solar cell having a PN junction according to claim 1, wherein, The vertical height of the buffer zone is 1~10μm.

4. The solar cell having a PN junction according to claim 1, wherein The width of the isolation zone is 20~1000μm.

5. The solar cell with a PN junction according to any one of claims 1 to 4, characterized in that, The surface of the isolation zone is a pyramid structure, and the surface of the launch zone is a pyramid structure. The pyramid is a square pyramid shape, and the pyramid size of the isolation zone is smaller than the pyramid size of the launch zone.

6. The solar cell with a PN junction according to claim 5, characterized in that, The height of the pyramid on the surface of the isolation zone is 0.2~2μm, and the side length of the base is 0.5~5μm.

7. The solar cell with a PN junction according to claim 6, characterized in that, The surface pyramid distribution density of the isolation zone is 3×10⁻⁶. 5 ~1×10 6 pcs / mm 2 .

8. The solar cell with a PN junction according to any one of claims 1 to 4, characterized in that, The surface of the isolation zone is a tower base structure, and the tower base is a truncated quadrangular shape.

9. The solar cell with a PN junction according to claim 8, characterized in that, The height of the tower base on the surface of the isolation zone is less than 0.2 μm, and the side length of the tower base is 10~50 μm.

10. The solar cell with a PN junction according to any one of claims 1 to 4, characterized in that, The passivation layer is a laminated thin film of aluminum oxide and silicon nitride.

11. A photovoltaic module, characterized by Including solar cells with PN junctions as described in any one of claims 1-10.

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