显示基板和显示装置
By employing a multi-layer conductive layer and a multi-power drive design, combined with high-mobility oxide thin-film transistors and low-temperature polycrystalline silicon thin-film transistors, and optimizing the power line wiring space, the problem of high power consumption in the drive circuit of Micro LED display products is solved, achieving lower power consumption and higher display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-07-31
- Publication Date
- 2026-07-17
AI Technical Summary
Existing Micro LED display products have high power consumption in their driving circuits, making it difficult to meet the needs of portable products. Furthermore, the driving transistors have high mobility requirements and high power line wiring space requirements.
By employing a multi-layer conductive layer and a multi-power drive design, and combining high-mobility oxide thin-film transistors with low-temperature polycrystalline silicon thin-film transistors, the power consumption of the pixel circuit is reduced by optimizing the power line wiring space and circuit design.
It effectively reduces the overall power consumption of Micro LED display products, improves the adaptability of driving circuits and display effects, and increases the utilization rate of power line wiring space.
Smart Images
Figure CN224521517U_ABST
Abstract
Claims
1. A display substrate, characterized by, include: Substrate; The first planarization layer is located on one side of the substrate. The first passivation layer is located on the side of the first planarization layer away from the substrate. The second conductive layer is located on the side of the first passivation layer away from the substrate. and The second planarization layer is located on the side of the second conductive layer away from the substrate. The first passivation layer includes a plurality of first openings, each of which exposes at least a portion of the surface of the first planarization layer away from the substrate. The second planarization layer is connected to the first planarization layer through the plurality of first openings. as well as The second conductive layer includes a plurality of first wedge structures, each of which is located in a plurality of first openings, and at least a portion of the first wedge structures are wrapped by both the first planarization layer and the second planarization layer. 2.The display substrate of claim 1, wherein, The display substrate further includes: a second passivation layer located on the side of the second planarization layer away from the substrate; a third conductive layer located on the side of the second passivation layer away from the substrate; and a third planarization layer located on the side of the third conductive layer away from the substrate. The second passivation layer includes a plurality of second openings, each of which exposes at least a portion of the surface of the second planarization layer away from the substrate. The third planarization layer is connected to the second planarization layer through the plurality of second openings. The third conductive layer includes a plurality of second wedge structures, each of which is located in a plurality of second openings, and at least a portion of the second wedge structures are wrapped by both the second planarization layer and the third planarization layer. 3.The display substrate of claim 2, wherein, The orthographic projections of the plurality of second openings on the substrate fall within the orthographic projections of the plurality of first openings on the substrate.
4. The display substrate according to claim 2 or 3, wherein, The display substrate further includes: a third passivation layer located on the side of the third planarization layer away from the substrate; a fourth conductive layer located on the side of the third passivation layer away from the substrate; and a fourth planarization layer located on the side of the fourth conductive layer away from the substrate. The third passivation layer includes a plurality of third openings, each of which exposes at least a portion of the surface of the third planarization layer away from the substrate. The fourth planarization layer is connected to the third planarization layer through the plurality of third openings. The fourth conductive layer includes a plurality of third wedge structures, which are respectively located in a plurality of third openings, and at least a portion of the third wedge structures are wrapped by both the third planarization layer and the fourth planarization layer. 5.The display substrate of claim 4, wherein, The orthographic projections of the plurality of third openings on the substrate fall within the orthographic projections of the plurality of second openings on the substrate. 6.The display substrate of claim 5, wherein, The first planarization layer includes a first side facing the first opening, and at least a portion of the bottom surface of the first wedge structure is connected to the first side. And / or, The second planarization layer includes a second side facing the second opening, and at least a portion of the bottom surface of the second wedge structure is connected to the second side; and / or, The third planarization layer includes a third side facing the third opening, and at least a portion of the bottom surface of the third wedge structure is connected to the third side. 7.The display substrate of any one of claims 1-3, 5-6, wherein, The display substrate further includes a second semiconductor layer located between the substrate and the first planarization layer, wherein the orthographic projection of the plurality of first openings on the substrate does not overlap with the orthographic projection of the second semiconductor layer on the substrate. 8.The display substrate of claim 7, wherein, The second semiconductor layer includes at least one second active portion, wherein the orthographic projection of the at least one second active portion on the substrate and the orthographic projection of the adjacent first opening on the substrate are spaced at a distance greater than or equal to 3 micrometers in a first direction, wherein the first direction is perpendicular to the light emission direction of the display substrate. 9.The display substrate of claim 4, wherein, The distribution density of the plurality of first openings is greater than or equal to 100 per square millimeter; and / or, The distribution density of the plurality of second openings is greater than or equal to 100 per square millimeter; and / or, The distribution density of the plurality of third openings is greater than or equal to 100 per square millimeter. 10.The display substrate of claim 4, wherein, The shape of the orthographic projection of the first opening onto the substrate includes a square; and / or, The shape of the orthographic projection of the second opening onto the substrate includes a square; and / or, The shape of the orthographic projection of the third opening onto the substrate includes a square. 11.The display substrate of claim 10, wherein, The width of the orthographic projection of the first opening onto the substrate in a first direction is greater than or equal to 9 micrometers, and the first direction is perpendicular to the light emission direction of the display substrate; And / or, The width of the orthographic projection of the second opening onto the substrate in the first direction is greater than or equal to 7 micrometers, and the first direction is perpendicular to the light emission direction of the display substrate; And / or, The width of the orthographic projection of the third opening onto the substrate in a first direction is greater than or equal to 5 micrometers, and the first direction is perpendicular to the light emission direction of the display substrate. 12.The display substrate of claim 4, wherein, The first passivation layer is made of silicon oxide, the second passivation layer is made of silicon oxide, and the third passivation layer is made of silicon oxide; and / or, The material of the first planarization layer includes an organic material, the material of the second planarization layer includes an organic material, and the material of the third planarization layer includes an organic material. 13.The display substrate of claim 7, wherein, The display substrate further includes a first insulating layer located between the second semiconductor layer and the first planarization layer. The first insulating layer includes a first sublayer and a second sublayer. The second sublayer is located on the side of the first sublayer away from the substrate. The material of the first sublayer includes silicon oxide, and the material of the second sublayer includes silicon nitride. 14.The display substrate of claim 7, wherein, The material of the second semiconductor layer includes an oxide semiconductor material; and The carrier mobility in the second semiconductor layer is greater than or equal to 30 square centimeters / (volt-second). 15.The display substrate of claim 14, wherein, The display substrate further includes a first semiconductor layer located on the side of the second semiconductor layer near the substrate, and the material of the first semiconductor layer includes polycrystalline silicon semiconductor material; as well as The ratio of the carrier mobility in the first semiconductor layer to the carrier mobility in the second semiconductor layer is in the range of 0.5 to 2. 16.The display substrate of claim 13, wherein, The display substrate further includes: a fifth conductive layer located between the first insulating layer and the second semiconductor layer; a first semiconductor layer located on the side of the second semiconductor layer closer to the substrate; and a sixth conductive layer located between the second semiconductor layer and the first semiconductor layer. The display substrate includes at least one second transistor, and the at least one second transistor includes: a second active portion located in the second semiconductor layer, a second top gate located in the fifth conductive layer, and a second bottom gate located in the sixth conductive layer. 17.The display substrate of claim 16, wherein, The display substrate further includes a first conductive layer located between the first insulating layer and the first planarization layer. The first conductive layer includes a first connection portion, and at least a portion of the second top gate and the second bottom gate of the second transistor are electrically connected through the first connection portion. 18.The display substrate of claim 2, wherein, The display substrate further includes: a first conductive layer located on the side of the first planarization layer near the substrate. The display substrate also includes multiple power lines, which are located in one or more of the first conductive layer, the second conductive layer and the third conductive layer.
19. A display device comprising: Includes the display substrate as described in any one of claims 1-18.