显示面板

By introducing a charging suppression layer into the display panel, the threshold voltage deviation of thin-film transistors caused by substrate charging is resolved, thus improving the display effect.

CN224521522UActive Publication Date: 2026-07-17EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
EVERDISPLAY OPTRONICS (SHANGHAI) CO LTD
Filing Date
2025-07-16
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

In existing display panels, the threshold voltage shift of thin-film transistors caused by substrate charging leads to uneven local light emission.

Method used

A charge suppression layer is introduced into the display panel, located on the same side of the substrate and the buffer layer, and covering the channel region of the thin-film transistor, to suppress ion migration caused by substrate charging and prevent threshold voltage shift.

Benefits of technology

This effectively avoids threshold voltage shift in thin-film transistors, improves brightness uniformity of the display panel, and ensures display performance.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN224521522U_ABST
    Figure CN224521522U_ABST
Patent Text Reader

Abstract

本实用新型公开了一种显示面板，包括：衬底；缓冲层，位于衬底的一侧；充电抑制层，与缓冲层位于衬底的同一侧；薄膜晶体管层，包括多个薄膜晶体管，位于缓冲层和充电抑制层远离衬底的一侧；充电抑制层在衬底上的垂直投影覆盖薄膜晶体管的沟道在衬底上的垂直投影。本实用新型实施例的显示面板中在衬底和薄膜晶体管层之间设置充电抑制层，且充电抑制层的投影完全覆盖薄膜晶体管的沟道区域，避免了由于衬底充电造成薄膜晶体管的阈值电压偏移现象，提升了显示面板的显示效果。
Need to check novelty before this filing date? Find Prior Art

Claims

1. A display panel, characterized by, include: Substrate; A buffer layer is located on one side of the substrate; A charging suppression layer is located on the same side of the substrate as the buffer layer; A thin-film transistor layer, including a plurality of thin-film transistors, is located on the side of the buffer layer and the charge suppression layer away from the substrate; The vertical projection of the charge suppression layer on the substrate overlaps the vertical projection of the channel of the thin-film transistor on the substrate.

2. The display panel of claim 1, wherein, The charging suppression layer is located between the substrate and the buffer layer, and the vertical projection of the charging suppression layer on the substrate completely overlaps with the vertical projection of the buffer layer on the substrate.

3. The display panel of claim 1, wherein, The charging suppression layer is disposed in the buffer layer.

4. The display panel of claim 1, wherein, The substrate includes: a first sub-substrate and a second sub-substrate; The charging suppression layer is located between the first sub-substrate and the second sub-substrate.

5. The display panel of claim 4, wherein, Also includes: Insulating layer; The insulating layer is located between the first sub-substrate and the second sub-substrate; The charging suppression layer is disposed adjacent to the insulating layer.

6. The display panel of claim 5, wherein, include: The charging suppression layer is located on the side of the insulating layer closest to the first sub-substrate.

7. The display panel of claim 5, wherein, include: The charging suppression layer is located on the side of the insulating layer away from the first sub-substrate.

8. The display panel of claim 4, wherein, Also includes: Insulating layer; The insulating layer is located between the first sub-substrate and the second sub-substrate; The charging suppression layer is disposed within the insulating layer.

9. The display panel of claim 1, wherein, The charging suppression layer includes a low-dielectric multi-oxygen vacancy film.

10. The display panel of claim 1, wherein, The material of the charging suppression layer includes: SiOCH.