显示面板

By employing a staggered double-layer planarization aperture design in the OLED display panel, the problems of uneven thickness and bubbles in the light-emitting film layer are solved, thereby improving the brightness uniformity and reliability of the display panel.

CN224521523UActive Publication Date: 2026-07-17WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
Filing Date
2025-07-30
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

In the fabrication of OLED display panels, uneven thickness of the luminescent film layer after inkjet printing deposition of luminescent materials leads to uneven brightness, and bubbles are generated in the outer area of ​​the planarization layer during ultraviolet light irradiation, causing the display panel to fail.

Method used

The design employs a double-layer planarization structure with staggered openings in the first and second planarization layers. This ensures that the metal layer is not exposed and improves the efficiency of bubble removal through large-area openings, thus preventing display panel failure caused by bubbles.

Benefits of technology

It effectively reduces the bubble content in the outer area of ​​the planarization layer, avoids metal layer exposure and short-circuit problems, and improves the reliability and brightness uniformity of the display panel.

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Abstract

本申请涉及一种显示面板,该显示面板包括显示区以及位于显示区至少一侧的外围区,显示面板包括衬底、第一平坦层以及第二平坦层,第二平坦层设置于第一平坦层远离衬底的一侧,其中,第一平坦层设置有多个第一开孔,第二平坦层设置有多个第二开孔,第一开孔和第二开孔均位于外围区,且第一开孔在衬底上的正投影与第二开孔在衬底上的正投影不重叠;本申请通过设置两层平坦层,且在外围区,两层平坦层分别开孔,同时使两层平坦层的开孔交错设置,可实现在平坦层的外围区大面积开孔,从而有效改善平坦层中存在大量的气泡问题。
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Claims

1. A display panel, characterized by, The display panel includes a display area and a peripheral area located on at least one side of the display area. Substrate; A first planarization layer is disposed above the substrate; and A second planarization layer is disposed on the side of the first planarization layer away from the substrate; The first planarization layer is provided with a plurality of first openings, and the second planarization layer is provided with a plurality of second openings. Both the first openings and the second openings are located in the peripheral area, and the orthographic projection of the first opening on the substrate does not overlap with the orthographic projection of the second opening on the substrate.

2. The display panel of claim 1, wherein, The display panel also includes: A first metal layer is disposed on the side of the first planarization layer near the substrate and located in the peripheral region; Wherein, the orthographic projection of the first metal layer on the substrate is located within the orthographic projection range of the first flat layer on the substrate and / or the orthographic projection range of the second flat layer on the substrate.

3. The display panel of claim 2, wherein, The display panel also includes: The second metal layer is disposed on the side of the second planarization layer close to the first planarization layer and located in the peripheral area; Wherein, the orthogonal projection of the second metal layer on the substrate is located within the orthogonal projection range of the second planar layer on the substrate.

4. The display panel of claim 3, wherein, The orthographic projection of the first metal layer on the substrate at least partially overlaps with the orthographic projection of the first opening on the substrate; Wherein, the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the first opening on the substrate.

5. The display panel of claim 3, wherein, The orthographic projection of the first metal layer on the substrate does not overlap with the orthographic projection of the first opening on the substrate; The orthographic projection of the second metal layer on the substrate at least partially overlaps with the orthographic projection of the first opening on the substrate.

6. The display panel of claim 3, wherein, The orthographic projection of the first metal layer on the substrate does not overlap with the orthographic projection of the first opening on the substrate; The orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the first opening on the substrate.

7. The display panel according to claim 1, characterized in that, The diameter or width of the first opening ranges from 3μm to 10μm, and the diameter or width of the second opening ranges from 3μm to 10μm; The distance between the first opening and the second opening ranges from 20μm to 100μm.

8. The display panel of any one of claims 1 to 7, wherein, The first planarization layer is further provided with a plurality of third openings, and the second planarization layer is further provided with a plurality of fourth openings. The third openings and the fourth openings are both located in the display area, and the orthographic projection of the third opening on the substrate and the orthographic projection of the fourth opening on the substrate at least partially overlap.

9. The display panel of claim 8, wherein, The display panel also includes: A third metal layer is disposed on the side of the first planarization layer near the substrate and located in the display area; A fourth metal layer is disposed on the side of the second planarization layer away from the first planarization layer and located in the display area; The third opening and the fourth opening are provided with connecting parts, and the third metal layer is electrically connected to the fourth metal layer through the connecting parts.

10. The display panel of claim 9, wherein, The display panel also includes: A thin-film transistor layer is disposed between the substrate and the first planarization layer; The anode is disposed on the side of the second planarization layer away from the first planarization layer; A pixel definition layer is disposed on the side of the second flat layer away from the first flat layer, the pixel definition layer including a plurality of pixel openings, the pixel openings exposing at least a portion of the anode; A light-emitting functional layer is disposed within the pixel opening and located above the anode; The cathode is disposed on the side of the light-emitting functional layer and the pixel definition layer away from the second planarization layer; An encapsulation layer is disposed on the side of the cathode away from the light-emitting functional layer; The fourth metal layer includes the anode; At least a portion of the pixel definition layer or at least a portion of the encapsulation layer is disposed within the second opening.