芯片级封装体以及低热阻功率模块
By designing a chip-level package and a low thermal resistance power module, the problem of low heat dissipation efficiency on the side of the chip in the existing technology is solved, and effective heat dissipation on five heat dissipation surfaces is achieved, thereby improving the overall heat dissipation performance of the chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- MACMIC SCIENCE & TECHNOLOGY CO LTD
- Filing Date
- 2025-06-13
- Publication Date
- 2026-07-17
AI Technical Summary
In existing power module packaging structures, the sides of the chip are not effectively designed for heat dissipation, resulting in low heat dissipation efficiency.
It adopts a chip-level package structure, including a metal base plate, an insulating layer and a conductor layer. The chip is fixed on the bottom metal layer surrounded by three side plates, and five heat dissipation surfaces are formed by injection molding. Combined with the double-sided heat dissipation design of the low thermal resistance power module, the grooves and filling materials of the DBC front conductive layer are used for further heat dissipation optimization.
It improves the chip's heat dissipation efficiency, forms five heat dissipation surfaces, and enhances the chip's heat dissipation capabilities in the x and y directions, resulting in better thermal resistance performance compared to single-sided or double-sided heat dissipation.
Smart Images
Figure CN224521637U_ABST
Abstract
Claims
1. A chip-scale package, characterized by, include: Metal base plate (210) and chip (220) encapsulated within metal base plate (210); The metal base plate (210) includes: The bottom metal layer (211) has side plates (212) on its three consecutive sides. An insulating layer (213) is provided on the side of the bottom metal layer (211) where the side plate (212) is not provided; A conductor layer (214) is disposed on an insulating layer (213); The chip (220) is fixed on the bottom metal layer (211) surrounded by three side plates (212), and a sealant layer (215) is provided between the side of the chip and the side plate (212).
2. The chip-scale package according to claim 1, characterized in that, The upper surface of the chip (220) is fixed with a connecting material (221).
3. The chip-scale package according to claim 1, characterized in that, The chip (220) is connected to the conductor layer (214) by a lead (222).
4. The chip-scale package according to claim 1, characterized in that, The height of the side plate (212) is higher than the height of the upper surface of the chip (220).
5. The chip-scale package according to claim 1, characterized in that, The chip-scale package is formed by injection molding.
6. A low thermal resistance power module characterized by, include: Two encapsulated parts (100) are arranged opposite each other at the top and bottom. The chip-scale package (200) as described in any one of claims 1-5 is disposed on the opposite surface of the partial package (100).
7. The low thermal resistance power module according to claim 6, characterized in that, The partial package (100) includes: a heat sink (110), a DBC back conductive layer (120), a DBC ceramic insulating layer (130), and a DBC front conductive layer (140) arranged sequentially from the outside to the inside. The chip-scale package (200) is disposed on the front conductive layer (140) of the DBC.
8. The low thermal resistance power module according to claim 7, characterized in that, The DBC front conductive layer (140) has a groove (141). The chip-scale package (200) is fixed in the groove (141); A filler material (142) is provided between the chip-scale package (200) and the inner wall of the groove (141).
9. The low thermal resistance power module according to claim 7, characterized in that, The depth of the chip-scale package (200) embedded in the groove (141) is greater than 0 mm and less than 0.3 mm.
10. The low thermal resistance power module according to claim 7, characterized in that, The opposing surfaces of the two partial encapsulation bodies (100) are filled with sealant (150).