一种芯片封装结构
By combining a substrate, heat sink frame, and heat pipe, the balance between heat dissipation efficiency and device size in chip packaging is solved, achieving efficient heat dissipation without affecting chip performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN BINFENG PRECISION KNIFE SAW TECHNOLOGY CO LTD
- Filing Date
- 2025-06-30
- Publication Date
- 2026-07-17
AI Technical Summary
Existing chip packaging structures struggle to balance heat dissipation efficiency and device size, leading to problems such as excessively large heat dissipation devices or reduced chip performance.
It adopts a combination structure of substrate, heat sink frame and heat pipe, and connects chip to package pin by wire bonding or flip-chip bonding. The heat sink frame conducts heat, the heat pipe increases the airflow area and improves the airflow speed, and the combination of insulating thermal pad and thermal grease enhances the heat conduction efficiency.
It improves the chip's heat dissipation efficiency, prevents heat buildup, keeps the chip working properly, and does not increase the size of the package structure.
Smart Images
Figure CN224521638U_ABST
Abstract
Claims
1. A chip package structure comprising a substrate (1) and a wafer (2), characterized in that, The substrate (1) is provided with an outwardly extending package pin (101), and the chip (2) is electrically connected to the package pin (101); a heat sink frame (3) is attached to the top of the chip (2), and a heat sink pipe (301) is provided inside the heat sink frame (3) from front to back with the middle of the inside and the front to back connected; a package shell (4) is provided on the top of the substrate (1), and the package shell (4) wraps the chip (2) and the heat sink frame (3).
2. The chip package structure of claim 1, wherein: The wafer (2) is connected to the package pins (101) by wire bonding or flip-chip bonding.
3. The chip package structure of claim 1, wherein: The surface areas of the substrate (1) and the heat sink (3) are both greater than the surface area of the wafer (2).
4. The chip package structure of claim 1, wherein: An insulating thermally conductive pad (302) is provided between the heat sink (3) and the chip (2).
5. The chip package structure of claim 1, wherein: The two ends of the heat pipe (301) extend from the encapsulation shell (4).
6. The chip package structure of claim 1, wherein: There are several heat dissipation pipes (301), which are evenly arranged from left to right.
7. The chip package structure of claim 6, wherein: The space between the heat pipe (301) and the interior of the heat sink frame (3) is filled with thermally conductive silicone grease.