半导体封装结构
By setting openings and transition conductive structures on the packaging structure, double-sided heat dissipation of the semiconductor packaging structure is achieved, solving the problem of insufficient single-sided heat dissipation, improving heat dissipation capacity and reliability, and making it suitable for high power density applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHONGQING PINGCHUANG SEMICON RES INST CO LTD
- Filing Date
- 2025-07-02
- Publication Date
- 2026-07-17
AI Technical Summary
Existing semiconductor packaging structures are mainly based on single-sided heat dissipation, resulting in insufficient heat dissipation capacity and inability to meet the requirements of high power density.
By setting an opening in the packaging structure to expose the part of the first electrical connection portion facing away from the heat sink, double-sided heat dissipation of the semiconductor packaging structure is achieved, and the difference in thermal expansion coefficient is mitigated by using a transition conductive structure, thereby enhancing the heat dissipation path and structural reliability.
It improves the heat dissipation capability of semiconductor packaging structures, enabling them to conduct larger currents at the same junction temperature, reducing the size of the application and achieving weight reduction, thereby improving the reliability and fabrication yield of the structure.
Smart Images
Figure CN224521639U_ABST
Abstract
Claims
1. A semiconductor package structure, comprising: include: Heat sink, The first pin is spaced apart from the heat sink. A chip is disposed on the heat sink. The chip includes a first electrode and a second electrode spaced apart. One of the first electrode and the second electrode is the source electrode, and the other is the drain electrode. The second electrode is connected to the heat sink. An interconnecting conductive structure is disposed on the side of the chip away from the heat sink. The interconnecting conductive structure includes a first electrical connection portion and a second electrical connection portion that are connected to each other. The first electrical connection portion is connected to the second electrode, and the second electrical connection portion is connected to the first pin. The packaging structure is configured to encapsulate the heat sink, the first pin, the chip, and the interconnect conductive structure; The packaging structure has an opening configured to expose at least a portion of the surface of the first electrical connection that faces away from the heat sink.
2. The semiconductor package structure of claim 1, wherein, The semiconductor packaging structure further includes a transition conductive structure, which is disposed between the chip and the first electrical connection portion and connected to the first electrode and the first electrical connection portion; the linear thermal expansion coefficient of the transition conductive structure is greater than the linear thermal expansion coefficient of the chip and less than the linear thermal expansion coefficient of the interconnect conductive structure.
3. The semiconductor package structure of claim 1, wherein, The side of the first electrical connection portion facing away from the heat sink is higher than the side of the second electrical connection portion facing away from the first pin. The surface of the first electrical connection portion facing away from the heat sink is flush with the surface of the encapsulation structure facing away from the heat sink. The encapsulation structure covers the side of the second electrical connection portion facing away from the first pin. The interconnected conductive structure further includes a third electrical connection portion, which is disposed between the first electrical connection portion and the second electrical connection portion, and its opposite ends are respectively connected to the first electrical connection portion and the second electrical connection portion.
4. The semiconductor package structure of claim 2, wherein, The orthographic projection of the first electrical connection portion on the heat sink is greater than the orthographic projection of the transition conductive structure on the heat sink, and the first electrical connection portion can cover the side of the transition conductive structure facing away from the chip.
5. The semiconductor package structure of claim 1, wherein, A limit slot is provided on the first pin; The second electrical connection portion has a limiting protrusion on the side near the first pin, and the limiting protrusion is engaged in the limiting groove.
6. The semiconductor package structure of claim 5, wherein, The heat sink and the first pin are arranged at intervals along the first direction; The first pin has limiting grooves on both sides opposite to each other in the second direction; The interconnected conductive structure is provided with limiting protrusions on both sides of the opposite sides in the second direction, and the limiting protrusions and the limiting grooves are engaged one-to-one. The second direction intersects with the first direction.
7. The semiconductor package structure of claim 1, wherein, The first pin and the interconnect conductive structure are an integral structure.
8. The semiconductor package structure of claim 1, wherein, The chip includes a gate, and the semiconductor package structure includes a gate connector and a second pin. The second pin is spaced apart from the heat sink and the first pin. One end of the gate connector is connected to the second pin, and the other end of the gate connector is connected to the gate. The side of the gate connector facing away from the second pin is lower than the side of the interconnect conductive structure facing away from the heat sink.
9. The semiconductor packaging structure according to claim 8, characterized in that, The gate connector and the second pin are integrated into one unit.
10. The semiconductor package structure of claim 2, wherein, The chip is one of a silicon chip and a silicon carbide chip, the interconnection conductive structure is a copper layer, and the transition conductive structure is a nickel-molybdenum-plated sheet.