一种ESOP引线框架及封装模块
By using the ESOP lead frame base island design and heat sink structure, the dielectric and heat dissipation problems of power device packaged products are solved, realizing the integration of four chips and efficient heat dissipation, reducing cost and parasitic parameters.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 四川明泰微电子有限公司
- Filing Date
- 2025-08-12
- Publication Date
- 2026-07-17
AI Technical Summary
Existing power device co-packaged products face challenges in dielectric properties and heat dissipation, especially with the increasing application of GAN chips, where existing solutions are costly and ineffective.
The design employs an ESOP lead frame, which integrates four chips by setting up three base islands and optimizing their connection and spacing. A heat sink is formed on the third base island, and combined with structures such as glue holes and anti-overflow grooves, electrical connection and efficient heat dissipation are achieved.
The integration of four chips within a limited space reduces the impact of parasitic parameters, improves heat dissipation, reduces costs, and enhances structural stability and electrical isolation.
Smart Images
Figure CN224521657U_ABST
Abstract
Claims
1. An ESOP lead frame comprising package units formed in a rectangular array on a frame body, characterized in that, The packaging unit includes: The base island region located in the middle includes the first base island (A9), the second base island (A10), and the third base island (A11) that are spaced apart from each other. The first pin (A1), the second pin (A2), the third pin (A3), and the fourth pin (A4) are located on one side of the base island area and are arranged sequentially at intervals. The fifth pin (A5), the sixth pin (A6), the seventh pin (A7), and the eighth pin (A8) are located on the other side of the base island area and are arranged sequentially at intervals. Among them, the first base island (A9) is connected to the eighth pin (A8), the second base island (A10) is connected to the first pin (A1), the first base island (A9) and the second base island (A10) are arranged opposite to each other, and the third base island (A11) is located in the area enclosed by the first base island (A9), the second base island (A10), the second pin (A2), the third pin (A3), the fourth pin (A4), the fifth pin (A5), the sixth pin (A6), and the seventh pin (A7). The two ends of the third base island (A11) are connected to the frame body through base island connecting ribs.
2. The ESOP lead frame of claim 1, wherein, The horizontal projected area of the third base island (A11) is greater than that of the first base island (A9) and the second base island (A10).
3. The ESOP lead frame of claim 1, wherein, The fourth pin (A4) and the fifth pin (A5) are opposite each other and both extend inward to form an extension segment. The extension segment is spaced apart from one end of the third base island (A11) and is spaced apart from the base island by the connecting rib.
4. The ESOP lead frame of claim 1, wherein, The first base island (A9) is a flat base island or a concave base island, and the second base island (A10) is a flat base island or a concave base island.
5. The ESOP lead frame of claim 1, wherein, At least one pin has a locking hole (A13).
6. The ESOP lead frame of claim 1, wherein, The third base island (A11) is recessed to expose the back of the third base island (A11) after molding.
7. The ESOP lead frame of claim 1, wherein, A ring of overflow prevention grooves (A14) is provided along the upper edge of the third base island (A11).
8. The ESOP lead frame of claim 1, wherein, A ring of counter-pressure grooves (A15) is provided along the upper edge of the third base island (A11).
9. A package module, characterized by, The package includes a molding compound and an ESOP lead frame as described in any one of claims 1-8. A third base island (A11) is provided with a driver IC chip (4) and a second MOS chip (3). A first base island (A9) is provided with one of an FRD chip (1) or a first MOS chip (2). A second base island (A10) is provided with the other of an FRD chip (1) or a first MOS chip (2). The molding compound encapsulates the packaging unit and each chip.
10. The package module of claim 9, wherein, The driver IC chip (4) is bonded to the second pin (A2), the third pin (A3), the third base island (A11), the fourth pin (A4), the sixth pin (A6) and the chip on the second base island (A10). The chip on the second base island (A10) is bonded to the second pin (A2). The second MOS chip (3) is bonded to the third base island (A11), the chip on the first base island (A9) and the second base island (A10).