半导体装置

Abstract

一种半导体装置包含基板、导电垫、钝化层与导电凸块。导电垫在基板上。钝化层在基板与导电垫上，且在横截面视图中，钝化层具有接触导电垫的多个第一部分与多个第二部分，第一部分具有第一高度，第二部分具有大于第一高度的第二高度。导电凸块覆盖钝化层的第一部分与第二部分，且导电凸块贯穿钝化层以接触导电垫。本实用新型的钝化层不易在后续的接合工艺期间破裂，因此可延长半导体装置的寿命。

Claims

1. A semiconductor device, characterized by comprising: Include: substrate; A conductive pad is placed on the substrate; A passivation layer is provided on the substrate and the conductive pad, and in a cross-sectional view, the passivation layer has a plurality of first portions and a plurality of second portions that contact the conductive pad, the plurality of first portions having a first height and the plurality of second portions having a second height greater than the first height; as well as A conductive bump covers the plurality of first portions and the plurality of second portions of the passivation layer, and the conductive bump penetrates the passivation layer to contact the conductive pad.

2. The semiconductor device according to claim 1, wherein The conductive bump includes: The column, on the plurality of first portions and the plurality of second portions of the passivation layer; and Solder, on the column, the top surface of the column includes a horizontal plane and a convex surface connecting the horizontal plane, the highest point of the convex surface being higher than the horizontal plane.

3. The semiconductor device according to claim 1, wherein The plurality of second portions of the passivation layer are located at the center of the conductive pad, and the plurality of first portions of the passivation layer surround the plurality of second portions of the passivation layer.

4. The semiconductor device according to claim 1, wherein In the cross-sectional view, the widths of the plurality of first portions and the plurality of second portions of the passivation layer are equal.

5. The semiconductor device according to claim 1, wherein The conductive bump includes: A column, wherein the top surface of the column includes a first horizontal plane and a plurality of protrusions, the highest point of the plurality of protrusions being higher than the first horizontal plane, and the plurality of protrusions being spaced apart from each other in the cross-sectional view; as well as Solder, on the column.

6. The semiconductor device according to claim 5, wherein The conductive bump further includes: An alloy layer is located between the column and the solder.

7. The semiconductor device according to claim 5, wherein The plurality of first portions and the plurality of second portions of the passivation layer are arranged in an intersecting manner, and the plurality of second portions of the passivation layer are aligned with the plurality of protrusions.

8. The semiconductor device according to claim 7, wherein The plurality of protrusions adjacent to each other have a plurality of second horizontal surfaces connecting the plurality of protrusions, and the plurality of first portions of the passivation layer correspond to the plurality of second horizontal surfaces.

9. The semiconductor device according to claim 5, wherein The plurality of protrusions are interspersed with recesses, the plurality of second portions of the passivation layer correspond to the plurality of protrusions, and the recesses correspond to the central part of the conductive pad that is not covered by the passivation layer, and the lowest point of the recesses is lower than the first horizontal plane.

10. The semiconductor device according to claim 1, wherein In the cross-sectional view, the width of the central one of the plurality of second portions of the passivation layer is greater than the width of any one of the plurality of first portions and any of the remaining plurality of second portions.

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