一种三维集成芯片结构

Abstract

本实用新型属于半导体集成电路技术领域，特别涉及一种三维集成芯片结构。包括散热基板，为微流道散热结构；多层晶圆电路，布设于所述散热基板上；通过互连钨通孔和互连金属将相邻的两层晶圆电路相连，以形成三维集成芯片。所述多层晶圆电路由下至上依次包括第一层晶圆电路、第二层晶圆电路、…第n层晶圆电路；其中所述第一层晶圆电路采用体硅CMOS或SOI CMOS工艺圆片制备，所述第二层晶圆电路至所述第n层晶圆电路采用SOI CMOS工艺圆片制备。本实用新型不仅将不同的功能的晶圆实现垂直堆叠，极大的缩小了芯片的面积，而且能够实现亚微米级别的层间距，缩短芯片间互连距离，大幅提升器件的带宽，降低芯片的延迟。

Claims

1. A three-dimensional integrated chip structure, comprising: include: The heat dissipation substrate (1) is a microchannel heat dissipation structure; Multilayer wafer circuits are arranged on the heat dissipation substrate (1); adjacent wafer circuits are connected by interconnect tungsten vias (7) and interconnect metals (8) to form a three-dimensional integrated chip.

2. A three-dimensional integrated chip structure as in claim 1, wherein, The multilayer wafer circuit comprises, from bottom to top, a first layer wafer circuit, a second layer wafer circuit, ..., an nth layer wafer circuit; wherein the first layer wafer circuit is fabricated using bulk silicon CMOS or SOI CMOS process wafers, and the second to nth layer wafer circuits are fabricated using SOI CMOS process wafers.

3. A three-dimensional integrated chip structure as in claim 2, wherein, Each layer of the multilayer wafer circuit includes: a Si active layer (2), an STI isolation region (3), a source / drain implantation layer (4), a SiO2 dielectric layer (5), a POLY polysilicon layer (9), and a GOX gate oxide dielectric layer (10); wherein the Si active layer (2) is provided with a source / drain implantation layer (4), and the source / drain implantation layer (4) is isolated by the STI isolation region (3) distributed on the outside; the GOX gate oxide dielectric layer (10) and the POLY polysilicon layer (9) are sequentially provided above the Si active layer (2); and the SiO2 dielectric layer (5) is provided on the source / drain implantation layer (4), the POLY polysilicon layer (9), and the STI isolation region (3).

4. A three-dimensional integrated chip structure as in claim 3, wherein, The source-drain implantation layer (4) in the first layer wafer circuit is implanted with P-type or N-type impurities; the source-drain implantation layer (4) in the second layer wafer circuit to the nth layer wafer circuit is implanted with N-type impurities.

5. The three-dimensional integrated chip structure of claim 3, wherein, The second layer wafer circuit to the bottom of the nth layer wafer circuit also includes a buried oxide layer (6).

6. A three-dimensional integrated chip structure as in claim 5, wherein, The interconnect tungsten via (7) includes: source-drain interconnect tungsten via and gate interconnect tungsten via; in the two adjacent wafer circuits, the source-drain interconnect tungsten via or the gate interconnect tungsten via is opened from bottom to top along the bottom SiO2 dielectric layer (5), the BOX buried oxide layer (6), the STI isolation region (3) and the upper SiO2 dielectric layer (5), and the source-drain interconnect tungsten via connects the bottom and upper source-drain injection layers (4) respectively, and the upper end of the source-drain interconnect tungsten via is exposed on the surface of the upper SiO2 dielectric layer (5); the gate interconnect tungsten via connects the bottom and upper POLY polysilicon layers (9) respectively, and the upper end of the gate interconnect tungsten via is exposed on the surface of the upper SiO2 dielectric layer (5).

7. A three-dimensional integrated chip structure as in claim 6, wherein, The interconnect metal (8) in the source-drain interconnect tungsten via and the gate interconnect tungsten via is a damascus copper interconnect structure.

8. A three-dimensional integrated chip structure as claimed in any one of claims 1 to 7, characterized in that Each wafer circuit layer is a circuit formed by a single transistor device or multiple transistor devices interconnected.

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