Wafer bonding apparatus and semiconductor processing system

Abstract

The application discloses a wafer bonding device and a semiconductor processing system. The device comprises a main body, a turnover device, a pressure device and a coating device. The main body is formed with a vacuum chamber, and comprises a top wall and a bottom wall. The turnover device is arranged on the bottom wall and comprises a first wafer carrier, a second wafer carrier and a driving module. The first wafer carrier and the second wafer carrier can be used for carrying a first wafer and a second wafer respectively. The driving module is used for driving at least one of the first wafer carrier and the second wafer carrier, so that the first wafer is turned over and aligned and attached to the second wafer to obtain a wafer stack. The pressure device is arranged on the top wall and is used for applying pressure to the wafer stack after the first wafer is turned over and aligned and attached to the second wafer. The coating device is arranged on the main body, and at least a part of the coating device is arranged in the vacuum chamber. The coating device is used for coating the surface of the first wafer or the second wafer. The device has the advantages of good bonding effect and the like.

Description

Technical Field

[0001] This application relates to the field of wafer bonding technology, and more particularly to a wafer bonding device and a semiconductor processing system. Background Technology

[0002] With the widespread application of wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3) in power electronics, radio frequency communications, and other fields, the power density and maximum junction temperature of related semiconductor devices are constantly rising, bringing about numerous problems. Especially under high junction temperature conditions, the stability and lifespan of semiconductor devices are severely affected. However, current semiconductor processing equipment and technology have many shortcomings in terms of heat dissipation solutions. While traditional heat dissipation solutions can achieve a certain level of cooling effect, their implementation often leads to secondary problems such as decreased yield, reduced product performance, and weakened mechanical structure strength. Therefore, how to improve the heat dissipation efficiency of semiconductor products by modifying related equipment, thereby enhancing their stability and reliability, has become a critical issue that urgently needs to be addressed. Utility Model Content

[0003] In view of this, this application proposes a wafer bonding apparatus and a semiconductor processing system, wherein the wafer bonding apparatus has the following features.

[0004] In a first aspect, this application proposes a wafer bonding apparatus, which includes:

[0005] The main body has a vacuum chamber and includes a top wall and a bottom wall.

[0006] A flipping device is disposed on the bottom wall. The flipping device includes a first wafer carrier, a second wafer carrier, and a driving module. The first wafer carrier and the second wafer carrier can be used to carry the first wafer and the second wafer, respectively. The driving module is used to drive at least one of the first wafer carrier and the second wafer carrier to flip the first wafer and align and attach it to the second wafer to obtain a wafer stack.

[0007] A pressure device is located on the top wall and is used to apply pressure to the wafer stack after the first wafer is flipped and aligned and attached to the second wafer.

[0008] A coating apparatus is disposed in a main body, at least a portion of which is disposed in a vacuum chamber. The coating apparatus is used to coat the surface of a first wafer and / or a second wafer.

[0009] In some embodiments, the wafer bonding apparatus further includes an activation device disposed in the main body, at least a portion of which is disposed in a vacuum chamber for surface activation treatment of the first wafer and / or the second wafer.

[0010] In some embodiments, the wafer bonding apparatus further includes a rotating device disposed on the bottom wall. The rotating device includes a rotating motor and a turntable. The rotating motor is used to drive the turntable to rotate, and a flipping device is disposed on the turntable.

[0011] In some embodiments, the coating apparatus includes a target gun for coating the surface of a first wafer and / or a second wafer by a magnetron sputtering process.

[0012] In some embodiments, the coating apparatus includes a plurality of target guns, which are evenly distributed and disposed on the same annular indexing circumference of the top wall, and the angle between the central axis of adjacent target guns and the central axis of the annular indexing circumference is equal.

[0013] In some embodiments, a first baffle is provided on the flipping device or the bottom wall, at least a portion of the first baffle being configured to correspond to the target material; and / or, the coating device includes a target material and a second baffle, at least a portion of the second baffle being configured to correspond to the target material.

[0014] In some embodiments, the first wafer carrier and the second wafer carrier are respectively provided with a first adsorption port and a second adsorption port, and the wafer bonding apparatus further includes:

[0015] A vacuum adsorber is connected to a first adsorption port and / or a second adsorption port. The vacuum adsorber is used to fix a first wafer and / or a second wafer by adsorption.

[0016] In some embodiments, the first wafer carrier and / or the second wafer carrier are provided with heating coils; and / or, the pressure device includes an air cushion indenter.

[0017] In some embodiments, the first wafer carrier and / or the second wafer carrier are provided with limiters.

[0018] Secondly, this application proposes a semiconductor processing system, which includes a wafer bonding apparatus as described in any embodiment of this application.

[0019] The wafer bonding equipment and semiconductor processing system proposed in this application, on the one hand, through the design of the mechanical structure, make it possible to perform thin film deposition, flipping and bonding operations on two wafers in the same vacuum / negative pressure or inert gas environment. This avoids problems such as oxidation deactivation and particle contamination of the related coatings when the wafers are transferred in the atmosphere or inert gas, which helps to form a dense, pore-free, and gapless thermal interface, improves thermal conductivity and heat dissipation performance, improves the stability and reliability of semiconductor products, and improves the production efficiency and yield of semiconductor products. On the other hand, based on the integrated, miniaturized, and efficient equipment design, it makes it possible to form multi-layer, high-quality coatings on semiconductor products such as wafer stacks. This not only improves the thermal conductivity and mechanical strength of the thermal interface, but also enables the equipment to achieve good bonding results at lower temperatures and / or pressures. This reduces the process difficulty and related costs, and avoids the semiconductor material from failing due to thermal sensitivity at excessively high temperatures or the wafer from cracking under excessively high pressures. This improves the production efficiency and process yield of semiconductor products, and enhances the stability and reliability of semiconductor products. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a first wafer and a second wafer provided in an embodiment of this application;

[0022] Figure 2 yes Figure 1 A schematic diagram of the structure of the wafer stack of the first and second wafers shown;

[0023] Figure 3 This is a schematic diagram of the structure of a first wafer and a second wafer provided in an embodiment of this application;

[0024] Figure 4 yes Figure 3 A schematic diagram of the structure of the wafer stack of the first and second wafers shown;

[0025] Figure 5 This is a schematic diagram of the structure of a first wafer and a second wafer provided in an embodiment of this application;

[0026] Figure 6 yes Figure 5 A schematic diagram of the structure of the wafer stack of the first and second wafers shown;

[0027] Figure 7 This is a schematic diagram of the structure of a wafer bonding device provided in an embodiment of this application;

[0028] Figure 8 This is a cross-sectional view of a wafer bonding apparatus provided in one embodiment of this application;

[0029] Figure 9 This is a schematic diagram of the structure of a flipping device provided in an embodiment of this application;

[0030] Figure 10 This is a schematic diagram of another flipping device provided in an embodiment of this application;

[0031] Figure 11 This is a schematic diagram of the structure of a coating apparatus provided in one embodiment of this application;

[0032] Figure 12 This is a schematic diagram of the structure of a coating apparatus provided in one embodiment of this application;

[0033] Figure 13 This is a schematic flowchart of a wafer bonding method provided in an embodiment of this application;

[0034] Figure 14 This is a schematic flowchart of a wafer setup method provided in an embodiment of this application;

[0035] Figure 15 This is a schematic flowchart illustrating the steps of a wafer deposition method provided in an embodiment of this application.

[0036] Explanation of reference numerals in the attached figures:

[0037] 100. Wafer bonding equipment; 10. Wafer stack; 11. First wafer; 111. Bonding surface of the first wafer; 12. Second wafer; 121. Bonding surface of the second wafer; 13. Adhesion layer; 131. First adhesion layer; 132. Second adhesion layer; 14. Atom diffusion layer; 141. First atom diffusion layer; 142. Second atom diffusion layer; 20. Main body; 21. Vacuum chamber; 22. Top wall; 23. Bottom wall; 30. Flipping device ; 31. First wafer carrier; 311. First adsorption port; 32. Second wafer carrier; 321. Second adsorption port; 33. Drive module; 34. Positioning push rod; 40. Pressure device; 41. Air cushion pressure head; 50. Coating device; 51. Target gun; 511. Annular indexing circumference; 52. Target material; 53. Cover plate; 60. Activation device; 70. Rotation device; 71. Rotating motor; 72. Turntable; 81. First baffle; 82. Second baffle. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0040] It should be understood that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0041] It should also be understood that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or may be connected to an intermediary element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element through an intermediary element.

[0042] The terminology used in this application specification is for the purpose of describing particular embodiments only and is not intended to limit the application. Descriptions using terms such as "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature.

[0043] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0044] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0045] With the rapid development of emerging industries such as new energy, robotics, chips, and artificial intelligence, semiconductor products such as power devices and power ICs are being used more and more widely in these fields. Among them, high-power semiconductor materials such as gallium nitride (GaN) and gallium oxide (Ga2O3), with their excellent performance, including high power density, high breakdown electric field strength, low on-resistance, and high thermal conductivity, have received widespread attention and favor from the semiconductor manufacturing and packaging industries and product users, meeting the demands of modern electronic devices for high-efficiency, miniaturized, and highly reliable semiconductor products. However, as the power density and junction temperature of related semiconductor materials and devices continue to rise, heat dissipation has become a key challenge hindering further industrial development.

[0046] While traditional thermal management techniques struggle to effectively address the heat dissipation issues of high-power devices, heat dissipation materials such as diamond and graphene, due to their extremely high thermal conductivity, hold great potential for application in heat dissipation technology. Improving the heat dissipation capacity of semiconductor devices, and thus enhancing their stability and reliability, by bonding these heat dissipation materials to relevant semiconductor wafers, has become a pressing technical challenge.

[0047] To address the aforementioned problems, this application proposes a semiconductor product. Please refer to [link / reference]. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a first wafer and a second wafer provided in an embodiment of this application. Figure 2 yes Figure 1 The diagram shows the structure of the wafer stack of the first and second wafers.

[0048] like Figure 1 and Figure 2 As shown, the material of the first wafer 11 may include diamond, and the material of the second wafer 12 may include sapphire, Si, SiO2, Ge, GaN, AlN, SiC, lithium niobate, lithium tantalate, or III-V compound semiconductors.

[0049] It should be understood that, due to the thermal conductivity of diamond reaching or exceeding 2000 W / (m·K), it possesses excellent thermal conductivity. When bonded to a semiconductor wafer, the resulting wafer stack 10 can be used to fabricate semiconductor products with better heat dissipation, thereby preventing excessively high junction temperatures from affecting the reliability, stability, and lifespan of the wafer stack 10 and other semiconductor products. It should be further understood that the first wafer 11 and the second wafer 12 can be bonded to obtain semiconductor products such as the wafer stack 10, and other semiconductor products can also be fabricated based on the wafer stack 10 and other semiconductor products. The semiconductor products protected in this application include, but are not limited to, the wafer stack 10 and other semiconductor products such as memory, processors, discrete devices, and power ICs fabricated based on the wafer stack 10.

[0050] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0051] In some embodiments, bonding can be performed between the bonding surface 111 of the first wafer 11 and the bonding surface 121 of the second wafer 12. An adhesion layer 13 may be formed on the bonding surface 121 of the first wafer 11 and the second wafer 12. It should be understood that by setting the first adhesion layer 131, both the bonding surface 111 of the first wafer 11 and the bonding surface 121 of the second wafer 12 are coated with a single layer film. On the one hand, a metal layer such as Ti or Ni with good adhesion can be deposited on the surface of the first wafer 11, and the direct bonding of heterogeneous wafers is transformed into the bonding of the interface of two metal layers. This prevents the reduction of the mechanical structural strength of semiconductor products such as wafer stack 10 due to the difference in thermal expansion coefficients of the first wafer 11 and the second wafer 12 at high or low operating junction temperatures, and also prevents internal structural strain failure. On the other hand, it can make full use of the advantages of metals such as Ti, Cr, Ta, Mo, and W, such as high hardness, high density, high temperature resistance, stable properties and strong alloying ability, to enhance the bonding between the metal and the substrate, and further enhance the reliability, stability and heat dissipation performance of semiconductor products such as wafer stack 10.

[0052] In some embodiments, the thickness of the adhesion layer 13 can be 5 nm to 100 nm, and the material of the adhesion layer 13 can include Ti, Cu, Al, Ni, Cr, Ta, Mo, or W. For example, an adhesion layer 13 with a thickness of 10 nm can be deposited using Ti. Typically, but not limitingly, the thickness of the adhesion layer 13 can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, or a range of any two values ​​thereto.

[0053] Furthermore, the bonding surfaces 111 of the first wafer 11 and / or 121 of the second wafer 12 can be polished to reduce surface roughness, ensure a smooth and clean bonding interface, and improve the bonding effect. This allows a dense, non-porous thermal interface to be formed on the bonding surface, effectively transferring heat generated by semiconductor materials such as Si, SiO2, Ge, GaN, AlN, SiC, lithium niobate, lithium tantalate, or III-V compound semiconductors to the diamond substrate for heat dissipation, thereby improving the reliability, stability, and heat dissipation performance of semiconductor products such as the wafer stack 10. Specifically, polishing can be performed using methods such as chemical mechanical polishing (CMP). For example, the surface roughness of the first wafer 11 and / or the second wafer 12 can be less than or equal to 1 nm, and the warpage can be less than or equal to 30 μm.

[0054] Please see Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the structure of a first wafer 11 and a second wafer 12 provided in an embodiment of this application. Figure 4 yes Figure 3 The diagram shows a schematic representation of the wafer stack 10 comprising the first wafer 11 and the second wafer 12. Figure 3 and Figure 4 As shown, an adhesion layer 13 can be formed on the bonding surface 111 of the first wafer 11 and the bonding surface 121 of the second wafer 12, and an atomic diffusion layer 14 can be formed on the adhesion layer 13 of the first wafer 11 and the second wafer 12. The material of the adhesion layer 13 includes Ti, Ni, Cr, Ta, Mo, or W, and the material of the atomic diffusion layer 14 includes Au, Ag, Cu, or Al. This results in both the bonding surface 111 of the first wafer 11 and the bonding surface 121 of the second wafer 12 being coated with a double-layer film. It should be understood that a single-layer film can also be deposited on the bonding surface of one of the first wafer 11 and the second wafer 12, and a double-layer film can be deposited on the bonding surface of the other; no specific limitation is made here.

[0055] It should be understood that since metals such as Cu have strong diffusion capabilities, they can easily penetrate into the second wafer 12 and affect performance. Therefore, the first adhesion layer 13, which uses Ti, Cr, Ta, Mo or W, can also serve as a barrier layer to prevent Cu from diffusing back into the semiconductor material or device, thus avoiding performance impact and improving the yield of semiconductor products.

[0056] Specifically, the material of the atomic diffusion layer 14 may include Au, Ag, Cu, or Al, and the thickness of the atomic diffusion layer 14 may be 20 nm to 1000 nm, for example, 200 nm. Typically, but not limitingly, the thickness of the atomic diffusion layer 14 may be 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, or a range of any two of these values.

[0057] Please refer to the supplementary information. Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the structure of a first wafer 11 and a second wafer 12 provided in an embodiment of this application. Figure 6 yes Figure 5 The diagram shows a schematic representation of the wafer stack 10 comprising the first wafer 11 and the second wafer 12. Figure 5 and Figure 6 As shown, an adhesion layer 13 and an atomic diffusion layer 14 may be formed on the bonding surface 121 of the first wafer 11 and / or the second wafer 12. The adhesion layer 13 includes a first adhesion layer 131 and a second adhesion layer 132, and the atomic diffusion layer 14 includes a first atomic diffusion layer 141 and a second atomic diffusion layer 142. The first adhesion layer 131 is formed on the bonding surface 111 of the first wafer 11 and the bonding surface 121 of the second wafer 12. The first atomic diffusion layer 141 is formed on the first adhesion layer 131, the second adhesion layer 132 is formed on the first atomic diffusion layer 141, and the second atomic diffusion layer 142 is formed on the second adhesion layer 132.

[0058] It should be understood that since the adhesion layer 13 and the atomic diffusion layer 14 can be the outermost metal films on the bonding surfaces 121 of the first wafer 11 and / or the second wafer 12, in addition to serving to bond the substrate and the metal layer and provide atomic diffusion channels, they can also achieve auxiliary bonding effects such as lowering the diffusion temperature and improving wettability. Therefore, the adhesion layer 13 or the atomic diffusion layer 14 located on the outermost bonding surfaces 121 of the first wafer 11 and / or the second wafer 12 can also be referred to as a bonding layer. The thickness of the bonding layer can be 20 nm to 500 nm. For example, the material of the bonding layer can include Au, and the thickness of the bonding layer is 50 nm. The bonding layer can also include nano-metal or non-metallic film layers.

[0059] Typically, but not limitingly, the thickness of the bonding layer can be 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, 320 nm, 340 nm, 360 nm, 380 nm, 400 nm, 420 nm, 440 nm, 460 nm, 480 nm, 500 nm, or a range of any two of these values.

[0060] In some embodiments, the material used for the outermost metal film on the bonding surface 111 of the first wafer 11 can be the same as the material used for the outermost metal film on the bonding surface 121 of the second wafer 12. It should be understood that by utilizing a symmetrical structure, symmetrical diffusion can be achieved, resulting in a more uniform material at the bonding / heat transfer interface, higher bonding strength, and better thermal conductivity. For example, Ti / Cu / Au can be used as the material for the outermost metal film on the bonding surface 111 of the first wafer 11 and the bonding surface 121 of the second wafer 12, thus achieving symmetrical diffusion.

[0061] In other embodiments, the material used for the outermost metal film on the bonding surface 111 of the first wafer 11 may be different from the material used for the outermost metal film on the bonding surface 121 of the second wafer 12. It should be understood that by utilizing heterostructures, interfacial metal interdiffusion reactions can be achieved to meet specific process requirements and performance optimizations.

[0062] In some embodiments, Ti, Cu, and / or Au can be used to form a metal stack structure, or Ta, Cu, and / or Au can be used to form a metal stack structure. By forming a multilayer structure, the diffusion reaction effect of each layer can be improved, thereby enhancing the overall effect of the wafer bonding process and improving the heat dissipation performance of semiconductor products. For example, on any wafer, a first adhesion layer 131 can be formed using Ti, a first atomic diffusion layer 141 can be formed using Cu, and a second adhesion layer 132 can be formed using Au.

[0063] It should be understood that by setting the atomic diffusion layer 14, atomic diffusion channels can be provided during the bonding process, thereby improving the bonding effect, enhancing the quality of the thermal interface formed by bonding, and improving the reliability, stability and heat dissipation performance of semiconductor products.

[0064] It should be further understood that when the bonding of the first wafer 11 and the second wafer 12 is completed, the layers between the bonding surfaces 121 of the first wafer 11 and the second wafer 12 may blur the boundaries between the layers or merge at least some of the layers. Therefore, those skilled in the art can understand that although some layers have merged or the layer boundaries have become blurred after bonding, this does not mean that the protection scope of this application can be escaped by changing the number of bonding layers or transition layers.

[0065] Please see Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of the structure of a wafer bonding apparatus 100 provided in an embodiment of this application. Figure 8 This is a cross-sectional view of a wafer bonding apparatus 100 provided in one embodiment of this application. Figure 7 and Figure 8 As shown in the illustration, this application also proposes a wafer bonding apparatus 100, which may include a main body 20, a flipping device 30, a pressure device 40, and a coating device 50. The main body 20 has a vacuum chamber 21, and the flipping device 30, pressure device 40, and coating device 50 utilize this vacuum chamber 21 to perform wafer coating, flipping bonding, and bonding. It should be understood that the vacuum chamber 21 can be used to create a vacuum, negative pressure, or inert gas environment, and no specific limitations are imposed here.

[0066] It should be noted that, due to limitations in equipment technology, each step of the traditional bonding process can often only be carried out using a variety of specialized equipment. For example, after the coating stage in the traditional process, the wafer needs to be transferred from the coating equipment to an atmospheric or inert gas environment and then bonded in an alignment and bonding equipment to form a wafer stack 10. The wafer stack 10 is then transferred from the alignment and bonding equipment to an atmospheric or inert gas environment, and finally bonded using a wafer bonding equipment 100. On the one hand, due to the long transfer path and complex transfer environment, the flatness and cleanliness of the adhesion layer 13 and / or atomic diffusion layer 14 formed on the bonding surface of the wafer are affected by oxidation, contamination, etc., resulting in problems such as porosity, oxidation and deactivation, and even wafer film peeling or cracking, leading to poor wafer bonding effect, which in turn affects the stability, reliability and heat dissipation performance of semiconductor products. On the other hand, since each step of the traditional bonding process is relatively independent and the path is long, although it is conducive to the division of labor in the industrial chain, it also causes problems such as long process flow and low production efficiency. Moreover, due to the multiple operations on the wafer, too many external interference factors are introduced, which not only easily causes the wafer alignment accuracy to decrease, but may also cause the wafer to be worn or damaged by external forces due to equipment accuracy and operation flexibility, affecting the stability and reliability of semiconductor products.

[0067] Therefore, by integrating the flipping device 30, the pressure device 40, and the coating device 50 into the same main body 20, and utilizing the vacuum chamber 21 formed by the main body 20 to realize the wafer coating, flipping bonding, and bonding processes, on the one hand, it is possible to quickly bond two wafers together after coating in the same vacuum / negative pressure or inert gas environment. By achieving seamless connection between thin film deposition and bonding operations, long-term storage and transfer in the atmosphere after coating are avoided, which can reduce problems such as thin film oxidation, contamination, and loss of activity, thereby improving the bonding interface quality, shortening the process flow, and improving process efficiency. On the other hand, by integrating the equipment design, the overall production line size and floor space can be reduced, lean production can be achieved, and it can be adapted to more diverse production environments.

[0068] It should be further understood that the integrated, miniaturized, and efficient equipment design makes it possible to form multi-layered, high-quality coatings on semiconductor products such as wafer stacks. This not only improves the thermal conductivity and mechanical strength of the thermal interface, but also enables the equipment to achieve good bonding effects at lower temperatures and / or pressures. This reduces process difficulty and related costs, and avoids the semiconductor material from failing due to thermal sensitivity at excessively high temperatures or the wafer from cracking under excessively high pressures. It also ensures sufficient atomic diffusion in the metal layer, thereby improving the production efficiency and process yield of semiconductor products, and enhancing the stability and reliability of semiconductor products.

[0069] Specifically, the coating apparatus 50 can be disposed on the main body 20, and at least a portion of the coating apparatus 50 can be disposed in the vacuum chamber 21. The coating apparatus 50 can be used to coat the surface of the first wafer 11 and / or the second wafer 12. The pressure device 40 can be disposed on the top wall 22. The pressure device 40 can be used to apply pressure to the wafer stack 10 after the first wafer 11 has been flipped and aligned with the second wafer 12. It should be understood that the coating apparatus 50 may include modules capable of performing coating functions, such as a magnetron sputtering module and a vacuum evaporation coating module, and is not specifically limited here.

[0070] In some embodiments, the pressure device 40 may include an air cushion indenter 41. In conventional wafer bonding equipment 100, to reduce related costs, a hard indenter is often used to bond wafers of a specific size. However, when bonding a wafer smaller than the first size of the hard indenter, the surface of the hard indenter will deform and become concave due to uneven force distribution during long-term use or mass production. This prevents the bonding of wafers larger than the first size, otherwise, uneven force distribution and other problems will occur. By using the air cushion indenter 41, a good and uniform pressing effect can be generated for wafers of different sizes, avoiding the problems of insufficient versatility, difficulty in adapting to mass production, frequent indenter replacement, and only being compatible with wafers of a specific size that are common in conventional wafer bonding equipment 100.

[0071] In some embodiments, the pressure device 40 may further include a servo motor and a pressure sensor. The servo motor can control the position of the pressure head, and the pressure sensor can measure the real-time force on the wafer during the pressure bonding process. It should be understood that by using servo motor control and configuring a pressure sensing system, the accuracy and uniformity of pressure control can be improved.

[0072] Please refer to the supplementary information. Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of the structure of a flipping device 30 provided in one embodiment of this application. Figure 10 This is a schematic diagram of another flipping device 30 provided in one embodiment of this application. Figures 8 to 10 As shown, the flipping device 30 can be disposed on the bottom wall 23. The flipping device 30 may include a first wafer carrier 31, a second wafer carrier 32, and a driving module 33. The first wafer carrier 31 and the second wafer carrier 32 can be used to carry the first wafer 11 and the second wafer 12, respectively. The driving module 33 is used to drive at least one of the first wafer carrier 31 and the second wafer carrier 32 to flip the first wafer 11 and align it with the second wafer 12 to obtain the wafer stack 10.

[0073] It should be understood that by promptly flipping and applying pressure for bonding after coating, a seamless connection between thin film deposition and bonding operations can be achieved. This avoids prolonged storage and atmospheric transfer after coating, reducing problems such as film oxidation, contamination, and loss of activity, thereby improving the purity and bonding activity of the metal layer, shortening the process flow, and increasing process efficiency. For example, the drive module 33 may include an electrically driven hinge flipping mechanism, on which a first wafer carrier 31 and a second wafer carrier 32 are mounted. Flipping via the electrically driven hinge allows the wafers to be bonded quickly, avoiding surface contamination and ensuring high alignment accuracy of the bonding positions.

[0074] In some embodiments, the wafer bonding apparatus 100 may include a vacuum adsorber, and the first wafer carrier 31 and the second wafer carrier 32 may be provided with a first adsorption port 311 and a second adsorption port 321, respectively. The vacuum adsorber is connected to the first adsorption port 311 and / or the second adsorption port 321, and the vacuum adsorber is used to fix the first wafer 11 and / or the second wafer 12 by adsorption.

[0075] It should be understood that the first adsorption port 311 can be understood as an adsorption port formed on the first wafer carrier 31, and the second adsorption port 321 can be understood as an adsorption port formed on the second wafer carrier 32. The terms "first" and "second" are not limited in quantity. For example, the first wafer carrier 31 may have a concentric array of adsorption ports formed by multiple first adsorption ports 311, and the second wafer carrier 32 may have a concentric array of adsorption ports formed by multiple second adsorption ports 321. It should be understood that the adsorption ports can be arranged in a concentric array to adapt to wafers of different sizes, making the adsorption effect on the wafer accurate and controllable. This allows for timely, convenient, and effective management and activation of the adsorption ports, ensuring proper positioning of the first wafer 11 and the second wafer 12 during flipping, bonding, and other processes, preventing slippage, improving alignment and bonding accuracy, increasing equipment energy efficiency and product yield, improving wafer bonding effects, and enhancing the stability and reliability of semiconductor products such as the wafer stack 10.

[0076] Those skilled in the art will understand that the adsorption port may include adsorption holes visible to the naked eye, or it may include tiny adsorption structures. For ease of description, the figure uses adsorption holes visible to the naked eye as an example. It may also be replaced with tiny adsorption structures to achieve the adsorption function, and no specific limitation is made here.

[0077] In some embodiments, the first wafer carrier 31 and the second wafer carrier 32 may also be equipped with heating coils. The heating coils enable efficient heating of the wafer, thereby controlling the temperature of the wafer surface during the deposition and bonding processes, and improving the effects of surface activation, deposition, and wafer bonding. Furthermore, a concentric vacuum cavity may be provided inside the wafer carrier, through which the adsorption port array can be connected to a vacuum adsorber. The heating coils may be coil-shaped to fit the concentric ring configuration of the vacuum cavity and adsorption port array on the wafer carrier, and the built-in protection of the vacuum cavity makes the wafer carrier structure more compact and efficient.

[0078] In some embodiments, the wafer bonding apparatus 100 may further include a vacuum device, a water system, a transfer device, an electrical control device, etc. The vacuum device may include a mechanical pump and a molecular pump, and a vacuum port may be provided on the main body 20, through which the vacuum device can be connected to the vacuum chamber 21. For example, to create a vacuum, negative pressure, or inert gas environment within the vacuum chamber 21, a coarse evacuation can be performed using a mechanical pump to achieve a pressure of 4-8 Pa, followed by switching to a molecular pump for fine evacuation.

[0079] In some embodiments, limiters may be provided on the first wafer carrier 31 and the second wafer carrier 32. These limiters may include positioning push rods 34, electrically controlled clamps, etc. Furthermore, the limiters may also include motors and limit switches. It should be understood that traditional wafer carriers often need to be designed according to different wafer sizes. By setting limiters, the wafer carriers can achieve good alignment and placement effects for different wafer sizes.

[0080] In some embodiments, the limiter may include positioning push rods 34, wherein a first wafer carrier 31 is provided with a set of positioning push rods 34, and a second wafer carrier 32 is provided with another set of positioning push rods 34. For example, two wafers to be bonded can be placed on the first wafer carrier 31 and the second wafer carrier 32, respectively, corresponding to the first adsorption port 311 and the second adsorption port 321, with the bonding surfaces of the two wafers facing upwards, and the cavity door closed; then, one set of positioning push rods 34 is controlled to position the two wafers, and the other set of positioning push rods 34 is operated in the same way, ensuring that the wafers in the two adsorption trays are aligned after reversal, vacuum adsorption is activated, and the positioning push rods 34 are retracted. Specifically, the wafer can be limited by advancing one push rod of one set of positioning push rods 34 to a designated position, and the other push rod can be advanced to a designated position to complete the positioning. It should be understood that the design of the positioning push rod 34 and other limiters enables the wafer carrier to be better adapted to wafers of various sizes, thereby improving the practicality and versatility of the wafer bonding equipment 100, improving the wafer bonding effect of wafers of various sizes, and compared with the traditional mechanical manipulator, the design of the positioning push rod 34 is simple, flexible and effective, without the need to introduce a large number of tolerance links, which not only reduces equipment costs, but also improves the accuracy of wafer alignment and bonding, and improves the wafer bonding effect.

[0081] Furthermore, the positioning push rod 34 can be programmable, or a force sensor or position sensor can be installed on the positioning push rod 34. Through the design of the dual wafer carrier and rotation alignment mechanism of the flipping device 30, the two wafers can be accurately aligned after flipping, improving the alignment of the bonding interface.

[0082] In some embodiments, the wafer bonding apparatus 100 may further include an activation device 60, disposed on the main body 20, with at least a portion of the activation device 60 disposed in the vacuum chamber 21, for performing surface activation treatment on the first wafer 11 and / or the second wafer 12. For example, the activation device 60 may include a Fast Atom Bombardment (FAB) module such as an atomic gun. Specifically, the activation device 60 may utilize Ar ion beams, neutral atoms, or bombardment to achieve surface activation treatment. It should be understood that the activation device 60 can be used to activate the bonding surfaces of the wafers, achieving surface activation through Ar ion beam and neutral atom bombardment, thereby resulting in better quality and stronger adhesion of subsequently deposited thin films.

[0083] In some embodiments, the wafer bonding apparatus 100 may further include vacuum devices such as mechanical pumps and molecular pumps to create a pure, vacuum, or negative pressure environment within the vacuum chamber 21. The wafer bonding apparatus 100 may also have a bias power supply on its bottom wall 23, which can guide thin film deposition or surface activation, ensuring the accuracy of operations such as magnetron sputtering and atomic bombardment. In particular, during the coating process, setting a bias voltage can make the coating more uniform, improve the bonding effect, and enhance the stability and reliability of semiconductor products such as the wafer stack 10.

[0084] In some embodiments, the wafer bonding apparatus 100 may further include a rotating device 70, at least a portion of which may be disposed on the bottom wall 23. The rotating device 70 may include a rotating motor 71 and a turntable 72. The rotating motor 71 may be used to drive the turntable 72 to rotate, and a flipping device 30 may be disposed on the turntable 72.

[0085] Specifically, the turntable 72 can be movably connected to the bottom wall 23. The rotating device 70 may include a power output shaft, and a rotating motor 71 is rotatably connected to the turntable 72 through the power output shaft. The rotating motor 71 can drive the turntable 72 inside the vacuum chamber 21 to rotate through the power output shaft. It should be understood that the design of the rotating device 70 makes it possible for the wafer on the flipping device 30 to rotate during activation or coating, which is beneficial for the wafer to react uniformly during activation and coating, helps to form a dense, gapless thermal interface, improves thermal conductivity and heat dissipation efficiency, and improves the stability and reliability of semiconductor products such as the wafer stack 10.

[0086] Please refer to the supplementary information. Figure 11 and Figure 12 , Figure 11 This is a schematic diagram of the structure of a coating apparatus 50 provided in one embodiment of this application. Figure 12 This is a schematic diagram of the structure of a coating apparatus 50 provided in one embodiment of this application. Figure 8 , Figure 11 and Figure 12 As shown, the coating apparatus 50 may include a magnetron sputtering module or a vacuum evaporation coating module. For example, the coating apparatus 50 may include a target gun 51. It should be understood that the target gun 51 can be used to coat the surface of the first wafer 11 and / or the second wafer 12 by a magnetron sputtering process.

[0087] Specifically, the target gun 51 may include a cathode target, a cylindrical target, etc. The coating device 50 may also include an RF power supply and / or a DC power supply, which can be connected to the target gun 51.

[0088] Furthermore, the coating apparatus 50 may include multiple target guns 51. It should be understood that by using multiple target guns 51, problems such as difficulty in accurately controlling the sputtering range and uneven coating during magnetron sputtering with a single target gun 51 can be avoided. It should also be understood that by using multiple target guns 51, it is possible to deposit multi-material, multi-layered thin films on the wafer surface, eliminating the need to replace the target material 52 during use.

[0089] Multiple target guns 51 are evenly distributed and arranged on the same annular indexing circumference 511 of the top wall 22, with equal angles between the central axes of adjacent target guns 51 and the central axis of the annular indexing circumference 511. By evenly distributing multiple target guns 51 on the same annular indexing circumference 511 of the top wall 22, the uniformity of the coating process is further improved, and multilayer sputtering and confocal sputtering become possible, thus enhancing the operability of the coating process.

[0090] In some embodiments, a first baffle 81 may be provided on the flipping device 30 or the bottom wall 23, and at least a portion of the first baffle 81 may be positioned corresponding to the target 52. Further, the coating apparatus 50 may include the target 52 and a second baffle 82, and at least a portion of the second baffle 82 may be positioned corresponding to the target 52. The baffle arrangement makes it possible to remove relevant impurities from the target 52 through pre-sputtering, improving the purity, thermal conductivity, and bonding effect of the coating. Especially during pre-sputtering of the target 52, it can cover the wafer or target 52 to prevent contamination of the wafer or vacuum chamber 21, facilitating the long-term reliability and stability of the wafer bonding equipment 100 and ensuring the wafer bonding effect.

[0091] It should be understood that the control of the baffles can be independent, thereby improving the operability of the coating process. For example, depending on the bonding process requirements, different target guns 51 and their target materials 52 can be used in a single operation to deposit transition layers or multi-layered films of different materials and structures on two wafers. This also prevents contamination between target materials 52 when multiple target guns 51 are simultaneously magnetron sputtered. Alternatively, two baffles can be opened simultaneously to deposit the same metal adhesion layer 13 on two wafers at the same time. Another example is that the baffles can be used to shield the first wafer 11, deposit the first adhesion layer 131 metal on the second wafer 12, then shield the second wafer 12 with the adhesion layer 13 already deposited, open the baffle above the first wafer 11, and deposit the second adhesion layer 132 metal on the first wafer 11. For example, two wafers can be plated with the same metal bonding layer, or a baffle can be used to shield the first wafer 11, while a first type of bonding layer metal is plated on the second wafer 12. Then, the second wafer 12 with the bonded layer is shielded again, and the baffle above the first wafer 11 is opened to plate a second type of bonding layer metal on the first wafer 11. Those skilled in the art will understand that, through the design of the baffle, it is also possible to plate multiple layers of the same or different metals onto the two wafers separately, depending on process requirements.

[0092] This application also proposes a semiconductor processing system, which may include wafer bonding equipment as described in any embodiment of this application.

[0093] This application also proposes a wafer bonding method applied to a wafer bonding apparatus 100, which has a vacuum chamber 21. Please refer to... Figure 13 , Figure 13 This is a schematic flowchart illustrating the steps of a wafer bonding method provided in an embodiment of this application. Figure 13 As shown, the wafer bonding method may include steps S101 to S104. It should be understood that the wafer bonding method may be at least part of the entire fabrication process of semiconductor products such as wafer stacks.

[0094] S101, Provide the first wafer and the second wafer.

[0095] Specifically, the material of the first wafer 11 may include diamond, and the material of the second wafer 12 may include sapphire, Si, SiO2, Ge, GaN, AlN, SiC, lithium niobate, lithium tantalate, or III-V compound semiconductors. Bonding the semiconductor wafers with diamond, which has high thermal conductivity, can effectively improve the heat dissipation performance of semiconductor products such as the wafer stack 10, reduce the operating junction temperature and thermal management difficulty of semiconductor products, and improve the stability, reliability, and lifespan of semiconductor products.

[0096] In some embodiments, the first wafer 11 and the second wafer 12 may also be polished and / or ultrasonically cleaned to improve the cleanliness of the wafer surface, prevent impurity contamination, improve the adhesion between the wafer substrate and the coating, improve the wafer bonding effect and the quality of thermal interface formation, and improve the stability, reliability and heat dissipation performance of semiconductor products such as the wafer stack 10.

[0097] S102. The first wafer and the second wafer are placed in a vacuum chamber, and a film is deposited on the bonding surface of the first wafer and the bonding surface of the second wafer.

[0098] It should be understood that the vacuum chamber 21 is the vacuum chamber 21 formed by the aforementioned wafer bonding equipment 100.

[0099] In some embodiments, the film thickness and diffusion time can be controlled according to process parameters or product specifications to form a dense, non-porous thermal interface. For example, the film thickness can be controlled between 10-100 nm. This effectively transfers the heat generated by power semiconductor materials such as gallium nitride and gallium oxide to diamond, improving heat dissipation efficiency.

[0100] In some embodiments, the bottom wall 23 of the vacuum chamber 21 may be provided with a wafer carrier, which has an adsorption port and a limiter. The wafer bonding apparatus 100 also includes a vacuum adsorber connected to the adsorption port. Please refer to [link to documentation]. Figure 14 , Figure 14 This is a schematic flowchart illustrating the steps of a wafer setup method provided in an embodiment of this application. Figure 14 As shown, the wafer setting method may specifically include steps S102a to S102d, which are used to implement the above-mentioned steps of setting the first wafer 11 and the second wafer 12 in the vacuum chamber 21.

[0101] S102a, Place the first wafer or the second wafer on the wafer carrier.

[0102] It should be understood that, for the sake of convenience, this wafer setup method is described using the setup process of one wafer as an example, and the other wafer can be referenced and executed accordingly, without making specific limitations on the order of operations or the objects of operations.

[0103] For example, if the wafer carrier includes a first wafer carrier 31 and a second wafer carrier 32, the first wafer 11 can be placed on the first wafer carrier 31 and the second wafer 12 can be placed on the second wafer carrier 32. Alternatively, the first wafer 11 can be placed separately first, and the second wafer 12 can be placed after the wafer setup method has been completed.

[0104] S102b, Enable limiter, positions the first wafer or the second wafer to the adsorption port.

[0105] It should be understood that the wafer carrier is equipped with an adsorption port and a limiter. The limiter may include a positioning push rod 34, a controllable clamp, etc., which can position the wafer placed on the wafer carrier to the adsorption port.

[0106] In some embodiments, the limiter may include a positioning push rod 34, and the wafer carrier may include a plurality of adsorption ports to form an adsorption port array. The positioning push rod 34 is disposed on the periphery of the adsorption port array to limit and position the wafer placed on the wafer carrier, so that the wafer is aligned with at least a portion of the adsorption ports of the adsorption port array for adsorption.

[0107] S102c. The first or second wafer is fixed to the adsorption port by a vacuum adsorber.

[0108] It should be understood that since the wafer bonding equipment 100 also includes a vacuum adsorber connected to the adsorption port, the first wafer 11 or the second wafer 12 can be fixed to the adsorption port through the vacuum adsorber.

[0109] For example, the adsorption ports can be formed into an array of adsorption ports arranged in concentric rings. The vacuum adsorber can achieve adsorption and fixation of wafers of different sizes by controlling the adsorption function of each ring of the concentric ring array.

[0110] S102d, retraction limiter.

[0111] It should be understood that a retraction limiter can also be understood as removing or retracting a limiter, as long as it can achieve the effect of releasing the limit / positioning of the wafer. The specific manner in which the limiter is released is not restricted here.

[0112] It should be understood that this wafer setup method allows for the early intervention of operations that facilitate alignment and correction during the wafer placement process. Furthermore, the design of limiters such as the positioning push rod 34 simplifies the control method, avoiding the error chain, external disturbances, and impacts introduced by the robotic arms and other operations of traditional alignment and bonding equipment. This improves the accuracy and efficiency of alignment, bonding, and wafer bonding, reduces the process difficulty and implementation cost of wafer bonding, and enhances the production efficiency of semiconductor products such as the wafer stack 10.

[0113] In some embodiments, after the first wafer 11 and the second wafer 12 are placed in the vacuum chamber 21, surface activation treatment can be performed on the first wafer 11 and / or the second wafer 12. For example, the wafer bonding apparatus 100 may also include an activation device 60, which can first use a vacuum device such as a mechanical pump or a molecular pump to evacuate the vacuum chamber 21; after the vacuum level reaches a preset condition, an inert gas is introduced into the vacuum chamber 21 and the gas pressure is stabilized within a preset range; enabling the activation device 60 to perform surface activation treatment on the wafers. Specifically, the inert gas may include argon, helium, etc. It should be understood that for diamond, sp 3 Hybrid carbon-carbon single bonds are extremely stable. Metallization, such as coating, on untreated diamond surfaces is prone to delamination. Surface activation treatment can introduce active states into the diamond surface, enhancing the bonding force, and is also applicable to other semiconductor materials.

[0114] In some embodiments, after the wafer is attached to the wafer carrier, the vacuum chamber 21 can be evacuated to 10°C. - 5 Pa-10 -4 Pa, Ar is introduced to maintain the working pressure at 1×10⁻⁶. -3 Pa–5×10 -3 Pa. With an incident angle of 45° and a power of 1.5kV×15mA, the Ar FAB and other activation devices were used to clean and activate the sample surface for 300s.

[0115] In some embodiments, the wafer bonding apparatus 100 may include a plurality of target guns 51. Prior to the aforementioned step of coating the bonding surface 111 of the first wafer 11 and the bonding surface 121 of the second wafer 12, pre-sputtering can be used to reduce impurities and oxide layers on the surface of the target material 52, ensuring stable and reliable coating quality. See also... Figure 15 , Figure 15 This is a schematic flowchart illustrating the steps of a wafer deposition method provided in one embodiment of this application. Figure 15 As shown, the wafer deposition method includes steps S102e to S102f.

[0116] S102e, pre-splashing using at least a portion of multiple target guns.

[0117] It should be understood that pre-sputtering can sputter impurities and oxide layers from the surface of the target 52 to areas outside the wafer surface. For example, a baffle can be provided in the sputtering direction of the target gun 51 or above the wafer. During pre-sputtering, impurities can be sputtered onto the baffle to prevent contamination of the wafer surface and the coating.

[0118] S102f: A coating is deposited on the bonding surface of the first wafer and the bonding surface of the second wafer using multiple target guns.

[0119] The bonding surface can be understood as the side of the wafer furthest from the wafer carrier, or as the topmost side of the wafer when it is placed on the wafer carrier. It should be understood that the presence of multiple target guns 51 makes it more convenient and controllable to form metal layers of various materials on the wafer. Furthermore, since each target gun 51 can be configured with different poses, target materials 52, and sputtering fluxes, complex operations such as multilayer sputtering and confocal sputtering can be achieved, improving the uniformity and controllability of the coating and enhancing the wafer bonding effect.

[0120] In some embodiments, a first adhesion layer 131 can be formed on the bonding surface 121 of the first wafer 11 and the second wafer 12 by deposition, and a first atomic diffusion layer 141 can be formed on the first adhesion layer 131 of the first wafer 11 and the second wafer 12. The presence of the first adhesion layer 131 and the first atomic diffusion layer 141 effectively reduces the temperature and pressure conditions during the wafer bonding process, prevents wafer deactivation at high temperatures and cracking under high pressure, and ensures sufficient atomic diffusion, thereby improving the yield and production efficiency of the wafer bonding process.

[0121] In some embodiments, the wafer bonding effect can be improved by using metallic materials to form the adhesion layer 13, the atomic diffusion layer 14, the bonding layer, etc. For example, the material of the first adhesion layer 131 may include Ti, Ni, Cr, Ta, Mo, or W. Similarly, the material of the first atomic diffusion layer 141 may include Au, Ag, Cu, or Al. It should be understood that transforming the direct bonding of heterogeneous wafers into bonding at the interface of two metal layers prevents the reduction of the mechanical structural strength of semiconductor products such as the wafer stack 10 due to the difference in thermal expansion coefficients between the first wafer 11 and the second wafer 12 at higher or lower operating junction temperatures, and also prevents internal structural strain failure.

[0122] In some embodiments, after forming a first atomic diffusion layer 141 on the first adhesion layer 131 of the first wafer 11 and the second wafer 12, a second adhesion layer 132 may be formed on the first atomic diffusion layer 141 of the first wafer 11 or the second wafer 12, and a second atomic diffusion layer 142 may be formed on the second adhesion layer 132. The material of the second adhesion layer 132 includes Ti, Cu, Al, Ni, Cr, Ta, Mo or W, and the material of the second atomic diffusion layer 142 includes Au, Ag, Cu or Al.

[0123] In some embodiments, after the surface activation treatment is completed, the first baffle 81 can be closed and the second baffle 82 can be opened. The Ar flow rate can be adjusted to keep the gas pressure stable at about 1 Pa. Pre-sputtering is performed for 5-10 minutes. Then, the second baffle 82 can be closed and both first baffles 81 can be opened at the same time. Rotation can be started and Ti metal adhesion layers 13 can be deposited on the two wafers at the same time. The power is set to 200W and the time is 2 minutes. The thickness of the Ti layer is about 10 nm. At the same time, Cu metal bonding layers can be deposited on the two wafers at the same time. The power is set to 150W and the time is 10 minutes. The thickness of the Cu layer can be 100 nm, thus realizing Ti-Cu-Ti bonding.

[0124] In some embodiments, after the surface activation treatment is completed, the first baffle 81 can be closed, the second baffle 82 can be opened, the Ar flow rate can be adjusted to keep the gas pressure stable at about 1 Pa, pre-sputtering can be performed for 5-10 minutes, the second baffle 82 can be closed, and the two first baffles 81 can be opened at the same time. The rotation can be started, and a 10 nm Ti metal adhesion layer 13 can be deposited on the two wafers. The gallium oxide wafer is shielded by the baffle, a 100 nm Cu metal bonding layer is deposited on the diamond wafer, and the diamond wafer is shielded again. The first baffle 81 above the second wafer 12 is opened, and a 100 nm Ag metal bonding layer is deposited on the gallium oxide wafer to achieve Ti-Cu-Ag-Ti bonding.

[0125] In some embodiments, metal adhesion layers 13 can be deposited on two wafers separately. For example, a second wafer 12 made of gallium oxide can be shielded by a first baffle 81, a 10nm Mo metal adhesion layer 13 can be deposited on a first wafer 11 made of diamond, the first wafer 11 can be shielded by a first baffle 81 above the first wafer 11, the first baffle 81 above the second wafer 12 can be opened, a 10nm Ti metal adhesion layer 13 can be deposited on the bonding surface 121 of the second wafer 12, and then both first baffles 81 can be opened to simultaneously deposit a 100nm Cu metal bonding layer on the diamond wafer and the gallium oxide wafer to achieve Ti-Cu-Mo bonding.

[0126] In some embodiments, metal adhesion layers 13 can be deposited on two wafers separately. For example, a gallium oxide wafer can be shielded by a first baffle 81, a 10 nm Mo metal adhesion layer 13 can be deposited on a diamond wafer, the diamond wafer can be shielded again, the baffle above the gallium oxide wafer can be opened, a 10 nm Ti metal adhesion layer 13 can be deposited, the gallium oxide wafer can be shielded by a baffle, a 100 nm Cu metal bonding layer can be deposited on the diamond wafer, the diamond wafer can be shielded again, the baffle above the gallium oxide wafer can be opened, and a 100 nm Ag metal bonding layer can be deposited on the gallium oxide wafer to achieve Cu-Ag bonding.

[0127] In some embodiments, a multilayer metal bonding layer structure can be formed. For example, a first adhesion layer 131 made of Ti can be deposited on the bonding surface 121 of the first wafer 11 and the second wafer 12, a first atomic diffusion layer 141 made of Cu can be deposited on the bonding surface 111 of the first wafer 11, and finally a bonding layer made of Au can be deposited on the bonding surface 121 of the first wafer 11 and the second wafer 12.

[0128] S103. In the vacuum chamber, flip the second wafer so that its bonding face is aligned with the bonding face of the first wafer to obtain a wafer stack.

[0129] It should be understood that by flipping the second wafer 12 in the same vacuum chamber 21 so that its bonding face is aligned with the bonding face 111 of the first wafer 11, the wafer transfer path can be shortened, atmospheric oxidation and impurity contamination can be reduced, equipment space and process costs can be saved, wafer bonding effect can be improved, and semiconductor products such as the diamond substrate wafer stack 10 can be formed.

[0130] S104. In a vacuum chamber, perform thermal bonding and / or pressure bonding on the wafer stack.

[0131] It should be understood that since the layer structure and material of the coating may be adjusted due to process or product requirements, the parameter selection, execution order, and process method of thermal bonding and pressure bonding can be adjusted according to actual needs. Simultaneous thermal bonding and pressure bonding processes can be performed to achieve wafer bonding, or thermal bonding or pressure bonding can be used alone, or thermal bonding can be used first followed by pressure bonding. No specific limitations are made here.

[0132] In some embodiments, the first wafer carrier 31 and the second wafer carrier 32 are provided with heating coils, which can be used to bring the first wafer 11, the second wafer 12 and / or the wafer stack 10 to a preset temperature. During the thermal bonding process of the wafer stack 10, the bonding temperature can be from room temperature to 450°C. Furthermore, the wafer carriers may also be provided with temperature sensors, which can be used to heat the first wafer 11, the second wafer 12 and / or the wafer stack 10 at a preset heating rate via the heating coils and the temperature sensor.

[0133] Typical, but not limiting, the bonding temperature can be 0°C, 20°C, 40°C, 60°C, 80°C, 100°C, 120°C, 140°C, 160°C, 180°C, 200°C, 220°C, 240°C, 260°C, 280°C, 300°C, 320°C, 340°C, 360°C, 380°C, 400°C, 420°C, 440°C, 450°C, or a range of any two of these values.

[0134] In some embodiments, Ti-Cu-Ti bonding can be used, that is, the material of the adhesion layer 13 is Ti and the material of the atomic diffusion layer 14 is Cu. The temperature is set to 200°C, the pressure applied by the pressure device 40 is set to 0.2 MPa, and the bonding is carried out under temperature and pressure for a certain period of time. For example, the bonding can be carried out under temperature and pressure for 20-40 minutes.

[0135] In some embodiments, after thermal bonding and / or pressure bonding of the wafer stack 10, the wafer stack 10 may be annealed and depressurized and cooled. For example, the wafer stack 10 may be depressurized first and then annealed, or the wafer stack 10 may be annealed first and then depressurized. This promotes metal recrystallization, improves the thermal conductivity of the bonding interface, and enhances the heat dissipation performance of the semiconductor product.

[0136] In some embodiments, the wafer bonding equipment 100 may also be equipped with a nitrogen charging valve and a vacuum pump. After the bonding process of heat preservation and pressure preservation, the wafer can be annealed and cooled to a safe temperature, which may be 40°C-60°C, for example, 50°C. Then the pressure is released and the pressure device 40 is removed. The charging valves for inert gases such as nitrogen and argon are opened to purge the wafer surface for cooling. At the same time, the vacuum pump is turned on to remove the heat.

[0137] In some embodiments, when the wafer stack 10 is cooled to a preset temperature, such as room temperature or 0-40°C, the wafer stack 10 can be fixed by a limiter and the vacuum adsorption can be turned off. Then, the wafer carrier placed on top can be flipped back to its original position by the drive module 33.

[0138] In some embodiments, after the air pressure in the vacuum chamber 21 reaches atmospheric pressure, the door of the vacuum chamber 21 can be opened and the vacuum suction device can be turned off to remove semiconductor products such as the wafer stack 10.

[0139] In some embodiments, the second baffle 82 can be used to shield the coating device 50, such as the target gun 51, before opening the first baffle 81 to prevent it from obstructing wafer placement. The first wafer 11 and the second wafer 12 are placed on the first wafer carrier 31 and the second wafer carrier 32, respectively. The door of the vacuum chamber 21 is closed, and the wafer carrier is automatically positioned and vacuum-adsorbed and fixed using the limiters on the wafer carrier. The limiters are then retracted. The vacuum chamber 21 is evacuated to 1×10⁻⁶. -5Pa, activation device 60 is activated to clean and activate the surfaces of the first wafer 11 and the second wafer 12; argon gas is introduced into vacuum chamber 21 and a fixed argon gas flow rate is set to stabilize the gas pressure at about 1 Pa; an adhesion layer 13, such as a titanium (Ti) metal layer, is deposited on the surfaces of the first wafer 11 and the second wafer 12, with a thickness controlled at about 50 nm. During the coating process, the temperature of the wafer can be increased to 200°C at a preset rate using a heating coil, and rotation and bias are achieved during the coating process using a rotation device 70, bias voltage, etc.; after the coating process is completed, the control drive module 33 flips the second wafer carrier 32, so that the bonding surface 121 of the second wafer 12 is attached to the bonding surface 111 of the first wafer 11, realizing wafer pre-bonding, and obtaining wafer stack 10; the pressure head of the pressure device 40 set on the top wall 22 is lowered to apply pressure to the wafer stack 10, and the pressure is applied by the pressure device 40 set on the wafer carrier. Heating coils heat the wafer stack 10 at a preset rate. Temperature and pressure are maintained according to preset parameters to form a stable metal transition layer, which may include all metal layers between the first wafer 11 and the second wafer 12. Annealing is performed according to specific process parameters to allow the metal transition layer to fully recrystallize, ensuring good thermal conductivity at the bonding interface. At the end of bonding, the temperature is lowered, then pressure is released until the pressure head is removed. After cooling to a safe temperature, the nitrogen filling valve is opened to purge and cool the wafer stack 10, and a vacuum pump is activated to remove heat. The nitrogen filling valve is closed, the wafer stack 10 is re-secured using a limiter, the venting valve is opened, and the second wafer carrier 32 is flipped back to its original position. Once the pressure in the vacuum chamber 21 reaches atmospheric pressure, the door of the vacuum chamber 21 is opened, the vacuum adsorber is closed, and the sample is removed.

[0140] This application provides a semiconductor product that can be prepared by the wafer bonding equipment 100 or wafer bonding method as described in any embodiment of this application.

[0141] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the devices and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0142] It should be understood that the wafer bonding method or wafer bonding equipment provided in the embodiments of this application can produce the following technical effects: First, it reduces the process temperature of wafer bonding. For example, the process temperature of traditional wafer bonding needs to be greater than 800℃ (such as Si / SiC), while some embodiments of this application can achieve low-temperature bonding of 200-400℃ through the design of atomic diffusion layers (such as Ti / Au, Al / Ni), and reduce the thermal budget, avoiding material degradation caused by high temperature (such as GaN decomposition, sapphire lattice distortion); Second, it reduces the process pressure requirements of wafer bonding. The process pressure of traditional hot-press bonding needs to be greater than 20MPa, while some embodiments of this application only require 0-0.5MPa pressure (traditional hot-press bonding requires 20MPa+), reducing the risk of brittle material fracture; Third, the semiconductor products obtained by some embodiments of this application have low interface thermal resistance and strong mechanical reliability.

[0143] The embodiments of this application also provide a computer-readable storage medium storing a computer program, the computer program including program instructions, and the processor executing the program instructions to implement any of the wafer bonding methods provided in the embodiments of this application.

[0144] The computer-readable storage medium can be an internal storage unit of the terminal device described in the foregoing embodiments, such as the hard disk or memory of the terminal device. Alternatively, the computer-readable storage medium can be an external storage device of the terminal device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., provided on the terminal device.

[0145] Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples.

[0146] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer bonding apparatus, characterized in that, include: A main body, the main body forming a vacuum chamber, the main body including a top wall and a bottom wall; A flipping device is disposed on the bottom wall. The flipping device includes a first wafer carrier, a second wafer carrier, and a driving module. The first wafer carrier and the second wafer carrier can be used to carry a first wafer and a second wafer, respectively. The driving module is used to drive at least one of the first wafer carrier and the second wafer carrier to flip the first wafer and align it to fit against the second wafer to obtain a wafer stack. A pressure device is disposed on the top wall, and the pressure device is used to apply pressure to the wafer stack after the first wafer is flipped and aligned and attached to the second wafer; A coating apparatus is disposed on the main body, at least a portion of which is disposed in the vacuum chamber, the coating apparatus being used to coat the surface of the first wafer and / or the second wafer.

2. The wafer bonding equipment as described in claim 1, characterized in that, Also includes: An activation device is disposed in the main body, and at least a portion of the activation device is disposed in the vacuum chamber, for performing surface activation treatment on the first wafer and / or the second wafer.

3. The wafer bonding equipment as described in claim 1, characterized in that, Also includes: A rotating device is disposed on the bottom wall. The rotating device includes a rotating motor and a turntable. The rotating motor is used to drive the turntable to rotate. The flipping device is disposed on the turntable.

4. The wafer bonding equipment as described in claim 1, characterized in that, The coating apparatus includes a target gun, which is used to coat the surface of the first wafer and / or the second wafer by a magnetron sputtering process.

5. The wafer bonding equipment as described in claim 4, characterized in that, The coating device includes multiple target guns, which are evenly distributed and arranged on the same annular indexing circumference of the top wall. The angle between the central axis of adjacent target guns and the central axis of the annular indexing circumference is equal.

6. The wafer bonding equipment as described in claim 1, characterized in that, The flipping device or the bottom wall is provided with a first baffle, at least a portion of which can be configured to correspond to the target material; and / or, The coating apparatus includes a target and a second baffle, at least a portion of which can be configured to correspond to the target.

7. The wafer bonding equipment as described in claim 1, characterized in that, The first wafer carrier and the second wafer carrier are respectively provided with a first adsorption port and a second adsorption port, and the wafer bonding equipment further includes: A vacuum adsorber, the vacuum adsorber being connected to the first adsorption port and / or the second adsorption port, the vacuum adsorber being used to fix the first wafer and / or the second wafer by adsorption.

8. The wafer bonding equipment as described in claim 1, characterized in that, The first wafer carrier and / or the second wafer carrier are provided with heating coils; and / or, The pressure device includes an air cushion indenter.

9. The wafer bonding equipment as described in claim 1, characterized in that, The first wafer carrier and / or the second wafer carrier are provided with limiters.

10. A semiconductor processing system, characterized in that, The semiconductor processing system includes the wafer bonding equipment as described in any one of claims 1-9.

Images