Silicon wafer epitaxial pedestal
By setting rounded corners in the wafer placement slots of the silicon wafer epitaxial substrate, the quality problem of epitaxial silicon wafers caused by wedge gaps was solved, achieving higher production quality and electrical performance uniformity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- MCL ELECTRONICS MATERIALS
- Filing Date
- 2025-05-30
- Publication Date
- 2026-07-21
AI Technical Summary
The wedge-shaped gap of the existing silicon wafer epitaxial substrate leads to poor production quality of epitaxial silicon wafers, high defect rate, and deposition of reactive gases and dopants at the edge of the silicon wafer, affecting the uniformity of electrical performance.
The wafer placement groove of the silicon wafer epitaxial substrate is rounded, with rounded corners between the groove wall and the bottom of the groove. This supports the bottom of the chamfered outer edge of the silicon wafer and reduces the deposition of reactive gases and the escape of dopants.
It improves the production quality of epitaxial silicon wafers, reduces the defect rate, reduces the electrical performance differences of epitaxial layers, and enhances physical shape and electrical performance.
Smart Images
Figure CN224531119U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of silicon wafer epitaxial process technology, specifically a silicon wafer epitaxial substrate. Background Technology
[0002] The epitaxial silicon wafer substrate is a critical component used to support and fix the epitaxial silicon wafer during semiconductor manufacturing, playing a vital role in chemical vapor deposition (CVD) equipment. Conventional silicon wafer epitaxial substrates include... Figure 4 As shown, the device has a base body 1 and multiple placement slots 2 disposed on the base body 1 for placing silicon wafers 4 to be epitaxially processed. The bottom wall and bottom of the placement slot 2 are usually at right angles. Due to processing accuracy limitations and for ease of placing and removing silicon wafers, the inner diameter of the placement slot 2 is often slightly larger than that of the silicon wafer 4 to be epitaxially processed. After the silicon wafer 4 to be epitaxially processed is placed, not only is there a fine annular gap between the outer periphery of the silicon wafer 4 to be epitaxially processed and the inner wall of the placement slot 2, but also a larger wedge-shaped gap 5 is generated between the lower part of the chamfered edge of the silicon wafer 4 to be epitaxially processed and the bottom wall and side wall of the placement slot 2.
[0003] The presence of the wedge-shaped gap 5 results in a high defect rate due to the inability to guarantee the production quality of the epitaxial silicon wafer. This is because: on the one hand, during the epitaxial growth of the upper surface of the silicon wafer 4 to be epitaxially processed, a large amount of reactive gas exists in the wedge-shaped gap 5 through the annular micro-gap, and is deposited at the lower part of the chamfer edge of the silicon wafer 4 to be epitaxially processed, or even at the bottom of the silicon wafer 4 to be epitaxially processed, forming residue; on the other hand, because the silicon wafer 4 to be epitaxially processed itself contains dopants, during the epitaxial process, the dopants at the lower part of the chamfer edge of the silicon wafer 4 to be epitaxially processed are easily released and exist in large quantities in the wedge-shaped gap 5, and then enter near the upper part of the chamfer edge of the silicon wafer 4 to be epitaxially processed through the annular micro-gap, thus causing a large difference in the electrical properties of the circumferential edge of the epitaxial silicon wafer after epitaxial processing compared with the middle part of the outer tube silicon wafer. Utility Model Content
[0004] The present invention aims to provide a silicon wafer epitaxial substrate, which helps to ensure the production quality of epitaxial silicon wafers and reduce the defect rate.
[0005] To solve the above technical problems, the specific solution adopted by this utility model is as follows: a silicon wafer epitaxial substrate, including a substrate body, on which a plurality of wafer placement grooves are provided at intervals, and the groove walls and bottoms of the wafer placement grooves have rounded corners.
[0006] Preferably, the rounded corner radius corresponds to the edge chamfer radius of the silicon wafer to be epitaxially processed.
[0007] Preferably, the wafer placement slots are for placing 8-inch silicon wafers. Five wafer placement slots are provided on the base body, and the five wafer placement slots are arranged in a ring array and evenly spaced on the base body.
[0008] Preferably, the wafer placement slots are for placing 6-inch silicon wafers, and there are 8 wafer placement slots on the base body. The 8 wafer placement slots are arranged in a ring array on the base body and are evenly spaced.
[0009] Preferably, the substrate of the base body is graphite.
[0010] Preferably, the substrate of the base body has a silicon carbide coating on its exterior.
[0011] Preferably, the wafer placement groove is a circular stepped groove with a large-diameter groove at the top and a small-diameter groove at the bottom. The small-diameter groove is for placing the silicon wafer to be epitaxially processed, and the large-diameter groove is used to make way for the loading and unloading fixtures for the silicon wafer to be epitaxially processed.
[0012] Preferably, the depth of the plate placement groove is 0.8±0.03mm, and the depth of the large-diameter groove is 0.4±0.03mm.
[0013] In this invention, rounded corners are provided in the conventional wafer placement slot, thereby supporting the bottom of the chamfered outer edge of the silicon wafer to be epitaxially processed during the epitaxial process. This reduces the amount of epitaxial reaction gas entering the bottom of the chamfered outer edge of the silicon wafer and forming residue. Furthermore, it minimizes the escape of dopants from the bottom of the chamfered outer edge of the silicon wafer through the annular gaps to the top outer edge of the silicon wafer, thus reducing the amount of dopants entering the epitaxial layer at the top outer edge of the wafer. This also reduces the electrical performance difference between the outer edge and the center of the top epitaxial layer of the entire silicon wafer, resulting in a significant improvement in both the physical shape and electrical performance of the epitaxial silicon wafer. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the structure of this utility model;
[0015] Figure 2 This is a cross-sectional view of one of the slot locations in this utility model.
[0016] Figure 3 for Figure 2 A schematic diagram showing the state of the silicon wafer to be epitaxially processed after it has been placed in the wafer placement slot.
[0017] Figure 4 This is a schematic diagram showing the state of a silicon wafer to be epitaxially processed after it has been placed in a conventional wafer placement slot.
[0018] The markings in the diagram are: 1. Base body, 2. Wafer placement groove, 3. Rounded corners, 4. Silicon wafer to be epitaxially processed, 5. Wedge-shaped gap. Detailed Implementation
[0019] like Figure 1As shown, this utility model discloses a silicon wafer epitaxial substrate, which, like conventional epitaxial substrates in the prior art, includes a substrate body 1 and multiple wafer placement slots 2 spaced apart on the substrate body 1. The substrate body 1 is made of high-purity graphite, and the surface of the high-purity graphite is coated with high-purity silicon carbide (SiC) by chemical vapor deposition (CVD). Each wafer placement slot 2 is a stepped slot, with a small-diameter slot at the bottom for direct placement of the silicon wafer 4 to be epitaxially processed, and its inner diameter being slightly larger than the outer diameter of the silicon wafer 4 to be epitaxially processed; the large-diameter slot at the top is used to accommodate the tooling for picking up and placing the silicon wafer 4 to be epitaxially processed.
[0020] In this embodiment, the wafer placement slot 2 accommodates 8 silicon wafers, and there are 5 wafer placement slots 2 in total. The depth of the wafer placement slot 2 is 0.8±0.03mm, the depth of the large-diameter slot is 0.4±0.03mm, the inner diameter of the small-diameter slot is 202±1mm, and the inner diameter of the large-diameter slot is 205±1mm. In other embodiments of this utility model, the number of wafer placement slots 2 can be set to 8 to accommodate 6-inch silicon wafers, and the inner diameter and depth of the wafer placement slots 2 can be modified accordingly.
[0021] Unlike conventional epitaxial bases, such as Figure 2 As shown in this invention, rounded corners 3 are provided on the walls and bottom of the small-diameter groove of the wafer placement groove 2, and the radius of the rounded corners 3 corresponds to the radius of the chamfer on the outer edge of the silicon wafer 4 to be epitaxially processed, thereby enabling... Figure 3 As shown, after the silicon wafer 4 to be epitaxially processed is placed into the small-diameter groove, the bottom of the chamfered edge of the silicon wafer 4 to be epitaxially processed is supported by the rounded corner 3. This reduces the entry of epitaxial reaction gas into the bottom of the chamfered edge of the silicon wafer 4 to be epitaxially processed, and also reduces the excessive escape of dopants from the bottom of the chamfered edge of the silicon wafer 4 to be epitaxially processed. This reduces the residue at the bottom of the chamfered edge of the epitaxial silicon wafer product and reduces the difference in electrical performance between the outer periphery and the middle of the epitaxial layer at the top of the epitaxial silicon wafer product.
[0022] It should be noted that, for ease of illustration, the thickness of the silicon wafer 4 to be epitaxially processed and the radius of its outer chamfer are disproportionately enlarged in the accompanying drawings. In practical applications, it is only necessary to set the radius of the fillet 3 in the wafer slot 2 to the actual chamfer radius of the silicon wafer 4 to be epitaxially processed.
Claims
1. A silicon wafer epitaxial substrate, comprising a substrate body (1), wherein a plurality of wafer placement slots (2) are spaced apart on the substrate body (1), characterized in that: The wafer placement groove (2) has a rounded corner (3) between the groove wall and the bottom of the groove; the radius of the rounded corner (3) corresponds to the edge chamfer radius of the silicon wafer (4) to be epitaxially processed.
2. The silicon wafer epitaxial substrate as described in claim 1, characterized in that: The wafer placement slot (2) is for placing 8-inch silicon wafers. Five wafer placement slots (2) are provided on the base body (1). The five wafer placement slots (2) are arranged in a ring array on the base body (1) and are evenly spaced.
3. The silicon wafer epitaxial substrate as described in claim 1, characterized in that: The wafer placement slot (2) is for placing 6-inch silicon wafers. There are 8 wafer placement slots (2) on the base body (1). The 8 wafer placement slots (2) are arranged in a ring array on the base body (1) and are evenly spaced.
4. A silicon wafer epitaxial substrate as described in claim 1, characterized in that: The base material of the base body (1) is graphite.
5. A silicon wafer epitaxial substrate as described in claim 4, characterized in that: The substrate of the base body (1) has a silicon carbide coating on its exterior.
6. A silicon wafer epitaxial substrate as described in claim 1, characterized in that: The wafer placement groove (2) is a circular stepped groove with a large diameter groove at the top and a small diameter groove at the bottom. The small diameter groove is for placing the silicon wafer (4) to be epitaxially processed, and the large diameter groove is used to make way for the loading and unloading fixtures of the silicon wafer (4) to be epitaxially processed.
7. A silicon wafer epitaxial substrate as described in claim 6, characterized in that: The depth of the plate placement groove (2) is 0.8±0.03mm, and the depth of the large diameter groove is 0.4±0.03mm.