A circuit for a multi-channel debit bus
By combining a 3/8 decoder and a bus driver, multi-channel inputs are converted into a bus form, solving the problem of insufficient FPGA pin resources and enabling efficient use of FPGA pins to access a large number of channels of inputs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANNXI POWER TRANSMISSION & TRANSFORMATION CO
- Filing Date
- 2025-08-07
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, FPGA pin resources are consumed excessively, making it impossible to connect multi-channel input circuits with more functions.
The circuit design employs a combination of a 3/8 decoder and a bus driver to convert multi-channel inputs into a bus format. All inputs are polled via the data bus, the input sub-board select pins, and the address bus pins, allowing a large number of channels to be connected using only a small number of FPGA pins.
It enables the connection of hundreds of channels with a small number of FPGA pins, saving FPGA hardware resources.
Smart Images
Figure CN224536044U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of digital maintenance and testing of secondary equipment in substations, specifically to a circuit for a multi-channel input bus. Background Technology
[0002] In the field of power testing, devices often require multi-channel inputs (e.g., a smart waveform recorder needs at least 192 input channels). Hardware designs typically connect all of these to the pins of an FPGA, but this consumes too many FPGA pins, limiting the number of functions that can be integrated into the FPGA hardware. Therefore, it is necessary to design a multi-channel input bus circuit to save FPGA pin resources. Utility Model Content
[0003] The purpose of this invention is to address the aforementioned shortcomings of the existing technology by providing a circuit for a multi-channel open-ended bus.
[0004] The above-mentioned objectives of this utility model are achieved through the following technical means:
[0005] A circuit for a multi-channel open-ended bus, including an FPGA chip,
[0006] The address bus pins of the FPGA chip are connected to the decoding input pins of the 3 / 8 decoder inside the input daughterboard, and the chip select pins of the FPGA chip are connected to the chip enable pins of the 3 / 8 decoder inside the input daughterboard.
[0007] A 3-to-8 decoder corresponds to a set of bus drivers.
[0008] The data B pins of each bus driver in the corresponding group of the 3 / 8 decoder inside the input daughterboard are connected to the data bus pins of the FPGA chip through the same data bus.
[0009] The input signal is connected to the data A pin of the bus driver inside the input sub-board.
[0010] Each decoder output pin of the 3 / 8 decoder in the input sub-board is connected to the enable pin of each bus driver in the corresponding group.
[0011] As mentioned above, there are multiple sub-boards.
[0012] As mentioned above, the 3 / 8 decoder is model 74HC138, and the bus driver is model SN74LVC245A.
[0013] The eight decoding output pins of the 3 / 8 decoder inside the input subboard are connected one-to-one with the enable pins of the eight bus drivers in the corresponding group.
[0014] As mentioned above, the number of data B pins of the bus driver, the number of data bus pins of the FPGA chip, and the number of data lines of the data bus are all 8.
[0015] As mentioned above, the address bus pins of the FPGA chip and the decoding input pins of the 3 / 8 decoder in the FPGA daughterboard are all three and connected one-to-one.
[0016] As described above, the direction control pin of the bus driver inside the daughterboard is connected to the system power supply through a corresponding resistor.
[0017] As mentioned above, the system power supply is 3.3V.
[0018] Compared with the prior art, this utility model has the following advantages:
[0019] This invention utilizes a 3-to-8 decoder and a bus driver to convert multi-channel inputs into a bus format. This allows the FPGA to poll all inputs via the data bus, input sub-board select pins, and address bus pins, enabling access to at least hundreds of input channels using only a dozen or so pins. Attached Figure Description
[0020] Figure 1 This is an overall block diagram of the present invention;
[0021] Figure 2 This is a functional block diagram of the internal interface board of this utility model;
[0022] In the picture:
[0023] SubBoard is an input sub-board;
[0024] FPGA_D[7-0] is the data bus;
[0025] FPGA_A[2-0] is the control bus;
[0026] Backboard is the back panel;
[0027] R1 is the first resistor; R2 is the second resistor; R3 is the third resistor; R4 is the fourth resistor; R5 is the fifth resistor; R6 is the sixth resistor; R7 is the seventh resistor; R8 is the eighth resistor;
[0028] U1 is the first bus driver; U2 is the second bus driver; U3 is the third bus driver; U4 is the fourth bus driver; U5 is the fifth bus driver; U6 is the sixth bus driver; U7 is the seventh bus driver; U8 is the eighth bus driver; U9 is a 3-to-8 decoder;
[0029] DI[0]~DI
[63] are 64 input signals; D[0]~D[7] are 8 data lines of the data bus;
[0030] A1 to A8 are the data A pins of the 8 bus drivers; B1 to B8 are the data B pins of the 8 bus drivers; DIR is the direction control pin of the bus driver; / OE is the enable pin of the bus driver.
[0031] FPGA_D7~FPGA_D0 are the 8 data bus pins of the FPGA chip; FPGA_A2~FPGA_A0 are the 3 address bus pins of the FPGA chip; U9_A2~U9_A0 are the 3 decoding input pins of the 3-to-8 decoder; / EN1 is the chip enable pin of the 3-to-8 decoder.
[0032] CS, CS0, CS1, and CS2 are all on-chip select pins for the FPGA chip.
[0033] Y7~Y0 are the 8 decoding output pins of the 3-8 decoder;
[0034] R8 to R1 are all resistors. Detailed Implementation
[0035] To facilitate understanding and implementation of this utility model by those skilled in the art, the present utility model will be further described in detail below with reference to embodiments. It should be understood that the embodiments described herein are only for illustration and explanation of this utility model and are not intended to limit this utility model.
[0036] like Figure 1 As shown, a multi-channel open-ended bus circuit includes an FPGA chip.
[0037] The address bus pins (FPGA_A2, FPGA_A1, FPGA_A0) of the FPGA chip are connected one-to-one with the decoding input pins (U9_A2, U9_A1, U9_A0) of the 3 / 8 decoder (model 74HC138 in this embodiment) in the input sub-board. The chip select pin (CS) of the FPGA chip is connected to the chip enable pin ( / EN1) of the 3 / 8 decoder in the input sub-board. There are multiple input sub-boards, which can be expanded according to the actual situation.
[0038] A 3-to-8 decoder corresponds to a set of bus drivers. In this embodiment, the bus driver is model SN74LVC245A, and one 3-to-8 decoder corresponds to eight bus drivers (U8-U1).
[0039] The data B-end pins (B1~B8) of each bus driver in the corresponding group of the 3 / 8 decoder in the input daughterboard are connected one-to-one with the data bus pins (FPGA_D7~FPGA_D0) of the FPGA chip through the same data bus (including data lines D[7]~D[0]). That is, the data B-end pin B1 of each bus driver is connected to the data bus pin FPGA_D0 of the FPGA chip through data line D[0], the data B-end pin B2 of each bus driver is connected to the data bus pin FPGA_D1 of the FPGA chip through data line D[1], and so on. The data B-end pin B8 of each bus driver is connected to the data bus pin FPGA_D7 of the FPGA chip through data line D[7].
[0040] Each input signal is connected one-to-one with the data A pin of the bus driver in the input sub-board. In this embodiment, one 3-to-8 decoder corresponds to eight bus drivers and can access 64 input signals. Every eight input signals are connected one-to-one with the data A pin (A8~A1) of the corresponding bus driver.
[0041] The decoder output pins (Y7~Y0) of the 3-8 decoder in the input sub-board are connected one-to-one with the enable pins ( / OE) of each bus driver in the corresponding group.
[0042] The direction control pins of each bus driver (U8~U1) in the input sub-board are connected to the system power supply through corresponding resistors (R8~R1). The system power supply is 3.3V.
[0043] like Figure 2 As shown, since the direction control pins (DIR) of the eight bus drivers (SN74LVC245A) on the input daughterboard are pulled up to the system power supply (high level), the data direction of the bus drivers is from the data A pin to the data B pin. The input daughterboard can send data to the data bus pins (FPGA_D7~FPGA_D0) of the FPGA chip via the input daughterboard chip select pin (CS), address bus pins (FPGA_A2~FPGA_A0), a 3 / 8 decoder, and 64 input signals in a polling manner (8 polls per daughterboard).
[0044] As shown in Table 1, when the chip select pin (CS) of the input sub-board is H (high level), that is, when the chip enable pin ( / EN1) of the 3 / 8 decoder is H (high level), all the output pins (Y7~Y0) of the 3 / 8 decoder are H (high level), and thus all the enable pins ( / OE) of each bus driver are H (high level), and all eight bus drivers are not working. The data bus pins (FPGA_D7~FPGA_D0) of the FPGA chip are not affected by the data of this input sub-board.
[0045] When the chip select pin (CS) of the input sub-board is L (low level), that is, the chip enable pin ( / EN1) of the 3 / 8 decoder is L (low level), the decoder signal (Y7~Y0) will be output according to the signal of the address bus pin (FPGA_A2~FPGA_A0). For example, when “FPGA_A2~FPGA_A0” is “L, L, L”, the decoder signal (Y7~Y0) will be “H, H, H, H, H, H, H, L”, so only one bus driver works (its / OE is connected to Y0 at low level), and the other seven bus drivers do not work. Therefore, the data bus pin (FPGA_D7~FPGA_D0) of the FPGA chip is connected to the input signal DI[7]~DI[0]. Similarly, we can obtain the input sub-board select pins and the address bus pins of the FPGA chip with different levels. The corresponding data bus pins (FPGA_D7~FPGA_D0) of the FPGA chip are connected to the input signals. Table 1 is a logic table of the input signals connected to the data bus pins (FPGA_D7~FPGA_D0) of the FPGA chip.
[0046] Table 1
[0047]
[0048]
[0049] Example 2:
[0050] like Figure 1 As shown, a method for using a multi-channel input bus circuit is described, comprising three input daughter boards. The input daughter board select pins CS of the FPGA chips corresponding to the three input daughter boards are respectively denoted as input daughter board select pin CS0, input daughter board select pin CS1, and input daughter board select pin CS2. The method includes the following steps:
[0051] Step S1: After powering on, the input sub-board select pin CS0 outputs L (low level), and the input sub-board select pins CS1 and CS2 output H (high level), meaning that the first input sub-board is selected, while the second and third input sub-boards are not selected (high impedance output).
[0052] Step S2: The signals on the address bus pins (FPGA_A2~FPGA_A0) of the FPGA chip are polled in 8 bits, so that the FPGA chip reads the 64 input values of the first input sub-board.
[0053] Step S3: Similarly, the output of the input sub-board select pin CS1 is L (low level), and the outputs of the input sub-board select pins CS0 and CS2 are H (high level), indicating that the second input sub-board is selected and the first and third input sub-boards are not selected. The signals on the address bus pins (FPGA_A2~FPGA_A0) of the FPGA chip are polled in 8 bits, so that the FPGA chip reads the 64 input values of the second input sub-board.
[0054] Step S4: Similarly, the FPGA chip continuously switches between input sub-boards and polls the 64 input values inside each input sub-board.
[0055] It should be noted that the embodiments described in this utility model are merely illustrative examples of the spirit of this utility model. Those skilled in the art to which this utility model pertains can make various modifications or additions to the described embodiments or use similar methods to replace them, but without departing from the spirit of this utility model or exceeding the scope defined by the appended claims.
Claims
1. A circuit for a multi-channel open-ended bus, comprising an FPGA chip, characterized in that, The address bus pins of the FPGA chip are connected to the decoding input pins of the 3 / 8 decoder inside the input daughterboard, and the chip select pins of the FPGA chip are connected to the chip enable pins of the 3 / 8 decoder inside the input daughterboard. A 3-to-8 decoder corresponds to a set of bus drivers. The data B pins of each bus driver in the corresponding group of the 3 / 8 decoder inside the input daughterboard are connected to the data bus pins of the FPGA chip through the same data bus. The input signal is connected to the data A pin of the bus driver inside the input sub-board. Each decoder output pin of the 3 / 8 decoder in the input sub-board is connected to the enable pin of each bus driver in the corresponding group.
2. The circuit for a multi-channel open-ended bus according to claim 1, characterized in that, There are multiple access sub-boards.
3. The circuit for a multi-channel open-ended bus according to claim 1, characterized in that, The 3-to-8 decoder is model 74HC138, and the bus driver is model SN74LVC245A.
4. The circuit for a multi-channel open-ended bus according to claim 3, characterized in that, The eight decoding output pins of the 3 / 8 decoder inside the input subboard are connected one-to-one with the enable pins of the eight bus drivers in the corresponding group.
5. The circuit for a multi-channel open-ended bus according to claim 3, characterized in that, The number of data B-terminal pins of the bus driver, the number of data bus pins of the FPGA chip, and the number of data lines of the data bus are all 8.
6. The circuit for a multi-channel open-ended bus according to claim 3, characterized in that, The address bus pins of the FPGA chip and the decoding input pins of the 3 / 8 decoder in the FPGA daughterboard are each three pins and are connected one-to-one.
7. The circuit of a multi-channel open-ended bus according to claim 1, characterized in that, The direction control pin of the bus driver in the input sub-board is connected to the system power supply through a corresponding resistor.
8. The circuit for a multi-channel open-ended bus according to claim 7, characterized in that, The system power supply is 3.3V.