Chip aging test apparatus
By integrating multiple chip testing modules on the test circuit board and a vacuum environment, the problem of low efficiency and poor accuracy in chip aging testing is solved, and efficient and accurate aging testing for batch testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 深圳米飞泰克科技股份有限公司
- Filing Date
- 2025-07-14
- Publication Date
- 2026-07-21
AI Technical Summary
Existing chip aging test methods suffer from low testing efficiency and poor accuracy. This is especially true for chip products with multiple chips integrated in a single package. Traditional single-chip testing methods cannot fully leverage the advantages of scale, resulting in low production efficiency and inaccurate test results.
Design a chip aging test device that integrates multiple chip test modules on a test circuit board, connects each chip to a corresponding chip via a probe connection component, and performs batch aging tests in a vacuum environment to ensure that all chips are aged under the same conditions.
It enables batch aging tests of chip products, improves testing efficiency and accuracy, avoids the impact of differences in testing environment on results, and makes full use of the scale advantages of integrated packaged chip products.
Smart Images
Figure CN224536127U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of chip manufacturing technology, and more specifically, relates to a chip aging test device. Background Technology
[0002] In the chip manufacturing process, burn-in testing (also known as aging testing) is a critical quality control step. It simulates the extreme operating environments that chips might encounter in real-world use, such as high temperatures and high pressures, to induce early detection of potential failures, thereby filtering out defective products and ensuring chip reliability. Currently, the industry commonly uses a method of performing burn-in testing on each chip individually after packaging. However, this method suffers from low testing efficiency and poor accuracy. Utility Model Content
[0003] This application provides a chip aging test apparatus, which aims to improve the technical problems of low test efficiency and poor test accuracy in existing chip aging test modes.
[0004] Therefore, this application provides a chip aging test apparatus for aging tests of chip products, wherein the chip products are integrated with multiple chips, and the chip aging test apparatus includes:
[0005] The test carrier includes a test circuit board and a test base with a test tank. The test tank can accommodate at least one of the chip products. The test circuit board includes multiple chip test modules. Each chip test module is provided with a probe connection component at the bottom of the test tank. Each probe connection component corresponds one-to-one with all the chips of all the chip products accommodated in the test tank and can be electrically connected to the corresponding chip by elastically abutting against the corresponding chip.
[0006] The cover assembly covers the test base, creates a vacuum environment in the test tank, and abuts and fixes the chip product in the test tank.
[0007] Optionally, in some embodiments of this application, the probe connection assembly includes a plurality of elastic probes corresponding one-to-one with the contacts of the chip, and the elastic probes protrude from the bottom of the test groove.
[0008] Optionally, in some embodiments of this application, the test carrier further includes a test base, and the test base is mounted on the test base;
[0009] The chip testing module also includes a test status indicator light, which is located on the test base and surrounds the test base.
[0010] Optionally, in some embodiments of this application, the chip aging test apparatus further includes:
[0011] An image acquisition component is disposed on one side of the test base where each of the test status indicator lights is located, and is used to acquire image information of each of the test status indicator lights;
[0012] The host computer is connected to the image acquisition component and is used to receive the image information from the image acquisition component and obtain the aging test results of the chip product.
[0013] Optionally, in some embodiments of this application, the cover assembly includes:
[0014] The cover body has at least one vacuum hole. The cover body covers the test base and seals the test tank, and abuts and fixes the chip product in the test tank.
[0015] A vacuum suction tube is connected to each of the aforementioned vacuum holes and to the vacuum pumping device.
[0016] Optionally, in some embodiments of this application, the cover body and the test base are fastened to each other by a locking structure or a screw structure.
[0017] Optionally, in some embodiments of this application, the cover body is provided with an elastic pad on the side facing the test tank, and the cover body uses the elastic pad to abut and fix the chip product in the test tank.
[0018] Optionally, in some embodiments of this application, the chip product is a strip structure, and the test slot is a rectangular slot, which can accommodate multiple chip products side by side.
[0019] Optionally, in some embodiments of this application, the bottom of the test tank is provided with at least one chip product accommodating area, and each chip product accommodating area corresponds to accommodating one chip product.
[0020] Optionally, in some embodiments of this application, all the probe connection components in the chip product accommodating area are distributed in a matrix array.
[0021] The chip aging test apparatus provided in this application embodiment, through the above-described structural configuration, integrates multiple chip test modules on its test carrier's test circuit board. Each chip test module operates independently and can complete the aging test operation for its corresponding chip individually. Therefore, when a chip product integrating multiple chips is manufactured and needs aging testing, it is no longer necessary to individually connect each chip to the test equipment to complete the entire test process. Simply open the cover assembly, place one or more chip products into the test chamber, and then close the cover assembly. This allows all chips of these chip products to be in the same vacuum environment while being electrically connected to the corresponding chip test module through corresponding spring-loaded connection components (ensuring that each chip is connected to the test circuit of the corresponding chip test module). At this time, placing the entire chip aging test apparatus into the aging chamber allows all chips of these chip products to undergo aging testing simultaneously, improving the testing efficiency of the chip products. Furthermore, since all chips of these chip products are in the same test environment, the problem of test accuracy being affected by differences in the test environment can be avoided, thus improving the test accuracy of the chip products. As can be seen, the technical solution of this application can realize batch aging tests of chip products, and improve the testing efficiency and accuracy of chip products. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of the chip aging test apparatus provided in the embodiments of this application;
[0024] Figure 2 for Figure 1 A schematic diagram of the test carrier of the chip aging test device shown.
[0025] Figure 3 for Figure 1 A partial V-shaped magnified structural diagram of the test carrier shown;
[0026] Figure 4 for Figure 1 The diagram shows the structure of the test carrier when the chip product is placed.
[0027] The following are the labeling elements in the figure:
[0028] 1. Chip aging test device; 10. Test carrier; 11. Test circuit board; 111. Probe connection assembly; 1111. Flexible probe; 12. Test base; 121. Test tank; 20. Cover assembly; 21. Cover body; 2. Chip product. Detailed Implementation
[0029] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0030] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0031] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0033] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.
[0034] In the chip manufacturing process, burn-in testing is a critical quality control step. It simulates the extreme operating environments that chips might encounter in real-world use, such as high temperatures and high pressures, to induce early detection of potential failures, thereby filtering out defective products and ensuring chip reliability. The industry standard for this approach is to perform burn-in testing on each chip individually after packaging.
[0035] This traditional single-chip testing model has several drawbacks, including: 1. Low testing efficiency: Each chip requires individual connection to the testing equipment to complete the entire testing process sequentially. In large-scale chip production, this results in lengthy testing cycles, severely restricting production efficiency and increasing time costs. 2. Poor testing accuracy: The testing process for each chip is relatively independent, making it difficult to ensure complete consistency of testing conditions. Subtle differences in testing environments between different chips can affect the accuracy and comparability of test results, leading to the failure to accurately detect potential problems in some chips. 3. Inability to fully leverage the scalability advantages of chip products with integrated packages: For chip products such as strip-packaged products with integrated packages containing multiple chips, this traditional single-chip testing model cannot fully utilize the scalability advantages of these products, significantly hindering efficient chip production and quality improvement.
[0036] Therefore, it is necessary to provide a chip aging test device to improve the technical problems of low test efficiency and poor test accuracy in existing chip aging test modes.
[0037] Please see Figures 1 to 4 The chip aging test apparatus 1 provided in this application embodiment will now be described. The chip aging test apparatus 1 includes a test carrier 10 and a cover assembly 20. The test carrier 10 mainly includes a test circuit board 11 and a test base 12 with a test groove 121. The test groove 121 can accommodate at least one chip product 2. The test circuit board 11 includes multiple chip test modules. Each chip test module has a probe connection assembly 111 at the bottom of the test groove 121. Each probe connection assembly 111 corresponds one-to-one with all chips of all chip products 2 accommodated in the test groove 121 and can be electrically connected to the corresponding chip by elastically abutting against the corresponding chip. The cover assembly 20 mainly covers the test base 12, forms a vacuum environment in the test groove 121, and abuts and fixes the chip products 2 in the test groove 121.
[0038] It is understood that the chip aging test apparatus 1 in this application embodiment is mainly used for aging tests during the production process of chip product 2. Here, chip product 2 mainly refers to chip product 2 that integrates multiple chips, such as strip-packaged products. The chip test module mentioned above is equivalent to a test circuit of an existing single-chip test mode, which can provide a stable power supply, accurate signal input, and reliable data acquisition channel for the corresponding chip to realize the aging test of the corresponding chip. Therefore, the specific implementation circuit of each chip test module can refer to the test circuit of the existing single-chip test mode, and this application will not elaborate on it in detail. The main concept of this application is to integrate these chip test modules on the same test circuit board 11. Since each chip test module can operate independently to realize the aging test of the corresponding chip, these chip test modules are connected in parallel in the test circuit board 11. At this time, the power supply module of the test circuit board 11 needs to provide sufficient current output to meet the power supply requirements of these chip test modules operating in parallel at the same time. That is, these chip test modules are individually connected to the power supply module of the test circuit board 11 to realize the parallel connection structure mentioned above.
[0039] The following describes the specific process of aging testing using a chip aging test device 1 that can accommodate one chip product 2 as an example: First, open the cover assembly 20 of the chip aging test device 1, and place the chip product 2 to be aged into the test slot 121 on the test base 12, so that all the chips of the chip product 2 are in contact with a probe connection assembly 111 on the bottom of the test slot 121. Then, close the cover assembly 20 and perform a vacuum operation on the sealed space formed between the cover assembly 20 and the test slot 121, so that all the chips of the chip product 2 are in the same vacuum environment, thereby reducing the influence of external environmental factors on the chip aging test and further ensuring the accuracy of the test. Next, the chip aging test device 1 is placed into the aging chamber. After setting the corresponding test parameters (including but not limited to setting the temperature and pressure in the aging chamber, setting the duration of the aging chamber operation, etc.), the chip aging test device 1 can be started, so that all chips of the chip product 2 are in the same high temperature and high pressure environment and undergo aging tests for the same duration at the same time. In this way, batch aging tests of chip product 2 can be realized, improving the testing efficiency and accuracy of chip product 2.
[0040] Thus, the chip aging test apparatus 1 provided in this application embodiment, through the above-described structural configuration, integrates multiple chip test modules on the test circuit board 11 of its test carrier 10. Each chip test module operates independently and can complete the aging test operation of its corresponding chip individually. Therefore, when a chip product 2 with multiple integrated chips is manufactured and needs to undergo aging testing, it is no longer necessary to connect each chip of the chip product 2 to the test equipment one by one to complete the entire test process sequentially. Simply open the cover assembly 20, place one or more chip products 2 into the test slot 121, and then close the cover assembly 20. This allows all the chips of these chip products 2 to be in the same vacuum environment while being electrically connected to the corresponding chip test module through the corresponding spring-loaded connection assembly (so that each chip is connected to the test circuit of the corresponding chip test module). At this point, by placing the entire chip aging test device 1 into the aging chamber, all chips of these chip products 2 can undergo aging tests simultaneously, thereby improving the testing efficiency of chip products 2. Furthermore, since all chips of these chip products 2 are in the same testing environment, the problem of differences in testing environments affecting the testing accuracy of chip products 2 can be avoided, thus improving the testing accuracy of chip products 2. Therefore, the technical solution of this application can realize batch aging tests of chip products 2, improving the testing efficiency and accuracy of chip products 2.
[0041] In some examples, such as Figure 2 and Figure 3 As shown, the probe connection assembly 111 includes multiple elastic probes 1111, each corresponding to a contact of the chip. The elastic probes 1111 protrude from the bottom of the test groove 121. This structural arrangement of the elastic probes 1111 ensures that after each chip abuts against its corresponding probe connection assembly 111, the elastic force provided by each elastic probe 1111 guarantees that each contact on each chip maintains tight contact with its corresponding elastic probe 1111. This prevents any abnormal interruption of the aging test process due to poor contact between the contacts and the corresponding elastic probe 1111, thus ensuring that the aging test results for each chip are not affected.
[0042] In some examples, the test carrier 10 also includes a test base (not shown), on which the test base 12 is mounted. The chip test module also includes test status indicator lights, which are located on the test base and surround the test base 12. Thus, with the above structural arrangement, after the aging test of the current chip product 2 is completed in this aging test apparatus, relevant personnel can immediately obtain the aging test structure of the current chip product 2 simply by observing the on / off state of the corresponding test status indicator lights.
[0043] It should be noted that the test status indicator lights in this example can be connected to the test circuit of the corresponding chip test module. This allows the test circuit to be disconnected when a chip connected to the same test circuit fails during the aging test, causing the test status indicator lights to turn off simultaneously, indicating that the aging test result of the corresponding chip is unqualified. Conversely, if the test status indicator lights remain lit after the aging test is completed, it indicates that the aging test result of the corresponding chip is qualified. The specific location of the test status indicator lights on the test base in this example is not limited, as long as they are located around the test base 12 to facilitate better observation of the aging test results of the corresponding chip product 2. Therefore, the test status indicator lights representing the aging test results of all chips of the same chip product 2 are preferably located in the same area and arranged in the same way according to the chip arrangement of the corresponding chip product 2.
[0044] In some examples, the chip aging test apparatus 1 also includes an image acquisition component and a host computer. The image acquisition component is mainly located on the side of the test base with the various test status indicator lights, and is used to acquire image information from each indicator light. The host computer is mainly connected to the image acquisition component to receive the image information and obtain the aging test results of the chip product 2. Thus, with the above structural setup, after the current chip product 2 has completed its aging test in this aging test apparatus, the aging test results of the current chip product 2 can be automatically recorded through the cooperation of the image acquisition component and the host computer.
[0045] It should be noted that the image acquisition component in this example can specifically be a device capable of capturing images, such as a CCD camera.
[0046] In some examples, such as Figure 1As shown, the cover assembly 20 specifically includes a cover body 21 and a vacuum suction tube (not shown). The cover body 21 has at least one vacuum hole. The cover body 21 covers the test base 12 and seals the test tank 121, and abuts and fixes the chip product 2 in the test tank 121. The vacuum suction tube is connected to each vacuum hole and to a vacuuming device. Thus, with the above structural arrangement, after the cover body 21 covers the test base 12 and seals the test tank 121, the external vacuuming device can perform a corresponding vacuuming operation on the sealed space formed between the cover assembly 20 and the test tank 121 through the vacuum suction tube, so that all the chips of the chip product 2 are in the same vacuum environment. Furthermore, the cover body 21 and the test base 12 are fastened to each other by a locking structure or a screw structure. Thus, through the above structural design, the locking mechanism or screw structure can ensure that the sealed space formed between the cover assembly 20 and the test tank 121 will not be accidentally opened during the aging test, thus affecting the aging test results of the current chip product 2.
[0047] In some examples, the cover body 21 has an elastic pad (not shown) on the side facing the test tank 121. The cover body 21 uses the elastic pad to abut and fix the chip product 2 in the test tank 121. In this way, the structure of the elastic pad ensures that after each chip abuts against the corresponding probe connection component 111, the elastic force provided by the probe pad ensures that each chip always maintains close contact with the corresponding probe connection component 111. This ensures that each chip will not experience abnormal interruption of the aging test process due to poor contact, thus affecting the aging test results of the corresponding chip.
[0048] In some examples, such as Figure 2 and Figure 3 As shown, chip product 2 has a strip-shaped structure, and the test tank 121 is a rectangular tank that can accommodate multiple chip products 2 side by side. Thus, through this structural arrangement, the aging test apparatus can better adapt to the aging test requirements of strip-packaged chip products 2.
[0049] In some examples, such as Figure 2 and Figure 3As shown, the bottom of the test tank 121 is provided with at least one chip product 2 accommodating area, and each chip product 2 accommodating area corresponds to accommodating one chip product 2. Thus, with the above structural arrangement, when the bottom of the test tank 121 is provided with more than one chip product 2 accommodating area, each chip product 2 accommodating area can accommodate one chip product 2, allowing the test tank 121 to accommodate more than one chip product 2 simultaneously. This enables the aging test apparatus to better perform aging tests on more than one chip product 2 simultaneously, further improving the testing efficiency of the chip product 2.
[0050] In some examples, such as Figure 2 and Figure 3 As shown, all probe connection components 111 in the accommodating area of chip product 2 are distributed in a matrix array. Thus, through the above structural arrangement, the layout of all probe connection components 111 in the accommodating area of chip product 2 can better correspond to the chip layout of the corresponding strip-packaged chip product 2, thereby better adapting to the aging test requirements of the strip-packaged chip product 2.
[0051] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A chip aging test apparatus for aging tests of chip products, wherein the chip products are integrated and packaged with multiple chips, characterized in that, The chip aging test device includes: The test carrier includes a test circuit board and a test base with a test tank. The test tank can accommodate at least one of the chip products. The test circuit board includes multiple chip test modules. Each chip test module is provided with a probe connection component at the bottom of the test tank. Each probe connection component corresponds one-to-one with all the chips of all the chip products accommodated in the test tank and can be electrically connected to the corresponding chip by elastically abutting against the corresponding chip. The cover assembly covers the test base, creates a vacuum environment in the test tank, and abuts and fixes the chip product in the test tank.
2. The chip aging test apparatus as described in claim 1, characterized in that, The probe connection assembly includes a plurality of elastic probes that correspond one-to-one with the contacts of the chip, and the elastic probes protrude from the bottom of the test tank.
3. The chip aging test apparatus as described in claim 1, characterized in that, The test carrier also includes a test base, and the test base is mounted on the test base; The chip testing module also includes a test status indicator light, which is located on the test base and surrounds the test base.
4. The chip aging test apparatus as described in claim 3, characterized in that, The chip aging test apparatus also includes: An image acquisition component is disposed on one side of the test base where each of the test status indicator lights is located, and is used to acquire image information of each of the test status indicator lights; The host computer is connected to the image acquisition component and is used to receive the image information from the image acquisition component and obtain the aging test results of the chip product.
5. The chip aging test apparatus as described in claim 1, characterized in that, The cover assembly includes: The cover body has at least one vacuum hole. The cover body covers the test base and seals the test tank, and abuts and fixes the chip product in the test tank. A vacuum suction tube is connected to each of the aforementioned vacuum holes and to the vacuum pumping device.
6. The chip aging test apparatus as described in claim 5, characterized in that, The cover body and the test base are fastened together by a locking structure or a screw structure.
7. The chip aging test apparatus as described in claim 6, characterized in that, The cover body has an elastic pad on the side facing the test tank, and the cover body uses the elastic pad to abut and fix the chip product in the test tank.
8. The chip aging test apparatus as described in claim 1, characterized in that, The chip product has a strip-shaped structure, and the test slot is a rectangular slot that can accommodate multiple chip products side by side.
9. The chip aging test apparatus according to any one of claims 1-8, characterized in that, The bottom of the test tank is provided with at least one chip product accommodating area, and each chip product accommodating area corresponds to accommodating one chip product.
10. The chip aging test apparatus as described in claim 9, characterized in that, All the probe connection components in the chip product containment area are distributed in a matrix array.