SSD backup power system fault self-detection circuit

Abstract

The utility model discloses a kind of SSD emergency power supply system fault self-detection circuit, it is related to electronic circuit technical field, including: emergency power supply unit, voltage stabilizing unit, reset unit and self-checking circuit, self-checking circuit includes system CPU chip, trigger unit and detection unit, the system CPU chip is used to start detection program according to reset signal, output active detection interrupt signal;Trigger unit is used to trigger emergency power supply unit to enter emergency power supply state according to voltage stabilizing voltage and active detection interrupt signal;Detection unit is used to collect and detect the state of the emergency power supply voltage output by emergency power supply unit after emergency power supply unit enters emergency power supply state.The utility model passes through the active detection function of self-checking circuit, the working state of emergency power supply unit can be detected periodically or on demand, voltage anomaly, charging and discharging fault and other problems of emergency power supply unit are discovered in time.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, and in particular to a fault self-detection circuit for an SSD backup power system. Background Technology

[0002] The core function of an SSD backup power system is to provide temporary power to the data in the DRAM cache during a power outage, ensuring that the data is completely written to the NAND flash memory. If the backup power system hardware malfunctions, the system cannot detect it in time; a subsequent power outage will cause the cache to not be refreshed in time, resulting in partial data loss. Existing designs do not have self-testing capabilities for the backup power system. If the backup power supply malfunctions, subsequent power supply branches will experience fluctuations and jitters, leading to system malfunctions. Current mainstream methods rely on periodic self-tests, but these solutions are mostly aimed at the controller path rather than the backup power unit. For backup power systems, stress tests simulating power outages need to be designed, but such methods require balancing testing accuracy and system overhead, and lack standardized evaluation benchmarks. Utility Model Content

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a fault self-detection circuit for SSD backup power systems, thereby improving the reliability of SSD backup power systems.

[0004] The objective of this utility model is achieved through the following technical solution: A fault self-detection circuit for an SSD backup power system includes: A backup power unit, the input of which is connected to the system power supply, is used to enter the backup power state and output backup power voltage according to the triggering conditions; A voltage regulator unit, the input terminal of which is connected to a backup power unit, is used to regulate the backup power voltage output by the backup power unit and output a regulated voltage to the electrical equipment. A reset unit, the input of which is connected to the output of the voltage regulator unit, is used to output a reset signal after a preset delay when the regulated voltage is a high-level voltage; The self-test circuit includes a system CPU chip, a trigger unit, and a detection unit. The input terminal of the system CPU chip is connected to the output terminal of the reset unit. The input terminal of the trigger unit is connected to the system CPU chip and the voltage regulator unit, and the output terminal of the trigger unit is connected to the backup power unit. The input terminal of the detection unit is connected to the backup power unit, and the output terminal of the detection unit is connected to the system CPU chip. The system CPU chip is used to start the detection program according to the reset signal and output an active detection interrupt signal. The trigger unit is used to trigger the backup power unit to enter the backup power state according to the regulated voltage and the active detection interrupt signal. The detection unit is used to collect and detect the status of the backup power voltage output by the backup power unit after the backup power unit enters the backup power state.

[0005] Furthermore, the specific steps of entering the backup power state based on the triggering conditions are as follows: The system detects the power supply voltage provided by the power supply, and when the power supply voltage is less than or equal to a preset first threshold, it actively enters the backup power state. When it receives an active detection interrupt signal from the system CPU chip, it passively enters the backup power state.

[0006] Furthermore, the triggering unit includes a PMOS transistor and a first resistor. The gate of the PMOS transistor is connected to the regulated voltage terminal, the source of the PMOS transistor is connected to the system CPU chip through the first resistor, and the drain of the PMOS transistor is connected to the backup power unit.

[0007] Furthermore, the detection unit includes a second resistor and a third resistor. One end of the second resistor and the third resistor are both connected to the regulated voltage terminal. The other end of the second resistor is connected to the backup power unit and the system CPU chip. The other end of the third resistor is also connected to the backup power unit and the system CPU chip.

[0008] Furthermore, a voltage conversion unit is also included between the voltage stabilizing unit and the electrical equipment. The input terminal of the voltage conversion unit is connected to the output terminal of the backup power unit and the output terminal of the voltage stabilizing unit, respectively. The output terminal of the voltage conversion unit is connected to the electrical equipment to provide the target voltage to the electrical equipment.

[0009] The beneficial effects of this utility model are: 1) Through the active detection function of the self-test circuit, the working status of the backup power unit can be detected periodically or as needed, and problems such as voltage abnormality and charging / discharging failure of the backup power unit can be detected in a timely manner to prevent the backup power system from failing at critical moments; it has both passive backup power (automatic start when the system power supply fails) and active detection backup power (CPU triggered start), which not only ensures the SSD data security in the event of a sudden power supply failure, but also realizes the active maintenance of the backup power system and improves the system reliability.

[0010] 2) The voltage conversion unit can adapt to SSDs with different voltage specifications, improving the applicability of the circuit. The charging and discharging protection provided by the voltage regulation unit, reset unit, and backup power unit effectively prevents damage to the SSD and circuit components caused by voltage fluctuations and misoperation, extending the equipment's lifespan. Attached Figure Description

[0011] Figure 1 A schematic diagram of a fault self-detection circuit for an SSD backup power system; Figure 2 This is a circuit diagram of a fault self-detection circuit for an SSD backup power system. Detailed Implementation

[0012] The technical solution of this utility model will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0013] See Figures 1-2 This utility model provides a technical solution: A fault self-detection circuit for an SSD backup power system, such as Figure 1 As shown, it includes: A backup power unit, whose input is connected to the system power supply, is used to enter a backup power state and output a backup power voltage based on trigger conditions. In this embodiment, entering the backup power state based on trigger conditions specifically involves: detecting the power supply voltage provided by the system power supply; actively entering the backup power state when the power supply voltage is less than or equal to a preset first threshold; and passively entering the backup power state when an active detection interrupt signal is received from the system CPU chip. The preset first threshold can be set according to the rated voltage of the system power supply. For example, if the system power supply is 12V, the preset first threshold can be set to 10V to ensure timely activation of backup power when the voltage drops significantly.

[0014] The voltage regulator unit, whose input terminal is connected to the backup power unit, is used to regulate the backup power voltage output by the backup power unit and output the regulated voltage to the power-consuming equipment. Since the output voltage of the backup power unit may fluctuate during the backup power process, the voltage regulator unit can use a linear regulator (LDO) or a switching regulator to stabilize the backup power voltage at the rated voltage required by the SSD, so as to avoid voltage fluctuations damaging the SSD or affecting its normal operation.

[0015] A reset unit, whose input is connected to the output of the voltage regulator unit, outputs a reset signal after a preset delay when the regulated voltage is high. The core function of the reset unit is to ensure that the system CPU chip starts the detection program only after the regulated voltage has stabilized, preventing malfunctions caused by unstable voltage. The preset delay can be set according to actual needs, typically between 10ms and 100ms.

[0016] The self-test circuit includes a system CPU chip, a trigger unit, and a detection unit. The input terminal of the system CPU chip is connected to the output terminal of the reset unit. The input terminal of the trigger unit is connected to the system CPU chip and the voltage regulator unit, and the output terminal of the trigger unit is connected to the backup power unit. The input terminal of the detection unit is connected to the backup power unit, and the output terminal of the detection unit is connected to the system CPU chip. The system CPU chip is used to start the detection program according to the reset signal and output an active detection interrupt signal. The trigger unit is used to trigger the backup power unit to enter the backup power state according to the regulated voltage and the active detection interrupt signal. The detection unit is used to collect and detect the status of the backup power voltage output by the backup power unit after the backup power unit enters the backup power state.

[0017] In a specific embodiment, such as Figure 2 As shown, the trigger unit includes a PMOS transistor and a first resistor R10. The gate of the PMOS transistor is connected to the regulated voltage terminal, the source of the PMOS transistor is connected to the system CPU chip through the first resistor, and the drain of the PMOS transistor is connected to the backup power unit. The trigger unit must ensure that the backup power unit is only triggered when the regulated voltage is stable (high level) and an active detection interrupt signal is received, to avoid false triggering.

[0018] The trigger unit works as follows: when the regulated voltage is high (stable voltage) and the system CPU chip outputs a low-level active detection interrupt signal, the PMOS transistor turns on, outputting a trigger signal to the backup power unit, triggering the backup power unit to enter backup power state; if the regulated voltage does not reach a high level, or no active detection interrupt signal is received, the PMOS transistor turns off, and the backup power unit is not triggered, avoiding false triggering. The first resistor is used for current limiting, protecting the PMOS transistor and the system CPU chip; its resistance value can be set according to the actual circuit current, typically 1kΩ-10kΩ.

[0019] like Figure 2 As shown, the detection unit includes a second resistor R8 and a third resistor R9. One end of both the second and third resistors is connected to a regulated voltage terminal, and the other end of the second resistor is connected to the backup power unit and the system CPU chip. The other end of the third resistor is also connected to the backup power unit and the system CPU chip. The detection unit converts the detected voltage signal into an electrical signal that can be recognized by the system CPU chip and feeds it back to the system CPU chip so that the CPU chip can determine whether there is a fault in the backup power unit.

[0020] Furthermore, a voltage conversion unit is also included between the voltage regulator unit and the power-consuming device. The input terminal of the voltage conversion unit is connected to the output terminal of the backup power unit and the output terminal of the voltage regulator unit, respectively. The output terminal of the voltage conversion unit is connected to the power-consuming device to provide the target voltage. Since different SSD models may require different operating voltages (e.g., some SSDs require 3.3V, while others require 5V), the voltage conversion unit can use a DC-DC converter module to achieve flexible voltage conversion, making this circuit applicable to SSDs of different specifications and improving the circuit's versatility. At the same time, the voltage conversion unit can further stabilize the output voltage, reduce voltage ripple, and provide a more stable power supply environment for the SSD.

[0021] This invention utilizes the active detection function of its self-testing circuit to periodically or as needed monitor the operating status of the backup power unit, promptly identifying issues such as voltage anomalies and charging / discharging faults, thus preventing system failure at critical moments. It combines passive backup power (automatic activation during system power failure) and active detection backup power (CPU-triggered activation), ensuring SSD data security during sudden power outages and enabling proactive maintenance of the backup power system, thereby improving system reliability. The voltage conversion unit adapts to SSDs with different voltage specifications, enhancing circuit versatility. The voltage regulation unit, reset unit, and charging / discharging protection of the backup power unit effectively prevent damage to the SSD and circuit components caused by voltage fluctuations and misoperation, extending equipment lifespan.

[0022] The above description is merely a preferred embodiment of this utility model. It should be understood that this utility model is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.

Claims

1. A fault self-detection circuit for an SSD backup power system, characterized in that, include: A backup power unit, the input of which is connected to the system power supply, is used to enter the backup power state and output backup power voltage according to the triggering conditions; A voltage regulator unit, the input terminal of which is connected to a backup power unit, is used to regulate the backup power voltage output by the backup power unit and output a regulated voltage to the electrical equipment. A reset unit, the input of which is connected to the output of the voltage regulator unit, is used to output a reset signal after a preset delay when the regulated voltage is a high-level voltage; The self-test circuit includes a system CPU chip, a trigger unit, and a detection unit. The input terminal of the system CPU chip is connected to the output terminal of the reset unit. The input terminal of the trigger unit is connected to the system CPU chip and the voltage regulator unit, and the output terminal of the trigger unit is connected to the backup power unit. The input terminal of the detection unit is connected to the backup power unit, and the output terminal of the detection unit is connected to the system CPU chip. The system CPU chip is used to start the detection program according to the reset signal and output an active detection interrupt signal. The trigger unit is used to trigger the backup power unit to enter the backup power state according to the regulated voltage and the active detection interrupt signal. The detection unit is used to collect and detect the status of the backup voltage output by the backup power unit after the backup power unit enters the backup power state.

2. The self-detection circuit for SSD backup power system faults according to claim 1, characterized in that: The specific steps for entering standby power state based on triggering conditions are as follows: The system detects the power supply voltage provided by the power supply, and when the power supply voltage is less than or equal to a preset first threshold, it actively enters the backup power state. When it receives an active detection interrupt signal from the system CPU chip, it passively enters the backup power state.

3. The self-detection circuit for SSD backup power system faults according to claim 1, characterized in that: The triggering unit includes a PMOS transistor and a first resistor. The gate of the PMOS transistor is connected to the regulated voltage terminal, the source of the PMOS transistor is connected to the system CPU chip through the first resistor, and the drain of the PMOS transistor is connected to the backup power unit.

4. The self-detection circuit for SSD backup power system faults according to claim 1, characterized in that: The detection unit includes a second resistor and a third resistor. One end of the second resistor and the third resistor are both connected to the regulated voltage terminal. The other end of the second resistor is connected to the backup power unit and the system CPU chip. The other end of the third resistor is also connected to the backup power unit and the system CPU chip.

5. The self-detection circuit for SSD backup power system faults according to claim 1, characterized in that: The voltage regulator unit and the electrical equipment are further connected by a voltage conversion unit. The input terminal of the voltage conversion unit is connected to the output terminal of the backup power unit and the output terminal of the voltage regulator unit, respectively. The output terminal of the voltage conversion unit is connected to the electrical equipment to provide the target voltage to the electrical equipment.

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