Serial-to-parallel chip and electronic device
By designing a serial-to-parallel converter chip, the problems of high cost and complex operation of multi-functional phase-amplitude chip testing equipment were solved. This enabled the testing of serial and parallel protocol chips, reduced equipment cost and size, and simplified the operation process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU SHIDAI SUXIN TECH CO LTD
- Filing Date
- 2025-04-28
- Publication Date
- 2026-07-21
Smart Images
Figure CN224536467U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip functional testing, and in particular to a serial-to-parallel converter chip and electronic device. Background Technology
[0002] Amplitude and phase multifunction chips and their derivatives have shown broad application prospects in many fields, especially in communications, radar, sensing, and artificial intelligence. Amplitude and phase multifunction chips are often based on non-standard communication bus (Serial Peripheral Interface, SPI) protocol. In addition to timing-related interfaces, advanced amplitude and phase multifunction chips often have multiple additional functional ports (I / O) and more than one set of SPI buses.
[0003] In routine testing, wave control equipment is typically used to control and adjust the operating state of amplitude and phase multifunction chips. Common equipment includes: PXI (PCI extensions for Instrumentation) test boards, various digital pattern generators, self-made FPGA (Field-Programmable Gate Array) boards, signal generators, manual DIP switches, or serial-to-parallel converters. However, PXI test boards require expensive chassis, increasing costs; digital pattern generators are complex to operate and bulky; self-made FPGA boards require professional design, are highly customized and specialized, but involve board deployment and additional control board testing; signal generators and manual DIP switches introduce a huge workload and are prone to errors; serial-to-parallel converters can only be used to test some parallel amplitude and phase chips, but are helpless against serial SPI protocol chips, and parallel-to-serial conversion requires a large number of I / O ports and other limitations, limiting their application scope and scenarios.
[0004] Given the above-mentioned technologies, finding a serial-to-parallel converter chip is a problem that urgently needs to be solved by those skilled in the art. Utility Model Content
[0005] The purpose of this invention is to provide a serial-to-parallel converter chip and electronic device. This solves the problems of high cost, implementation difficulty, and complex operation associated with controlling multifunctional chips in existing technologies.
[0006] To solve the above-mentioned technical problems, this utility model provides a serial-to-parallel converter chip, including: a bus transceiver, a reset module, a first-level register module, a second-level register module, a frequency divider module, and a level conversion module;
[0007] The bus transceiver is integrated into the first-level register module.
[0008] The input terminal of the reset module is connected to the reset terminal of the upper-level main control chip as the reset input terminal of the serial-to-parallel converter chip. The output terminal of the reset module is connected to the reset terminal of the first-level register module, and is used to control the first-level register module to perform the corresponding reset operation according to the reset signal sent by the upper-level main control chip.
[0009] The signal terminal of the first-level register module is connected to the signal terminal of the upper-level main control chip as the signal input terminal of the serial-to-parallel converter chip. The first output terminal of the first-level register module is connected to the output terminal of the frequency divider module and the input terminal of the second-level register module. The second output terminal of the first-level register module is connected to the signal terminal of the frequency divider module, which is used to send the data signal sent by the upper-level main control chip to the second-level register module.
[0010] The output of the second-level register module is connected to the input of the level conversion module, and is used to send the data signals stored inside the second-level register module to the level conversion module;
[0011] The enable terminal of the frequency divider module is connected to the first enable input terminal of the serial-to-parallel converter chip and the first enable terminal of the upper-level main control chip, and is used to divide the first enable signal sent by the upper-level main control chip.
[0012] The enable terminal of the level conversion module is connected to the second enable terminal of the serial-to-parallel converter chip as the second enable terminal of the upper-level main control chip. It is used to perform level conversion on the data signal according to the second enable signal sent by the upper-level main control chip and output the corresponding status signal.
[0013] The output of the level conversion module is connected to the control output of the serial-to-parallel converter chip and is used to control the lower-level chip under test according to the output status signal.
[0014] Preferably, the first-level register module includes: a data register and a function register;
[0015] The input terminal of the data register is connected to the input terminal of the function register, and together they serve as the signal terminals of the first-level register module, which are connected to the signal terminals of the upper-level main control chip.
[0016] The reset terminal of the data register is connected to the reset terminal of the function register, and together they serve as the reset terminal of the first-level register module. The data register's reset terminal is connected to the second output terminal of the reset module; the first output terminal and the second output terminal of the reset module together constitute the output terminal of the reset module.
[0017] The output of the data register is connected to the first output of the function register, and together they serve as the first output of the first-level register module, which is connected to the output of the frequency divider module and the input of the second-level register module.
[0018] The second output of the function register is connected to the signal terminal of the frequency divider module as the second output of the first-level register module.
[0019] Preferably, the frequency divider module is a counter;
[0020] Among them, the enable terminal of the counter is connected to the first enable terminal of the upper-level main control chip as the enable terminal of the frequency divider module.
[0021] The signal terminal of the counter is connected to the second output terminal of the first-stage register module, which serves as the signal terminal of the frequency divider module.
[0022] The output of the counter is connected to the input of the second-stage register module as the output of the frequency divider module.
[0023] Preferably, the level conversion module includes: a voltage divider circuit, a comparator, and a drive push-pull circuit;
[0024] The input terminal of the voltage divider circuit is connected to the reference voltage source, and the output terminal of the voltage divider circuit is connected to the first input terminal of the comparator.
[0025] The second input of the comparator is connected to the output of the second register module as the input of the level conversion module, and the output of the comparator is connected to the first terminal of the drive push-pull circuit.
[0026] The power supply terminal of the drive push-pull circuit is connected to the preset voltage source as the power supply terminal of the level conversion module, and the output terminal of the drive push-pull circuit is connected to the downstream chip under test as the output terminal of the level conversion module.
[0027] Preferably, the level conversion module further includes: a buffer;
[0028] The input terminal of the buffer is connected to the output terminal of the voltage divider circuit.
[0029] The output of the buffer is connected to the first input of the comparator.
[0030] Preferably, the drive push-pull circuit includes: a gate drive circuit and a complementary push-pull output circuit;
[0031] In this circuit, the input terminal of the gate drive circuit is connected to the output terminal of the comparator as the input terminal of the drive push-pull circuit.
[0032] The output of the gate drive circuit is connected to the input of the complementary push-pull output circuit.
[0033] The power supply terminal of the gate drive circuit is connected to the power supply terminal of the complementary push-pull output circuit, and together they serve as the power supply terminal for driving the push-pull circuit and are connected to the preset voltage source.
[0034] The output terminal of the complementary push-pull output circuit is connected to the output terminal of the drive push-pull circuit and the next-level chip under test.
[0035] Preferably, the gate drive circuit includes: a first resistor, a first transistor, and a second transistor;
[0036] The first end of the first resistor is connected to the output of the comparator as the input of the gate drive circuit, and the first end of the first resistor is connected to the base of the first transistor and the base of the second transistor.
[0037] The collector of the first transistor is connected to a preset voltage source as the power supply terminal of the gate drive circuit.
[0038] The emitter of the first transistor is connected to the collector of the second transistor, and together they serve as the output of the gate drive circuit and the input of the complementary push-pull output circuit.
[0039] The emitter of the second transistor is grounded.
[0040] Preferably, the complementary push-pull output circuit includes: a second resistor, a first MOSFET, and a second MOSFET;
[0041] The first end of the second resistor is connected to the output end of the gate drive circuit as the input end of the complementary push-pull output circuit, and the first end of the second resistor is connected to the gate of the first MOS transistor and the gate of the second MOS transistor.
[0042] The source of the first MOSFET is connected to a preset voltage source as the power supply terminal of the complementary push-pull output circuit.
[0043] The drain of the first MOSFET is connected to the source of the second MOSFET, and together they serve as the output terminal of the complementary push-pull output circuit, which is connected to the next-level chip under test.
[0044] The drain of the second MOSFET is grounded.
[0045] Preferably, the bus transceiver is a serial SPI bus transceiver.
[0046] On the other hand, this application also provides an electronic device including the above-described serial-to-parallel converter chip.
[0047] Therefore, the serial-to-parallel converter chip provided by this utility model includes a reset module that controls a first-level register module to perform a corresponding reset operation based on a reset signal sent by an upper-level main control chip; a first-level register module that sends data signals sent by the upper-level main control chip to a second-level register module; a second-level register module that sends data signals stored internally to a level conversion module; a frequency divider module that divides the first enable signal sent by the upper-level main control chip; a level conversion module that performs level conversion on the data signal based on a second enable signal sent by the upper-level main control chip and outputs a corresponding status signal; and a level conversion module that controls the lower-level chip under test based on the output status signal. Thus, the serial-to-parallel converter chip provided by this application can control the lower-level chip under test without additional equipment connections, thereby reducing cost and size. Furthermore, the frequency divider module in this application can handle various signal communication rates, and the reset module can achieve port reset, enabling testing of chips corresponding to both serial and parallel protocols, thereby reducing the difficulty of using the chip. Attached Figure Description
[0048] To more clearly illustrate the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a structural diagram of a serial-to-parallel converter chip provided in an embodiment of this application;
[0050] Figure 2 A structural diagram of the first-level register module provided in an embodiment of this application;
[0051] Figure 3 This is a structural diagram of the level conversion module provided in an embodiment of this application;
[0052] Figure 4 A circuit diagram of a drive push-pull circuit provided in an embodiment of this application. Detailed Implementation
[0053] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0054] The core of this invention is to provide a serial-to-parallel converter chip and an electronic device.
[0055] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0056] Figure 1 This is a structural diagram of a serial-to-parallel converter chip provided in an embodiment of this application, as shown below. Figure 1 As shown, it includes: a bus transceiver 1, a reset module 4, a first-level register module 2, a second-level register module 6, a frequency divider module 5, and a level conversion module 3; its current connection relationship is as follows: the bus transceiver 1 is integrated into the first-level register module 2; the input terminal of the reset module 4 is connected to the reset terminal (GRST and DRST) of the upper-level main control chip as the reset input terminal of the serial-to-parallel converter chip, and the output terminal of the reset module 4 is connected to the reset terminal of the first-level register module 2; the signal terminal of the first-level register module 2 is connected to the signal terminal (SCK, SDA, CS, SDO) of the upper-level main control chip as the signal input terminal of the serial-to-parallel converter chip, and the first-level register module 6... The first output terminal of block 2 is connected to the output terminal of frequency divider module 5 and the input terminal of second-stage register module 6. The second output terminal of first-stage register module 2 is connected to the signal terminal of frequency divider module 5. The output terminal of second-stage register module 6 is connected to the input terminal of level conversion module 3. The enable terminal of frequency divider module 5 is connected to the first enable terminal (TRG and TE) of the upper-level master control chip as the first enable input terminal of serial-to-parallel converter chip. The enable terminal of level conversion module 3 is connected to the second enable terminal (OE) of the upper-level master control chip as the second enable input terminal of serial-to-parallel converter chip. The output terminal of level conversion module 3 is connected to the lower-level chip under test as the control output terminal of serial-to-parallel converter chip.
[0057] The upper-level control chip can be an embedded processor, a field-programmable gate array, or other chip; the lower-level chip under test can be a phase-amplitude multi-functional chip.
[0058] One point that needs to be noted is that the I / O ports of the serial-to-parallel converter chip provided in this application correspond to the I / O ports of the upper-level main control chip, as shown in Table 1.
[0059] Table 1
[0060]
[0061] In a specific embodiment, the bus transceiver 1 provided in this application is a serial SPI bus transceiver, and the upper-level master control chip communicates with the serial-to-parallel converter chip provided in this application through the standard 4-Wire SPI protocol. Each frame is 48 bits, and the communication frequency is up to 25MHz. The definition of the data bits in a single frame is shown in Table 2 below.
[0062] Table 2
[0063]
[0064] When the CS signal of the chip (upper-level main control chip and serial-to-parallel converter chip) is high, the serial-to-parallel converter chip provided in this application does not receive data; when the CS signal of the chip is low, the data bits D[47:45] are serially entered from the SDA signal at the rising edge of the SCK signal; when the data bit D
[44] is 1'b0, it is in write mode (W mode), and the data of the data bits D[31:0] is written to the specific register address (ADDR) in the first-level register module 2 pointed to by the data bits D[43:32] at the rising edge of the CS signal; when the data bit D
[44] is 1'b1, it is in read mode (R mode), the data (DATA) of the data bits D[31:0] will be ignored, and after all the data is written (the falling edge of the 17th SCK signal), the signal terminal SDO will serially output the 32 bits of data in the register position pointed to by the data bits D[43:32].
[0065] The DRST and GRST reset pins of the chip are responsible for the reset function of this serial-to-parallel converter chip. When the DRST reset pin signal is low, the signal dat_rst output by the second output of the reset module 4 will reset the address of the specific register 0x000-0x7FF in the corresponding first-level register module 2 to 32'b0. When the DRST reset pin signal is high, the serial-to-parallel converter chip works normally. When the GRST reset pin signal is low, the signal glo_rst output by the first output of the reset module 4 will reset the address of all registers in the first-level register module 2 to their initial value; when the GRST reset pin signal is high, the serial-to-parallel converter chip works normally. That is, register reset and global reset are performed through two reset pins respectively.
[0066] The core of the frequency divider module 5 is a counter with an enable. When the signal at the TE terminal of the chip is high, the signal at the TRG terminal of the chip will be shielded, and the wire_trig signal cannot be generated. Therefore, the data signal in the first-level register module 2 will not be updated to the second-level register module 6, and the frequency divider signal 5 will not be output. When the [0]th bit of the register at address 0x801 in the first-level register module 2 is 0 and the signal at the TE terminal of the chip is low, the rising edge of the signal at the TRG terminal of the chip will synchronously output a wire_trig signal with the same frequency. When the [0]th bit of the register at address 0x801 is 1, a certain number of rising edges of TRG will generate a rising edge of a wire_trig signal, prompting the frequency divider module 5 to perform the frequency division function. The specific number will be determined by the [31:16]th bits of the register at address 0x801. In this design, whether the signal is divided or not, the signal frequency at the TRG terminal can be guaranteed to switch normally at 50MHz, and the edge time of the output of the level conversion module 3 is less than 20% of the trigger signal period.
[0067] The level conversion module 5 clamps the high-level voltage signal output by the first-stage register module 2 to a preset voltage, thereby realizing the level conversion function.
[0068] Furthermore, the frequency divider module 5 and the level conversion module 3 in the above structure are respectively connected to the corresponding voltage sources (VCC1 and VCC2).
[0069] Therefore, the serial-to-parallel converter chip provided by this utility model includes a reset module that controls a first-level register module to perform a corresponding reset operation based on a reset signal sent by an upper-level main control chip; a first-level register module that sends data signals sent by the upper-level main control chip to a second-level register module; a second-level register module that sends data signals stored internally to a level conversion module; a frequency divider module that divides the first enable signal sent by the upper-level main control chip; a level conversion module that performs level conversion on the data signal based on a second enable signal sent by the upper-level main control chip and outputs a corresponding status signal; and a level conversion module that controls the lower-level chip under test based on the output status signal. Thus, the serial-to-parallel converter chip provided by this application can control the lower-level chip under test without additional equipment connections, thereby reducing cost and size. Furthermore, the frequency divider module in this application can handle various signal communication rates, and the reset module can achieve port reset, enabling testing of chips corresponding to both serial and parallel protocols, thereby reducing the difficulty of using the chip.
[0070] Based on the above embodiments, as a preferred embodiment, such as... Figure 2As shown, its first-level register module 2 includes a data register 21 and a function register 22. Their connections are as follows: the input terminal of the data register 21 is connected to the input terminal of the function register 22, and together they serve as the signal terminals of the first-level register module 2, connected to the signal terminals of the upper-level control chip; the reset terminal of the data register 21 is connected to the reset terminal of the function register 22, and together they serve as the reset terminal of the first-level register module 2, connected to the first output terminal of the reset module 4, and the reset terminal of the data register 21 is connected to the second output terminal of the reset module 4; wherein the first output terminal and the second output terminal of the reset module 4 together constitute the output terminal of the reset module 4; the output terminal of the data register 21 is connected to the first output terminal of the function register 21, and together they serve as the first output terminal of the first-level register module 2, connected to the output terminal of the frequency divider module 5 and the input terminal of the second-level register module 6; the second output terminal of the function register 22 serves as the second output terminal of the first-level register module 2, connected to the signal terminal of the frequency divider module 5.
[0071] In a specific embodiment, the first-level register module 2 includes a set of registers with a depth of 2051 and a bit width of 32 bits, which are divided into a data register 21 and a function register 22. The data register 21 is reg_data[0][31:0]-reg_data
[2047] [31:0]; while the function register 22 is reg_data
[2048] [31:0]-reg_data
[2050] [31:0]. Under this structure, the first-level register module 2 pre-stores 2048 sets of data and supports continuous triggering starting from any set of addresses. Combined with the above frequency divider module 5, it can be seen that when reg_data
[2049] [0] is 0 and the signal at the TE terminal of the chip is low, the rising edge of the signal at the TRG terminal of the chip will synchronously output a wire_trig signal with the same frequency; when reg_data
[2049] [0] is 1, and a rising edge of a wire_trig signal is generated at reg_data
[2049] [31:16], the frequency divider module 5 will realize the frequency division function.
[0072] Based on the above embodiments, as a preferred embodiment, such as... Figure 3As shown, the level conversion module 3 includes: a voltage divider circuit 31, a comparator 32, a buffer 33, a gate drive circuit 34, and a complementary push-pull output circuit 35. The circuit connections are as follows: the input terminal of the voltage divider circuit 31 is connected to a reference voltage source (1.8V); the output terminal of the voltage divider circuit 31 is connected to the input terminal of the buffer 33; the output terminal of the buffer 33 is connected to the first input terminal of the comparator 32; the second input terminal of the comparator 32 serves as the input terminal of the level conversion module 3 and is connected to the first output terminal of the first-stage register module 2 and the output terminal of the frequency divider module 6; the output terminal of the comparator 32 is connected to the input terminal of the gate drive circuit 34; the output terminal of the gate drive circuit 34 is connected to the input terminal of the complementary push-pull output circuit 35; the power supply terminal of the gate drive circuit 34 is connected to the power supply terminal of the complementary push-pull output circuit 35, and both are connected to a preset voltage source; the output terminal of the complementary push-pull output circuit 35 serves as the output terminal of the level conversion module 3 and is connected to the next-stage chip under test.
[0073] In a specific embodiment, the level conversion module 3 converts the high-level output voltage latched in the second-stage register module 6 to the voltage VREF corresponding to a preset voltage source. First, the voltage VCC (e.g., 1.8V) corresponding to the reference voltage source forms a 0.9V comparator reference voltage through the voltage divider circuit 31 and the buffer 33. When the output of the first-stage register module 2 is higher than 0.9V, the comparator 32 outputs a high level; otherwise, it outputs a low level. Then, the voltage output by the comparator 32 passes through the gate drive circuit 34 to obtain the VGS voltage of the complementary push-pull output circuit 35. When VGS is high, the complementary push-pull output circuit 35 is turned on, and the final output VOUT = VREF; when VGS is low, the output is turned off, and the final output VOUT = 0V, thereby realizing the level conversion function.
[0074] Among them, such as Figure 4As shown, preferably, the gate driving circuit includes: a first resistor R1, a first transistor Q1, and a second transistor Q2. The circuit connection is as follows: the first end of the first resistor R1 is connected to the output of the comparator 32 as the input of the gate driving circuit 34; the first end of the first resistor R1 is connected to the base of the first transistor Q1 and the base of the second transistor Q2; the collector of the first transistor Q1 is connected to a preset voltage source as the power supply of the gate driving circuit 34; the emitter of the first transistor Q1 is connected to the collector of the second transistor Q2, and together they serve as the output of the gate driving circuit 34 and are connected to the input of the complementary push-pull output circuit 35; the emitter of the second transistor Q2 is grounded. The complementary push-pull output circuit includes: a second resistor R2, a first MOSFET Q3, and a second MOSFET Q4. Their connections are as follows: the first end of the second resistor R2 serves as the input terminal of the complementary push-pull output circuit 35 and is connected to the output terminal of the gate drive circuit 34; the first end of the second resistor R2 is connected to the gate of the first MOSFET Q3 and the gate of the second MOSFET Q4; the source of the first MOSFET Q3 serves as the power supply terminal of the complementary push-pull output circuit 35 and is connected to a preset voltage source; the drain of the first MOSFET Q3 is connected to the source of the second MOSFET Q4, and together they serve as the output terminal of the complementary push-pull output circuit 35, connected to the next-stage chip under test; the drain of the second MOSFET Q4 is grounded.
[0075] Among them, the first transistor Q1 is an NPN transistor; the second transistor Q2 is a PNP transistor; the first MOSFET Q3 is an N-type MOSFET; and the second MOSFET Q4 is a P-type MOSFET.
[0076] In summary, the operating logic of the serial-to-parallel converter chip for amplitude and phase multi-function wave control testing provided in this application is as follows: When the serial-to-parallel converter chip is working, a single frame of 32-bit data is written to reg_data[2047:0] via a 4-wire SPI bus, corresponding to the high and low level states of the second-level register module 6. The state of the reg_data data register corresponds to the IO state of 2048 frames. The registers (data register 21 and function register 22) of the serial-to-parallel converter chip are defined as shown in Table 3 below.
[0077] Table 3
[0078]
[0079] The serial-to-parallel converter chip outputs data with the following start address: start_addr = reg_data
[2048] [10:0], and stop_addr = reg_data
[2048] [26:16]. When the TE terminal of the chip is low, the initial addr is start_addr. Whenever the wire_trig signal rises, the data in reg_data[addr][31:0] is immediately updated and output to the second-level register module 6. Then, addr is automatically incremented by 1 until stop_addr. When the TE terminal of the chip rises, addr = start_addr. In this manner, the TRG terminal of the chip updates the data in the second-level register module 6 of the specified length to the output, completing the serial timing output. Meanwhile, the update of the second-level register module 6 is affected by the signal update[31:0] = reg_data
[2050] [31:0]. When update[x] = 0, only reg_IO[x] in the second-level register module 6 will not be updated. That is, if some bits in update[31:0] are 0, the corresponding bits in reg_IO[31:0] will not participate in the update. When update[x] = 1, only reg_IO[x] in the second-level register module 6 is updated normally. This ensures that specific ports can have parallel output in serial timing. When the signal at the OE terminal of the chip is low, the level conversion circuit module 3 converts the high-level voltage output of the second-level register module 6 to VREF.
[0080] It should be noted that the output of the second-level register module 6 can also be understood as the output of the I / O port. This can also be understood as supporting the updating and enabling of each I / O, determining whether the I / O follows the trigger signal to update to the new frame or retains the state of the previous frame.
[0081] It should be noted that the embodiments provided in this application are only one possible implementation method, but are not limited to this implementation method. Users can set their own implementation methods according to their needs.
[0082] Therefore, the serial-to-parallel converter chip provided in this application has the following advantages:
[0083] 1. It adopts the standard 4-wire SPI protocol driver, and the data length is defined as an integer byte. It can use the hardware SPI of the embedded processor or USB to SPI modules such as FT2232 for high-speed communication and convenient control.
[0084] 2. All functional chips and derivative products can be driven by serial-to-parallel conversion chips, which has good versatility.
[0085] 3. Small size.
[0086] 4. Low cost.
[0087] 5. Because the serial-to-parallel converter chip uses a standard communication interface, it can use pre-developed driver header files to quickly perform secondary development and integrate into a unified host computer interface, making development convenient.
[0088] 6. It comes with a built-in level conversion module, eliminating the need for additional circuitry, simplifying the external circuit design, and increasing interface electrical compatibility.
[0089] On the other hand, this application also provides an electronic device that includes the above-mentioned serial-to-parallel converter chip and has the same beneficial effects.
[0090] Since the embodiments provided in this application are the same as the embodiments of the serial-to-parallel chip described above, they will not be described again here.
[0091] The foregoing has provided a detailed description of the serial-to-parallel converter chip and electronic device provided by this utility model. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this utility model without departing from the principle of this utility model, and these improvements and modifications also fall within the protection scope of the claims of this utility model.
[0092] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
Claims
1. A serial-to-parallel converter chip, characterized in that, include: Bus transceiver, reset module, first-level register module, second-level register module, frequency divider module, and level conversion module; The bus transceiver is integrated into the first-level register module; The input terminal of the reset module is connected to the reset terminal of the upper-level main control chip as the reset input terminal of the serial-to-parallel converter chip, and the output terminal of the reset module is connected to the reset terminal of the first-level register module. It is used to control the first-level register module to perform the corresponding reset operation according to the reset signal sent by the upper-level main control chip. The signal terminal of the first-level register module is connected to the signal terminal of the upper-level main control chip as the signal input terminal of the serial-to-parallel converter chip. The first output terminal of the first-level register module is connected to the output terminal of the frequency divider module and the input terminal of the second-level register module. The second output terminal of the first-level register module is connected to the signal terminal of the frequency divider module, which is used to send the data signal sent by the upper-level main control chip to the second-level register module. The output of the second-stage register module is connected to the input of the level conversion module, and is used to send the data signal stored inside the second-stage register module to the level conversion module; The enable terminal of the frequency divider module is connected to the first enable input terminal of the serial-to-parallel converter chip and the first enable terminal of the upper-level main control chip, and is used to divide the first enable signal sent by the upper-level main control chip. The enable terminal of the level conversion module is connected to the second enable terminal of the serial-to-parallel converter chip as the second enable terminal of the upper-level main control chip. It is used to perform level conversion on the data signal according to the second enable signal sent by the upper-level main control chip and output the corresponding status signal. The output of the level conversion module is connected to the downstream chip under test as the control output of the serial-to-parallel converter chip, and is used to control the downstream chip under test according to the output status signal.
2. The serial-to-parallel converter chip according to claim 1, characterized in that, The first-level register module includes: a data register and a function register; The input terminal of the data register is connected to the input terminal of the function register, and together they serve as the signal terminal of the first-level register module, which is connected to the signal terminal of the upper-level main control chip. The reset terminal of the data register is connected to the reset terminal of the function register, and together they serve as the reset terminal of the first-level register module, connected to the first output terminal of the reset module. The reset terminal of the data register is also connected to the second output terminal of the reset module. The first output terminal and the second output terminal of the reset module together constitute the output terminal of the reset module. The output terminal of the data register is connected to the first output terminal of the function register, and together they serve as the first output terminal of the first-level register module, which is connected to the output terminal of the frequency divider module and the input terminal of the second-level register module. The second output terminal of the function register is connected to the signal terminal of the frequency divider module as the second output terminal of the first-level register module.
3. The serial-to-parallel converter chip according to claim 1, characterized in that, The frequency division module is a counter; The enable terminal of the counter is connected to the first enable terminal of the upper-level main control chip as the enable terminal of the frequency divider module. The signal terminal of the counter is connected to the second output terminal of the first-stage register module as the signal terminal of the frequency divider module. The output of the counter is connected to the input of the second-stage register module as the output of the frequency divider module.
4. The serial-to-parallel converter chip according to claim 1, characterized in that, The level conversion module includes: a voltage divider circuit, a comparator, and a drive push-pull circuit; The input terminal of the voltage divider circuit is connected to the reference voltage source, and the output terminal of the voltage divider circuit is connected to the first input terminal of the comparator. The second input terminal of the comparator is connected to the output terminal of the second-stage register module as the input terminal of the level conversion module, and the output terminal of the comparator is connected to the first terminal of the drive push-pull circuit. The power supply terminal of the drive push-pull circuit is connected to a preset voltage source as the power supply terminal of the level conversion module, and the output terminal of the drive push-pull circuit is connected to the downstream chip under test as the output terminal of the level conversion module.
5. The serial-to-parallel converter chip according to claim 4, characterized in that, The level conversion module further includes: a buffer; The input terminal of the buffer is connected to the output terminal of the voltage divider circuit; The output of the buffer is connected to the first input of the comparator.
6. The serial-to-parallel converter chip according to claim 5, characterized in that, The drive push-pull circuit includes: a gate drive circuit and a complementary push-pull output circuit. The input terminal of the gate driving circuit is connected to the output terminal of the comparator as the input terminal of the driving push-pull circuit. The output terminal of the gate drive circuit is connected to the input terminal of the complementary push-pull output circuit. The power supply terminal of the gate driving circuit is connected to the power supply terminal of the complementary push-pull output circuit, and together they serve as the power supply terminal of the driving push-pull circuit and are connected to the preset voltage source. The output terminal of the complementary push-pull output circuit is connected to the lower-level chip under test as the output terminal of the driving push-pull circuit.
7. The serial-to-parallel converter chip according to claim 6, characterized in that, The gate drive circuit includes: a first resistor, a first transistor, and a second transistor; Wherein, the first end of the first resistor is connected to the output end of the comparator as the input end of the gate drive circuit, and the first end of the first resistor is connected to the base of the first transistor and the base of the second transistor. The collector of the first transistor is connected to the preset voltage source as the power supply terminal of the gate drive circuit; The emitter of the first transistor is connected to the collector of the second transistor, and together they serve as the output terminal of the gate drive circuit and are connected to the input terminal of the complementary push-pull output circuit. The emitter of the second transistor is grounded.
8. The serial-to-parallel converter chip according to claim 7, characterized in that, The complementary push-pull output circuit includes: a second resistor, a first MOSFET, and a second MOSFET; Wherein, the first end of the second resistor serves as the input end of the complementary push-pull output circuit and is connected to the output end of the gate drive circuit, and the first end of the second resistor is connected to the gate of the first MOS transistor and the gate of the second MOS transistor. The source of the first MOS transistor is connected to the preset voltage source as the power supply terminal of the complementary push-pull output circuit. The drain of the first MOS transistor is connected to the source of the second MOS transistor, and together they serve as the output terminal of the complementary push-pull output circuit, which is connected to the next-level chip under test. The drain of the second MOSFET is grounded.
9. The serial-to-parallel converter chip according to any one of claims 1-8, characterized in that, The bus transceiver is a serial SPI bus transceiver.
10. An electronic device, characterized in that, Includes the serial-to-parallel converter chip as described in any one of claims 1-9.