signal generator
By using a motherboard and daughterboard structure for the signal generator, the structure of the signal generator is simplified, the problem of unstable signal quality is solved, it is suitable for signal testing of high-resolution automotive displays, and maintenance costs are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU HUAXING YUANCHUANG TECH CO LTD
- Filing Date
- 2025-07-30
- Publication Date
- 2026-07-21
AI Technical Summary
Existing signal generators have poor signal quality stability when outputting EDP/HDMI signals to in-vehicle displays, which can easily lead to problems such as abnormal images or failure to light up. In addition, they are complex in structure and expensive, and cannot meet the needs of high-resolution in-vehicle displays.
It adopts a motherboard and daughterboard structure. The motherboard contains an ARM module and an FPGA module, and the daughterboard contains an encoding unit. It directly outputs power signals through an interface module. The daughterboard receives and outputs the encoded signals, which simplifies the structure, avoids wire connections, and is suitable for more application scenarios to meet different signal output requirements.
It improves signal stability, simplifies the signal generator structure, reduces maintenance costs, is suitable for more application scenarios, and enables signal testing of high-resolution vehicle displays.
Smart Images
Figure CN224536499U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display signal technology, and in particular to a signal generator. Background Technology
[0002] Currently, there are two main types of automotive displays from screen manufacturers: bare chips and finished automotive displays. Finished automotive displays typically use FDP-LINK or GMSL as their signal source. With advancements in display technology and a surge in demand for automotive displays, the resolution of these displays is also increasing. FDP-LINK and GMSL have evolved to third or fourth generation protocols, and their encoding chips generally use EDP or HDMI signals as their signal input source.
[0003] In related technologies, signal output can be achieved by using a signal generator, a converter, and cables. However, this method results in poor signal quality stability, which can lead to abnormal images or even failure to light up the screen. Utility Model Content
[0004] Therefore, it is necessary to provide a signal generator that can improve signal stability and enhance signal quality to address the problem of poor screen detection signal quality.
[0005] A signal generator, the signal generator comprising:
[0006] The motherboard has an interface module for outputting display signals, control signals, and power signals.
[0007] The sub-board, connected to the interface module, is used to receive the control signal, the display signal, and the power signal, and to output the encoded signal and the power signal.
[0008] In one embodiment, the motherboard includes an ARM module and an FPGA module, and the display signals include HDMI signals and / or EDP signals.
[0009] In one embodiment, the FPGA module is electrically connected to the ARM module, the FPGA module receives image parameter instructions transmitted by the ARM module, and outputs the display signal and the control signal.
[0010] In one embodiment, the motherboard includes a power module, which is electrically connected to the FPGA module via a digital-to-analog converter module. The interface module is electrically connected to the power module. The power module is used to receive a power configuration signal output by the FPGA module and output a power signal matching the power configuration signal to the interface module.
[0011] In one embodiment, the motherboard further includes an analog-to-digital converter module, which is electrically connected to the power supply module and the FPGA module respectively, and is used to receive circuit parameter information from the power supply module and output circuit parameter signals corresponding to the circuit parameter information to the FPGA module.
[0012] In one embodiment, the subboard includes an encoding unit for receiving the control signal and the display signal, and outputting the encoded signal.
[0013] In one embodiment, the encoding unit includes an FPD-LINK encoding chip and / or a GMSL encoding chip.
[0014] In one embodiment, the subboard further includes a signal buffer unit electrically connected to the encoding unit, for receiving the display signal output by the interface module and sending the display signal to the encoding unit.
[0015] In one embodiment, the sub-board further includes a display output interface electrically connected to the encoding unit for receiving and outputting the encoded signal.
[0016] In one embodiment, the daughterboard further includes a power output interface for receiving and outputting power signals from the interface module.
[0017] The aforementioned signal generator includes a motherboard and a daughterboard. The motherboard has an interface module for outputting display signals, control signals, and power signals. The daughterboard connects to the interface module, receives the display signals, control signals, and power signals, and outputs encoded signals and power signals. The power signal supplies power to the display screen, enabling the screen to display according to the encoded signals, thus achieving screen testing. The motherboard directly outputs power signals through the interface module, eliminating the need for a separate power module and power supply for the daughterboard, simplifying the signal generator's structure. The daughterboard connects directly to the motherboard via the interface module, eliminating the need for additional cables and avoiding signal quality issues caused by wiring connections, making it suitable for more application scenarios. The daughterboard can directly output encoded signals based on display and control signals. By configuring the daughterboard according to the actual application scenario, different signal output requirements can be met. The implementation is simple, requiring no changes to the motherboard hardware structure, facilitating future maintenance and reducing maintenance costs. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the structure of a signal generator in one embodiment.
[0019] Figure 2 This is a schematic diagram of the signal generator in another embodiment.
[0020] Figure 3 This is a schematic diagram of the signal generator in another embodiment. Detailed Implementation
[0021] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0022] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0023] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0024] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0025] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0026] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.
[0027] With technological advancements, the resolution of in-vehicle displays is increasing. Consequently, FPD-LINK (Flat Panel Display Link) or GMSL (Gigabit Multimedia Serial Link) protocols have evolved to third or fourth generation. Their encoding chips typically use EDP or HDMI signals as input sources. FPD-LINK or GMSL outputs are differential or single-ended signals, with no other signals. Output connectors are standard automotive cable connectors, typically single-pin, dual-pin, or four-pin, depending on whether the signal is differential or single-ended. Power is supplied via a single path, usually 12V or 24V. Therefore, if an existing signal generator lacks EDP / HDMI signals, it cannot output FPD-LINK or GMSL signals via an adapter board. Even with a signal source, the existing signal generator itself requires multiple power outputs, resulting in higher costs and a fixed power supply, making it impossible to guarantee the required power output. If using the existing equipment, in the first scenario, the signal generator's signal meets the requirements, but an external signal conversion board is needed, requiring independent power and resulting in a complex structure. Secondly, because EDP / HDMI signals are high-speed signals, using cables will encounter signal quality instability issues, potentially leading to abnormal images or even failure to display the image. In the second scenario, the existing signal generator cannot output EDP / HDMI signals, requiring conversion using other signals. However, this approach has limitations. FPD-LINK / GMSL signals have relatively high speeds, and since EDP / HDMI signals are also high-speed, if the existing signal generator only outputs relatively low-speed signals, while it can convert to EDP / HDMI signals, it cannot convert them to the corresponding high-speed state. This results in the subsequent signal conversion not meeting the requirements, necessitating the development of a new signal generator, which increases both the development time and cost.
[0028] To address the aforementioned problems, this application provides a signal generator, see reference. Figure 1 , Figure 1 A schematic diagram of a signal generator according to an embodiment of this application is shown. (Refer to...) Figure 1 As shown, the signal generator 100 includes:
[0029] Motherboard 110, the motherboard having interface module 111, the interface module being used to output display signals, control signals and power signals;
[0030] For example, the motherboard has an interface module that can output display signals, control signals, and power signals. In some examples, the display signals are used to provide display information, such as information corresponding to the image to be displayed; the control signals are used to provide display parameters, such as, but not limited to, display refresh rate and resolution, which can be determined according to the actual application scenario.
[0031] Optionally, the interface module may include an interface capable of outputting high-frequency and low-frequency signals.
[0032] The sub-board 120 is connected to the interface module and is used to receive the control signal, the display signal and the power signal, and output the encoded signal and the power signal.
[0033] For example, the daughterboard is connected to the interface module to receive control signals, display signals, and power signals. In some examples, the daughterboard has a port corresponding to the interface module, which can be directly electrically connected to the interface module. For instance, the daughterboard may have gold fingers corresponding to the interface module for connecting to the interface module on the motherboard.
[0034] Optionally, the encoded signal can be data that the display screen can directly receive and display, which can be determined according to the actual application scenario. In some examples, the signal generator is connected to the display screen under test (DUT) to output a signal to the DUT so that the display screen can display according to the received signal, thereby performing a display test on the DUT. In some examples, the daughterboard outputs a power signal to the DUT to power the display screen.
[0035] In this embodiment, the signal generator includes a motherboard and a daughterboard. The motherboard has an interface module for outputting display signals, control signals, and power signals. The daughterboard is connected to the interface module, receives the display signals, control signals, and power signals, and outputs encoded signals and power signals. The power signals supply power to the display screen, enabling the display screen to display according to the encoded signals, thus achieving display screen testing. The motherboard directly outputs power signals through the interface module, eliminating the need for a separate power module and power supply for the daughterboard, simplifying the signal generator's structure. The daughterboard connects directly to the motherboard through the interface module, eliminating the need for additional cables for adapters and avoiding signal quality issues caused by cable connections, making it suitable for more application scenarios. The daughterboard can directly output encoded signals based on the display and control signals. By configuring the daughterboard according to the actual application scenario, different signal output requirements can be met, and the implementation is simple, requiring no changes to the motherboard hardware structure, facilitating later maintenance and reducing maintenance costs.
[0036] In one embodiment, such as Figure 3As shown, the motherboard includes an ARM module 112 and an FPGA module 113, and the display signals include HDMI signals and / or EDP signals.
[0037] For example, the motherboard includes an ARM (Advanced RISC Machines) module and an FPGA (Field-Programmable Gate Array) module for generating and outputting display and control signals.
[0038] Optionally, the display signals include HDMI (High-Definition Multimedia Interface) signals and / or EDP (Embedded DisplayPort, a digital display interface optimized for mobile devices) signals. HDMI and / or EDP signals can be used as input sources to enable FPD-LINK (Flat Panel Display Link) and GMSL (Gigabit Multimedia Serial Link) signal transmission.
[0039] In this embodiment, the motherboard adopts an ARM+FPGA architecture, which can output different signals according to actual application requirements and is suitable for more application scenarios.
[0040] In one embodiment, the FPGA module is electrically connected to the ARM module, the FPGA module receives image parameter instructions transmitted by the ARM module, and outputs the display signal and the control signal.
[0041] For example, the FPGA module is electrically connected to the ARM module. The ARM module outputs image parameter instructions to the FPGA module, and the FPGA module outputs corresponding display signals and control signals according to the received image parameter instructions. In some examples, the image parameter instructions can be determined based on the signal type, test object, test item, etc., of the display signals required to be output in the actual application scenario.
[0042] In this embodiment of the disclosure, the ARM module transmits image parameter instructions to the FPGA module, enabling the FPGA module to output display signals and control signals, thereby achieving the output of the corresponding signals quickly and accurately.
[0043] In one embodiment, the motherboard includes a power module, which is electrically connected to the FPGA module via a digital-to-analog converter module. The interface module is electrically connected to the power module. The power module is used to receive a power configuration signal output by the FPGA module and output a power signal matching the power configuration signal to the interface module.
[0044] For example, the motherboard also includes a power module, which is electrically connected to the FPGA module via a digital-to-analog converter module, and the interface module is electrically connected to the power module. The FPGA module configures the output of the power module, outputting a power configuration signal to the power module. This power configuration signal can be determined based on the power requirements of the actual application scenario; for example, it can be determined based on the power supply requirements of the display under test.
[0045] Optionally, after receiving the power configuration signal, the power module outputs a power signal to the interface module based on the power configuration signal. In some examples, the power configuration signal may include, but is not limited to, current configuration information, voltage configuration information, etc. In some examples, the digital-to-analog converter converts the power configuration signal into an analog signal that the power module can recognize, so that the power module outputs a corresponding power signal to the interface module.
[0046] In this embodiment, a power module is set on the motherboard, which can configure and output power according to actual application requirements. At the same time, the power module is directly connected to the interface module, and outputs power to the daughter board through the interface module. The daughter board does not need to be powered independently, which effectively simplifies the structure of the signal generator, reduces costs, and is suitable for more application scenarios.
[0047] In one embodiment, the motherboard further includes an analog-to-digital converter module, which is electrically connected to the power supply module and the FPGA module respectively, and is used to receive circuit parameter information from the power supply module and output circuit parameter signals corresponding to the circuit parameter information to the FPGA module.
[0048] For example, the motherboard also includes an analog-to-digital converter (ADC) module, which is electrically connected to the power supply module and the FPGA module. The ADC module converts the circuit parameter information of the power supply module into digital signals, i.e., circuit parameter signals, and outputs these signals to the FPGA module.
[0049] In this embodiment of the disclosure, the circuit parameter information of the power module is converted into circuit parameter information through an analog-to-digital conversion module, thereby enabling the determination of the working status of the power module and improving the stability and reliability of the signal generator operation.
[0050] In one embodiment, the subboard includes an encoding unit for receiving the control signal and the display signal, and outputting the encoded signal.
[0051] For example, the daughterboard includes an encoding unit that receives control signals and display signals, and outputs encoded signals. In some examples, the encoding unit may include, but is not limited to, an encoding chip.
[0052] Optionally, the encoding unit can be determined based on the actual application scenario. In some examples, it can be determined based on the interface protocol of the display screen under test.
[0053] In this embodiment of the disclosure, by setting up an encoding unit, a dedicated signal generation can be achieved, which reduces the system bloat of a general signal generator, lowers the frequency of program modification, and makes maintenance convenient and reduces maintenance costs.
[0054] In one embodiment, the encoding unit includes an FPD-LINK encoding chip and / or a GMSL encoding chip.
[0055] For example, the encoding unit includes an FPD-LINK encoding chip and / or a GMSL encoding chip, which can generate encoded signals based on display signals and control signals. The encoded signals can be used for testing the display screen corresponding to the FPD-LNK / GML interface protocol.
[0056] In one embodiment, the subboard further includes a signal buffer unit electrically connected to the encoding unit, for receiving the display signal output by the interface module and sending the display signal to the encoding unit.
[0057] For example, the daughterboard also includes a signal buffer unit disposed between the interface and the encoding unit for buffering and reading the received high-frequency signal. In some examples, when the display signal is a high-frequency signal, the interface module transmits the display signal to the signal buffer unit, and the signal buffer unit sends the received display signal to the encoding unit.
[0058] In this embodiment, a signal buffering unit is used to buffer high-frequency signals, which improves the stability and reliability of signal transmission, thereby effectively improving the stability of the encoded signal output by the daughterboard. This makes it suitable for more application scenarios and improves the display screen testing effect.
[0059] In one embodiment, the sub-board further includes a display output interface electrically connected to the encoding unit for receiving and outputting the encoded signal.
[0060] For example, the daughterboard includes a display output interface, which is electrically connected to the encoding unit for receiving and outputting the encoded signal output by the encoding unit.
[0061] Optionally, the display output interface can be connected to the display interface of the display screen under test. The encoded signal output through the display output interface can enable the display screen under test to display according to the display signal and control signal.
[0062] In one embodiment, the daughterboard further includes a power output interface for receiving and outputting power signals from the interface module.
[0063] For example, the daughterboard includes a power output interface that receives and outputs power signals from the interface module. In some examples, the daughterboard is connected to the interface module through a corresponding interface on the daughterboard, and the power output interface is electrically connected to the corresponding interface on the daughterboard, receiving power signals output by the interface module through the corresponding interface on the daughterboard.
[0064] In this embodiment of the disclosure, a display output interface and a power output interface are provided on the daughterboard, which can realize the connection with the display interface and power interface corresponding to the display screen under test, and realize the display control and power supply of the display screen under test.
[0065] Figure 3 This is a schematic diagram illustrating the structure of a signal generator according to an exemplary embodiment. (Refer to...) Figure 3As shown, the signal generator includes a mainboard and independent sub-boards (corresponding to daughterboards). The main design of the signal generator is still based on the ARM+FPGA architecture, where the ARM module can be configured according to actual needs. In some examples, the ARM includes common interfaces such as PMIC (Power Management Integrated Circuit), EMMC (Embedded Multi-Media Controller), DDR (Double Data Rate Synchronous Dynamic Random-Access Memory), USB (Universal Serial Bus), and serial port, enabling peripherals with common functions such as network port, USB, serial port, and PCIe (Peripheral Component Interconnect Express). The PMIC powers the ARM module, the EMMC stores the ARM's own system program, FPGA program, and image storage, the DDR is the memory, and the network port is a gigabit network port used to communicate with the host computer and receive control signals from the PC. The USB and serial ports are peripheral interfaces, facilitating later debugging, maintenance, and functional expansion.
[0066] The FPGA is selected to have high-speed signal output, for example, a chip that meets DP1.4 and HDMI2.1 output standards, enabling signal rates of over 20Gbps. The output power supply uses a DC-DC converter (DC-DC converter), with a DAC (digital-to-analog converter) for voltage setting and I2C (intra-communication protocol) for voltage and current reading. An independent power supply module facilitates future maintenance and upgrades. The signal section uses a general-purpose interface such as the M2 interface (corresponding to the interface module), internally containing output EDP / HDMI signals (corresponding to display signals) and some control I / O (corresponding to control signals). The output power (corresponding to power signals) is also input to the M2 interface, and then outputs the corresponding signal interface (corresponding to the display output interface) and power interface (corresponding to the power output interface) through the FPD-LINK / GMSL small board. The signal generator motherboard is equipped with an ARM+FPGA and comes pre-installed with a power module. The power output is fed into the M2 interface. All signals output by the FPGA, such as EDP / HDMI signals (corresponding to display signals) and I2C / GPIO (General-Purpose Input / Output) signals (corresponding to control signals), are output to the M2 interface. The external FPD-LINK / GMSL signal board for the M2 interface can be made according to the signal decoding chip and signal interface type definition of the screen.
[0067] The FPGA's function is to receive image parameter control instructions (corresponding to image parameter instructions) from the ARM, and output ED / HDMI signals of the corresponding resolution, as well as related parameters such as I2C / GPIO, to the M2 interface board. The M2 interface board interfaces with the backend screen decoding chip to output images and power in the corresponding format. The VBL power module (corresponding to the power module) mainly generates a VBL (Vertical Blanking Interval, a signal used to control the backlight and provide power in video signals) power to the screen (corresponding to the display under test). The screen needs this power to drive its own backlight and power its own ICs.
[0068] In some examples, the ARM can use chips such as RK3562 / RK3568 / RK3588, which can be selected according to the actual application scenario and cost requirements. The ARM needs to be powered by a PMIC and has common peripherals such as DDR, eMMC, Gigabit Ethernet, USB, and serial port. PCIe interacts and controls the FPGA to transmit image parameters and control commands. In addition, the ARM controls the FPGA startup and loads programs through some control pins. Subsequent FPGA program upgrades only require downloading the program to the eMMC via the network, and then powering on to configure and load the program, making upgrades convenient.
[0069] The FPGA output rate can be set to 10Gbps / 20Gbps, with PCIe and ARM interfaces for interaction. It supports peripherals such as DDR4 (Double Data Rate 4 Synchronous Dynamic Random-Access Memory) and clock, and outputs HDMI / EDP signals as well as I2C / GPIO. Since the FPGA has a large number of pins, the I / O resources that cannot be fully utilized by the M.2 interface can be pulled out using the FSMC (Flexible Static Memory Controller) connector. This can be used to expand other video signals or power control in the future.
[0070] The VBL module (corresponding to the power supply module) is mounted on the motherboard. The FPGA configures the output power range via a DAC, and the ADC (analog-to-digital converter) collects and reads the voltage and current. It can independently and promptly shut down in case of abnormalities. The M2 board receives all signals from the motherboard, such as EDP / HDMI, I2C, and GPIO. The M2 board is mainly designed with FPD-LINK / GMSL encoding chips (corresponding to encoding units), which can be determined based on the decoding chip used by the backend screen.
[0071] The signal buffer unit (EDP / HDMI Reder) is located between the interface and the encoding unit and is used to buffer and transmit received high-frequency signals. In some examples, when the display signal is a high-frequency signal, the interface module transmits the display signal to the signal buffer unit, and the signal buffer unit sends the received display signal to the encoding unit.
[0072] This disclosed embodiment reduces the system bloat of general-purpose signal generators and lowers the rate of program modification; it saves costs by eliminating the need for general-purpose signal generators, thus reducing procurement costs; the dedicated FPD-LINK / GML signal generator can be used exclusively for automotive screen detection, with a relatively simple function, making later maintenance convenient and reducing maintenance costs; it adopts an M2 interface, allowing the backend FPD-LINK / GML signal board to be arbitrarily replaced, upgraded, and repaired, resulting in a flexible structure; the power supply adopts a modular design, facilitating maintenance and upgrade solutions; its size is much smaller than that of general-purpose signal generators, making it applicable to multiple application scenarios; it is highly adaptable, and can output corresponding signals according to actual application requirements.
[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0074] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A signal generator, characterized in that, The signal generator includes: The motherboard has an interface module for outputting display signals, control signals, and power signals. The sub-board, connected to the interface module, is used to receive the control signal, the display signal, and the power signal, and to output the encoded signal and the power signal.
2. The signal generator according to claim 1, characterized in that, The motherboard includes an ARM module and an FPGA module, and the display signals include HDMI signals and / or EDP signals.
3. The signal generator according to claim 2, characterized in that, The FPGA module is electrically connected to the ARM module. The FPGA module receives image parameter instructions transmitted by the ARM module and outputs the display signal and the control signal.
4. The signal generator according to claim 2, characterized in that, The motherboard includes a power module, which is electrically connected to the FPGA module via a digital-to-analog converter module. The interface module is electrically connected to the power module. The power module is used to receive the power configuration signal output by the FPGA module and output a power signal matching the power configuration signal to the interface module.
5. The signal generator according to claim 4, characterized in that, The motherboard also includes an analog-to-digital converter module, which is electrically connected to the power supply module and the FPGA module respectively. The analog-to-digital converter module is used to receive the circuit parameter information of the power supply module and output the circuit parameter signal corresponding to the circuit parameter information to the FPGA module.
6. The signal generator according to claim 1, characterized in that, The subboard includes an encoding unit, which is used to receive the control signal and the display signal, and output the encoded signal.
7. The signal generator according to claim 6, characterized in that, The encoding unit includes an FPD-LINK encoding chip and / or a GMSL encoding chip.
8. The signal generator according to claim 6, characterized in that, The sub-board also includes a signal buffer unit electrically connected to the encoding unit, used to receive the display signal output by the interface module and send the display signal to the encoding unit.
9. The signal generator according to claim 6, characterized in that, The sub-board also includes a display output interface, which is electrically connected to the encoding unit and is used to receive and output the encoded signal.
10. The signal generator according to claim 1, characterized in that, The subboard also includes a power output interface for receiving and outputting power signals from the interface module.