Interface system based on a heterogeneous computing platform

Abstract

The utility model relates to interface technical field especially, it relates to an interface system based on heterogeneous computing platform, including ARM treater unit, programmable logic unit and external extension interface, ARM treater unit is connected with programmable logic unit, ARM treater unit manages external extension interface through peripheral controller, and external extension interface includes 5G interface unit, WIFI interface unit, USB3.0 interface unit and TYPEC serial unit, 5G interface unit is used for wireless wide area network access, and WIFI interface unit is used for wireless LAN access, and USB3.0 interface unit is used for connecting high -speed external device, and TYPEC serial unit is the interface that possesses power supply and command line interaction. The utility model solves the problem of traditional heterogeneous platform single interface, wiring complex, bus competition, data delay.

Description

Technical Field

[0001] This utility model relates to the field of interface technology, and in particular to an interface system based on a heterogeneous computing platform. Background Technology

[0002] With the rapid development of fields such as artificial intelligence, machine vision, industrial automation, and high-speed communication, unprecedented demands have been placed on the computing power, real-time performance, energy efficiency, and data throughput of embedded systems. Traditional single-architecture processors (such as those relying solely on CPUs) are no longer sufficient to meet the needs of these complex application scenarios. Against this backdrop, heterogeneous computing platforms have emerged and become the mainstream solution. These platforms integrate processors with different architectures (such as general-purpose CPUs, graphics processing units (GPUs), and neural network processing units (NPUs) with programmable logic devices (such as field-programmable gate arrays (FPGAs), fully leveraging the advantages of each—the CPU handles complex logic and control, while the FPGA enables low-latency, high-throughput hardware acceleration—thus achieving significant breakthroughs in performance, flexibility, and energy efficiency.

[0003] The core of a heterogeneous computing platform lies in the efficient collaboration between its various computing units, which heavily relies on a powerful, flexible, and high-speed interface system. This system is responsible for establishing data paths between the processor, FPGA, memory, and various peripherals, enabling task distribution, data transmission, and result feedback. Currently, processors and programmable logic devices connect via GPIO ports, I2C, MIPI 4LANE, and PCIe interfaces, and with peripherals via Ethernet, USB 2.0, and RS485 interfaces. However, this approach has the following limitations:

[0004] 1) Lacks wireless LAN or WAN access capability, requiring the configuration of an additional interface to achieve wireless data transmission;

[0005] 2) Unable to connect to high-speed peripherals, such as high-speed USB flash drives or USB 3.0 cameras;

[0006] 3) Log output and command line interaction are mainly achieved through the UART serial port, which is implemented through the Type-C interface. However, the current heterogeneous computing platform lacks the Type-C interface.

[0007] 4) Interfaces and debug serial ports typically use separate controllers or bridge chips connected to the main processor, resulting in complex circuitry, difficult PCB layout, and poor power consumption control. Furthermore, the lack of coordination mechanisms between interfaces can easily lead to bus contention and data latency in multi-task concurrent scenarios. Utility Model Content

[0008] This invention provides an interface system based on a heterogeneous computing platform, integrating high-speed interfaces such as 5G, Wi-Fi, and USB 3.0, which solves the problems of single interface, complex wiring, bus contention, and data latency in traditional heterogeneous platforms.

[0009] To achieve the purpose of this utility model, the technical solution adopted is: an interface system based on a heterogeneous computing platform, including an ARM processor unit, a programmable logic unit, and an external expansion interface. The ARM processor unit is connected to the programmable logic unit. The ARM processor unit manages the external expansion interface through a peripheral controller. The external expansion interface includes a 5G interface unit, a WIFI interface unit, a USB 3.0 interface unit, and a TYPEC serial port unit. The 5G interface unit is used for wireless wide area network access, the WIFI interface unit is used for wireless local area network access, the USB 3.0 interface unit is used to connect high-speed external devices, and the TYPEC serial port unit is an interface that combines power supply and command line interaction.

[0010] As an optimized solution of this utility model, the ARM processor unit is the RK3588 chip U1.

[0011] As an optimized solution of this utility model, the interface system based on the heterogeneous computing platform also includes a USB conversion chip U20. The 16th pin of the USB conversion chip U20 is connected to AL7 of the RK3588 chip U1, and the 15th pin of the USB conversion chip U20 is connected to AM7 of the RK3588 chip U1.

[0012] As an optimized solution of this utility model, the 5G interface unit includes a 5G module U26, capacitors C255, C256, C257, C258, resistors R269 and R270, a transistor Q30, resistors R266 and R267. Pin 29 of the 5G module U26 is connected to pin J30 of the RK3588 chip U1 via capacitor C255. Pin 31 of the 5G module U26 is connected to pin J31 of the RK3588 chip U1 via capacitor C256. Pin 35 of the 5G module U26 is connected to pin H29 of the RK3588 chip U1 via capacitor C257. Pin 37 of the 5G module U26 is connected to pin Q270 of the RK3588 chip U1 via capacitor C258. Pin H30 is connected. Pin 6 of 5G module U26 is connected to pin AM29 of RK3588 chip U1 through resistor R266. Pin 8 of 5G module U26 is connected to pin AE28 of RK3588 chip U1 through resistor R267. Pin 67 of 5G module U26 is connected to the collector of transistor Q30. The base of transistor Q30 is connected to the emitter of transistor Q30 through resistor R270. The base of transistor Q30 is connected to pin AB28 of RK3588 chip U1 through resistor R269. Pin 7 of 5G module U26 is connected to pin 7 of USB conversion chip U20. Pin 9 of 5G module U26 is connected to pin 6 of USB conversion chip U20.

[0013] As an optimized solution of this utility model, the WIFI interface unit includes a WIFI module U18, a resistor R166 and a resistor R167. The 6th pin of the WIFI module U18 is connected to the 11th pin of the USB conversion chip U20 through the resistor R166, and the 7th pin of the WIFI module U18 is connected to the 10th pin of the USB conversion chip U20 through the resistor R167.

[0014] As an optimized solution of this utility model, the USB 3.0 interface unit includes a USB connector J6. Pin 9 of the USB connector J6 is grounded through trigger diode ED7 and connected to pin AP9 of the RK3588 chip U1. Pin 8 of the USB connector J6 is grounded through trigger diode ED8 and connected to pin AN9 of the RK3588 chip U1. Pin 6 of the USB connector J6 is grounded through trigger diode ED9 and connected to pin AN8 of the RK3588 chip U1. Pin 5 of the USB connector J6 is grounded through trigger diode ED10 and connected to pin AP8 of the RK3588 chip U1. Pin 3 of the USB connector J6 is grounded through trigger diode ED12 and connected to pin AK9 of the RK3588 chip U1. Pin 2 of the USB connector J6 is grounded through trigger diode ED11 and connected to pin AL9 of the RK3588 chip U1.

[0015] As an optimized solution of this utility model, the TYPEC serial port unit includes a USB Type-C controller U10 and a Type-C connector J7. Pin 6 of the USB Type-C controller U10 is connected to pin W31 of the RK3588 chip U1, pin 7 of the USB Type-C controller U10 is connected to pin V31 of the RK3588 chip U1, pin 5 of the USB Type-C controller U10 is connected to pin U33 of the RK3588 chip U1, and pins 10 and 11 of the USB Type-C controller U10 are both connected to pin A5 of the Type-C connector J7. Pins 1 and 14 of the PE-C controller U10 are both connected to pin B5 of the Type-C connector J7. Pin A8 of the Type-C connector J7 is connected to pin AL27 of the RK3588 chip U1 via resistor R54. Pin A8 of the Type-C connector J7 is connected to pin AL15 of the RK3588 chip U1 via capacitor C92. Pin B8 of the Type-C connector J7 is connected to pin AM15 of the RK3588 chip U1 via capacitor C93. Pin B8 of the Type-C connector J7 is connected to pin AM27 of the RK3588 chip U1 via resistor R55. Pins A7 and B7 of connector J7 are connected to pin AM12 of RK3588 chip U1 via resistor R58. Pins A6 and B6 of Type-C connector J7 are connected to pin AL27 of RK3588 chip U1 via resistor R59. Pin A3 of Type-C connector J7 is connected to pin AN14 of RK3588 chip U1 via capacitor C94. Pin A2 of Type-C connector J7 is connected to pin AP14 of RK3588 chip U1 via capacitor C95. Pin B10 of Type-C connector J7 is connected to pin AP13 of RK3588 chip U1 via resistor R60. Pin B11 of Type-C connector J7 is connected to pin AN13 of RK3588 chip U1 via resistor R61. Pin B3 of Type-C connector J7 is connected to pin AN16 of RK3588 chip U1 via capacitor C96. Pin B2 of Type-C connector J7 is connected to pin AP16 of RK3588 chip U1 via capacitor C97. Pin A10 of Type-C connector J7 is connected to pin AP15 of RK3588 chip U1 via resistor R62. Pin A11 of Type-C connector J7 is connected to pin AN15 of RK3588 chip U1 via resistor R63.

[0016] This utility model has the following positive effects: 1) By integrating a 5G interface unit and a Wi-Fi interface unit, the system simultaneously possesses the ability to remotely access a wide area network and interconnect a local area network at high speed, meeting the flexible networking needs of scenarios such as edge computing and remote monitoring; it is also equipped with a USB 3.0 interface unit, supporting plug-and-play functionality for peripherals such as high-speed USB flash drives and 4K cameras, significantly improving data throughput and system scalability, and solving the problem of traditional heterogeneous platforms having a single interface and relying on external expansion;

[0017] 2) Both the 5G module and the Wi-Fi module of this utility model are connected to the RK3588 main controller via a USB conversion chip, avoiding the waste of pin resources and complex PCB routing caused by independently connecting them to the main processor. This design realizes centralized scheduling and power management of communication peripherals, simplifies the hardware architecture, improves the reliability and maintainability of the system, and is conducive to the development of miniaturized terminal devices;

[0018] 3) The TYPEC serial port unit not only supports command line interaction and log output, but also enables device power supply through a Type-C connector. Power supply, debugging and data communication can be completed with only one Type-C cable, which greatly simplifies the development and debugging process, avoids the confusion caused by multiple cable connections, and improves the ease of use and integration of the product. Attached Figure Description

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0020] Figure 1 This is a schematic diagram of the principle of this utility model;

[0021] Figure 2 This is a schematic diagram of the USB HUB of this utility model;

[0022] Figure 3 This is the circuit schematic diagram of the USB HUB of this utility model;

[0023] Figure 4 This is the circuit schematic diagram of the 5G interface unit of this utility model;

[0024] Figure 5 This is a circuit diagram of the WIFI interface unit of this utility model;

[0025] Figure 6 This is a circuit schematic diagram of the USB 3.0 interface unit of this utility model;

[0026] Figure 7 This is the circuit schematic diagram of the USB Type-C controller of this utility model;

[0027] Figure 8This is the original circuit diagram of the Type-C connector of this utility model. Detailed Implementation

[0028] The technical solutions described below in conjunction with the embodiments of this utility model will be clearly and completely described. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0029] It should be noted that, where there is no conflict, the features in the embodiments of this utility model can be combined with each other.

[0030] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0031] like Figure 1 As shown, this utility model discloses an interface system based on a heterogeneous computing platform, including an ARM processor unit, a programmable logic unit (PLU), and external expansion interfaces. The ARM processor unit is connected to the PLU, and the ARM processor unit manages the external expansion interfaces through a peripheral controller. The external expansion interfaces include a 5G interface unit, a WIFI interface unit, a USB 3.0 interface unit, and a TYPEC serial port unit. The 5G interface unit is used for wireless wide area network (WAN) access, the WIFI interface unit is used for wireless local area network (LAN) access, the USB 3.0 interface unit is used to connect high-speed external devices, and the TYPEC serial port unit is an interface that combines power supply and command-line interaction. The ARM processor unit is an RK3588 chip U1, which is based on a quad-core ARM Cortex-A76 processor with a clock speed of 1.6GHz in normal mode and 2.0GHz in overclocked mode. The PLU is an XCKU5P-2FFVB676I, featuring 475K logic cells (CLBs), 217K lookup tables (LUTs), and 434K flip-flops. The RK3588J connects to the FPGA via MIPI 4LANE, PCIe 30x4, I2C, and GPIO. It has undergone professional PCB layout and high / low temperature testing, demonstrating stability and reliability to meet the requirements of various industrial applications. External expansion interfaces include 2 ETH Gigabit Ethernet ports, 3 USB 2.0 ports, 1 USB 3.0 port, 1 RS485 port, 2 MIPI CSI 4LANE ports, 3 MIPI CSI 4LANE ports, 1 audio input and 1 audio output, 2 SATA ports, 1 5G port, 1 Wi-Fi port, 1 HDMI 4K60 input, 2 HDMI 4K60 outputs, 2 Type-C serial ports, 1 FMC-HPC port, and 1 100G optical port, facilitating rapid technical research and development.

[0032] like Figure 2 As shown, one signal is drawn from the RK3588 chip, which is then converted into four signals by the USB converter chip U20. The USB converter chip U20 is model FE1.1S-BSOP28BCN, and these signals are connected to the WIFI / BT, USB 2.0 HOST, and 5G interfaces, respectively. Figure 3 As shown, pin 16 of the USB converter chip U20 is connected to pin AL7 of the RK3588 chip U1, and pin 15 of the USB converter chip U20 is connected to pin AM7 of the RK3588 chip U1. The USB converter chip U20 is used for unified connection of peripherals such as 5G and Wi-Fi. It achieves convergence and conversion of multiple high-speed interfaces through a single intermediary chip, improving integration. Through the architecture of RK3588 (integrated CPU / GPU / NPU) + FPGA + multi-functional interface expansion, it solves the problem of whether or not there are wireless and high-speed interfaces. Furthermore, through a unified USB Hub and master control scheduling, it achieves efficient integration and collaborative control of interface resources, resolving issues of bus contention and data latency.

[0033] like Figure 4As shown, the 5G interface unit includes a 5G module U26, capacitors C255, C256, C257, and C258, resistors R269 and R270, a transistor Q30, resistors R266 and R267. Pin 29 of the 5G module U26 is connected to pin J30 of the RK3588 chip U1 via capacitor C255. Pin 31 of the 5G module U26 is connected to pin J31 of the RK3588 chip U1 via capacitor C256. Pin 35 of the 5G module U26 is connected to pin H29 of the RK3588 chip U1 via capacitor C257. Pin 37 of the 5G module U26 is connected to pin H30 of the RK3588 chip U1 via capacitor C258. The 5G module U26 is connected via resistor R266 to pin AM29 of the RK3588 chip U1, pin 8 to pin AE28 of the RK3588 chip U1 via resistor R267, pin 67 to the collector of transistor Q30, the base of transistor Q30 to the emitter of transistor Q30 via resistor R270, and the base of transistor Q30 to pin AB28 of the RK3588 chip U1 via resistor R269. Pin 7 of the 5G module U26 is connected to pin 7 of the USB conversion chip U20, and pin 9 of the 5G module U26 is connected to pin 6 of the USB conversion chip U20. The interface system based on the heterogeneous computing platform has a 4G / 5G M.2 interface, and the 5G module U26 uses Quectel's EM05CEFC-128-SGAS module. The 5G module's enable control (via transistor Q30 and RK3588's AB28 pin) gives the system active power and status management capabilities for the wireless module, which is something traditional distributed interfaces lack.

[0034] like Figure 5 As shown, the WIFI interface unit includes a WIFI module U18, resistors R166 and R167. Pin 6 of the WIFI module U18 is connected to pin 11 of the USB conversion chip U20 through resistor R166, and pin 7 of the WIFI module U18 is connected to pin 10 of the USB conversion chip U20 through resistor R167. The WIFI module U18 uses SKI.WB800D80U.2 and has an external RF coaxial interface antenna.

[0035] like Figure 6As shown, the USB 3.0 interface unit includes a USB connector J6. Pin 9 of the USB connector J6 is grounded via trigger diode ED7 and is connected to pin AP9 of the RK3588 chip U1. Pin 8 of the USB connector J6 is grounded via trigger diode ED8 and is connected to pin AN9 of the RK3588 chip U1. Pin 6 of the USB connector J6 is grounded via trigger diode ED9 and is connected to pin AN8 of the RK3588 chip U1. Pin 5 is grounded through trigger diode ED10. Pin 5 of USB connector J6 is connected to pin AP8 of RK3588 chip U1. Pin 3 of USB connector J6 is grounded through trigger diode ED12. Pin 3 of USB connector J6 is connected to pin AK9 of RK3588 chip U1. Pin 2 of USB connector J6 is grounded through trigger diode ED11. Pin 2 of USB connector J6 is connected to pin AL9 of RK3588 chip U1. The USB 3.0 interface unit supports one USB 3.0 port and can support connection to USB devices such as storage devices and external hard drives.

[0036] like Figure 7 and Figure 8As shown, the TYPE-C serial port unit includes a USB Type-C controller U10 and a Type-C connector J7. Pin 6 of the USB Type-C controller U10 is connected to pin W31 of the RK3588 chip U1; pin 7 of the USB Type-C controller U10 is connected to pin V31 of the RK3588 chip U1; pin 5 of the USB Type-C controller U10 is connected to pin U33 of the RK3588 chip U1; and pins 10 and 11 of the USB Type-C controller U10 are both connected to pin A5 of the Type-C connector J7. Pins 1 and 14 of U10 are both connected to pin B5 of Type-C connector J7. Pin A8 of Type-C connector J7 is connected to pin AL27 of RK3588 chip U1 via resistor R54. Pin A8 of Type-C connector J7 is connected to pin AL15 of RK3588 chip U1 via capacitor C92. Pin B8 of Type-C connector J7 is connected to pin AM15 of RK3588 chip U1 via capacitor C93. Pin B8 of Type-C connector J7 is connected to pin AM27 of RK3588 chip U1 via resistor R55. Pins A7 and B7 are both connected to pin AM12 of RK3588 chip U1 via resistor R58. Pins A6 and B6 of Type-C connector J7 are both connected to pin AL27 of RK3588 chip U1 via resistor R59. Pin A3 of Type-C connector J7 is connected to pin AN14 of RK3588 chip U1 via capacitor C94. Pin A2 of Type-C connector J7 is connected to pin AP14 of RK3588 chip U1 via capacitor C95. Pin B10 of Type-C connector J7 is connected to pin AP13 of RK3588 chip U1 via resistor R60. Pin B11 of the e-C connector J7 is connected to pin AN13 of the RK3588 chip U1 via resistor R61. Pin B3 of the Type-C connector J7 is connected to pin AN16 of the RK3588 chip U1 via capacitor C96. Pin B2 of the Type-C connector J7 is connected to pin AP16 of the RK3588 chip U1 via capacitor C97. Pin A10 of the Type-C connector J7 is connected to pin AP15 of the RK3588 chip U1 via resistor R62. Pin A11 of the Type-C connector J7 is connected to pin AN15 of the RK3588 chip U1 via resistor R63. Pins A4, A9, B4, and B9 of the Type-C connector J7 are VBUS pins used for power transmission. When an external power source (such as a Type-C charger or PC) is connected to J7 via a Type-C cable, the VBUS voltage (typically 5V) can directly power the entire heterogeneous computing system.

[0037] Example:

[0038] ARM Processor Unit: The RK3588 chip, based on the quad-core ARM Cortex-A76 architecture, supports a clock speed of 1.6GHz in normal mode and 2.0GHz in overclocking mode, providing powerful computing capabilities.

[0039] Programmable logic unit: The FPGA selected is the Xilinx XCKU5P-2FFVB676I model, which has 475K logic units, 217K lookup tables and 434K flip-flops, and can realize highly customized hardware acceleration functions.

[0040] The U20 USB converter chip, model FE1.1S-BSOP28BCN, is used to convert one signal from the RK3588 into four signals, which are respectively connected to the WIFI / BT module, the USB2.0 HOST interface, and the 5G module, improving the system's integration and interface flexibility.

[0041] Wireless access capability: Through the 5G interface unit and the Wi-Fi interface unit, the system realizes wireless access capability for wide area network and local area network, meeting the needs of remote data transmission and local high-speed interconnection.

[0042] High-speed peripheral connectivity: The USB 3.0 interface unit supports the connection of high-speed external devices, such as storage devices or high-definition cameras, ensuring high-bandwidth data transmission efficiency.

[0043] 5G module enable control: By connecting the transistor Q30 and resistor network (R269, R270) to the AB28 pin of RK3588, active power management of the 5G module is realized. The module can be dynamically turned on or off according to actual needs to optimize power consumption performance.

[0044] The Type-C serial port unit not only provides a command-line interaction channel but also serves as a power supply, embodying the design concept of multi-purpose use in a single cable, simplifying the development and debugging process, and improving the user experience.

[0045] This interface system, through the effective integration of the aforementioned components, achieves efficient management and scheduling of multiple interfaces within a unified framework. It not only overcomes the limitations of traditional heterogeneous computing platforms in wireless communication and high-speed peripheral connections, but also, through professional PCB layout design and rigorous high and low temperature testing, ensures its stability and reliability in various industrial environments. This integrated design concept is of great significance for promoting the development of fields such as image recognition, medical imaging diagnosis, the Internet of Things, intelligent robots, and intelligent transportation.

[0046] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above descriptions are merely specific embodiments of this utility model and are not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. An interface system based on a heterogeneous computing platform, characterized in that: It includes an ARM processor unit, a programmable logic unit (PLU), and external expansion interfaces. The ARM processor unit is connected to the PLU. The ARM processor unit manages the external expansion interfaces through a peripheral controller. The external expansion interfaces include a 5G interface unit, a WIFI interface unit, a USB 3.0 interface unit, and a TYPEC serial port unit. The 5G interface unit is used for wireless wide area network (WAN) access, the WIFI interface unit is used for wireless local area network (LAN) access, the USB 3.0 interface unit is used to connect high-speed external devices, and the TYPEC serial port unit is an interface that combines power supply and command-line interaction.

2. The interface system based on a heterogeneous computing platform according to claim 1, characterized in that: The ARM processor unit is the RK3588 chip U1.

3. The interface system based on a heterogeneous computing platform according to claim 2, characterized in that: The interface system based on the heterogeneous computing platform also includes a USB conversion chip U20. Pin 16 of the USB conversion chip U20 is connected to AL7 of the RK3588 chip U1, and pin 15 of the USB conversion chip U20 is connected to AM7 of the RK3588 chip U1.

4. The interface system based on a heterogeneous computing platform according to claim 3, characterized in that: The 5G interface unit includes a 5G module U26, capacitors C255, C256, C257, and C258, resistors R269 and R270, a transistor Q30, resistors R266 and R267. Pin 29 of the 5G module U26 is connected to pin J30 of the RK3588 chip U1 via capacitor C255. Pin 31 of the 5G module U26 is connected to pin J31 of the RK3588 chip U1 via capacitor C256. Pin 35 of the 5G module U26 is connected to pin H29 of the RK3588 chip U1 via capacitor C257. Pin 37 of the 5G module U26 is connected to pin H30 of the RK3588 chip U1 via capacitor C258. Pin 6 of 5G module U26 is connected to pin AM29 of RK3588 chip U1 via resistor R266. Pin 8 of 5G module U26 is connected to pin AE28 of RK3588 chip U1 via resistor R267. Pin 67 of 5G module U26 is connected to the collector of transistor Q30. The base of transistor Q30 is connected to the emitter of transistor Q30 via resistor R270. The base of transistor Q30 is connected to pin AB28 of RK3588 chip U1 via resistor R269. Pin 7 of 5G module U26 is connected to pin 7 of USB conversion chip U20. Pin 9 of 5G module U26 is connected to pin 6 of USB conversion chip U20.

5. The interface system based on a heterogeneous computing platform according to claim 4, characterized in that: The WIFI interface unit includes a WIFI module U18, resistors R166 and R167. Pin 6 of the WIFI module U18 is connected to pin 11 of the USB conversion chip U20 through resistor R166, and pin 7 of the WIFI module U18 is connected to pin 10 of the USB conversion chip U20 through resistor R167.

6. The interface system based on a heterogeneous computing platform according to claim 5, characterized in that: The USB 3.0 interface unit includes a USB connector J6. Pin 9 of USB connector J6 is grounded through trigger diode ED7 and is connected to pin AP9 of RK3588 chip U1. Pin 8 of USB connector J6 is grounded through trigger diode ED8 and is connected to pin AN9 of RK3588 chip U1. Pin 6 of USB connector J6 is grounded through trigger diode ED9 and is connected to pin AN8 of RK3588 chip U1. Pin 5 of USB connector J6 is grounded through trigger diode ED10 and is connected to pin AP8 of RK3588 chip U1. Pin 3 of USB connector J6 is grounded through trigger diode ED12 and is connected to pin AK9 of RK3588 chip U1. Pin 2 of USB connector J6 is grounded through trigger diode ED11 and is connected to pin AL9 of RK3588 chip U1.

7. The interface system based on a heterogeneous computing platform according to claim 6, characterized in that: The TYPE-C serial port unit includes a USB Type-C controller U10 and a Type-C connector J7. Pin 6 of the USB Type-C controller U10 is connected to pin W31 of the RK3588 chip U1; pin 7 of the USB Type-C controller U10 is connected to pin V31 of the RK3588 chip U1; pin 5 of the USB Type-C controller U10 is connected to pin U33 of the RK3588 chip U1; and pins 10 and 11 of the USB Type-C controller U10 are both connected to pin A5 of the Type-C connector J7. Pins 1 and 14 are both connected to pin B5 of Type-C connector J7. Pin A8 of Type-C connector J7 is connected to pin AL27 of RK3588 chip U1 through resistor R54. Pin A8 of Type-C connector J7 is connected to pin AL15 of RK3588 chip U1 through capacitor C92. Pin B8 of Type-C connector J7 is connected to pin AM15 of RK3588 chip U1 through capacitor C93. Pin B8 of Type-C connector J7 is connected to pin AM27 of RK3588 chip U1 through resistor R55. Pin A7 of Type-C connector J7... Pins B7 and B7 are connected to pin AM12 of RK3588 chip U1 via resistor R58. Pins A6 and B6 of Type-C connector J7 are connected to pin AL27 of RK3588 chip U1 via resistor R59. Pin A3 of Type-C connector J7 is connected to pin AN14 of RK3588 chip U1 via capacitor C94. Pin A2 of Type-C connector J7 is connected to pin AP14 of RK3588 chip U1 via capacitor C95. Pin B10 of Type-C connector J7 is connected to pin AP13 of RK3588 chip U1 via resistor R60. The B11 pin of Type-C connector J7 is connected to the AN13 pin of RK3588 chip U1 through resistor R61. The B3 pin of Type-C connector J7 is connected to the AN16 pin of RK3588 chip U1 through capacitor C96. The B2 pin of Type-C connector J7 is connected to the AP16 pin of RK3588 chip U1 through capacitor C97. The A10 pin of Type-C connector J7 is connected to the AP15 pin of RK3588 chip U1 through resistor R62. The A11 pin of Type-C connector J7 is connected to the AN15 pin of RK3588 chip U1 through resistor R63.

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