A radio frequency switch chip
By setting non-conductive dielectric isolation trenches on the interconnect layer and packaging substrate of the RF switch chip, the problem of insufficient isolation of multi-channel RF switch chips is solved, achieving high isolation and low interference effect within a limited area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI ARCHIWAVE MICROELECTRONICS CO LTD
- Filing Date
- 2025-08-12
- Publication Date
- 2026-07-21
AI Technical Summary
In Massive MIMO systems, it is difficult to improve the isolation of multi-channel RF switch chips within a limited chip area, resulting in severe interference between adjacent channels. Existing methods, such as increasing the number of ground bumps, are limited and cannot meet the high isolation requirements.
By setting a first isolation trench filled with non-conductive dielectric on the interconnect layer of the RF switch chip, the common ground return path between the ground points of adjacent RF channels is cut off, and a third isolation trench is set on the package substrate to further improve the isolation.
It effectively improves the isolation between adjacent RF channels, reduces interference, meets high isolation requirements, and adapts to the increase in chip integration.
Smart Images
Figure CN224536511U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of radio frequency chips, and in particular to a radio frequency switch chip. Background Technology
[0002] As a key component of the RF front-end in modern communication systems, RF switches play a special role in Massive Multiple-Input Multiple-Output (MIMO) system architectures. For the feedback link design of Digital Predistortion (DPD) systems, high-isolation RF switches are required to construct a multi-channel sampling system. First, the nonlinear RF signal output from the power amplifier (PA) is extracted via a directional coupler, digitized by an analog-to-digital converter (ADC), and transmitted to a digital signal processor (DSP). The DSP generates a predistorted waveform in real-time, which is then converted into an analog signal by a digital-to-analog converter (DAC) and finally injected into the power amplifier input to compensate for its nonlinear distortion. Because Massive MIMO systems employ a multi-channel power amplifier parallel transmission mechanism, when the DPD system samples each channel alternately, crosstalk can occur between adjacent channels through common ground, spatial radiation, and other means. In this case, the isolation of the RF switch directly determines the purity of the feedback signal—high isolation effectively suppresses leakage interference from non-sampled channels. Switching isolation (in dB) is defined as the absolute logarithm of the ratio of the incident voltage to the output voltage across the signal transmission path when the signal is off. Under normal circumstances, switching isolation is typically between 20 and 40 dB, with 40-60 dB considered high isolation (signal transmission is only 1 / 100th of its original value). Switching isolation > 60 dB (signal transmission is 1 / 1000th of its original value) is considered ultra-high isolation.
[0003] Multi-channel RF switches typically use single-pole four-throw (SP4T) switches. To improve isolation, three high-isolation single-pole double-throw (SPDT) switches can be used instead of SP4T. However, with increasing channel counts and higher chip integration requirements, using multiple high-isolation SPDTs to replace multi-channel RF switches is no longer the preferred solution. Currently, the method to improve inter-channel isolation is to increase the number of ground bumps (GND bumps) between the die and the package substrate. However, as chip integration becomes higher, die area decreases, and the number of channels increases, the number of ground bumps that can be placed within a limited space becomes restricted. Therefore, how to achieve high-isolation multi-channel RF switch chips is a pressing technical problem that needs to be solved. Utility Model Content
[0004] To address the above technical issues, this application provides an RF switch chip that can improve the isolation between RF channels of a multi-channel RF switch by optimizing the distribution of ground bumps and setting isolation slots within a limited chip area.
[0005] This application discloses a radio frequency (RF) switch chip, comprising at least two adjacent RF channels. Each RF channel includes a series-parallel switch structure, comprising: N series-connected first switches, connected sequentially between the RF input and RF output terminals of the RF channel, where N is an integer ≥ 1; and M parallel-connected second switches, each connected between the RF channel and a standard ground, where M is an integer ≥ 1. Each second switch has a grounding point for connection to the standard ground. The surface of the RF switch chip has grounding bumps, and each grounding point is electrically connected to the standard ground through its corresponding grounding bump. The RF switch chip further comprises: a device layer and an interconnect layer on the device layer. A first isolation trench is provided on the interconnect layer, the first isolation trench being used to isolate the grounding point that has the greatest impact on the isolation between adjacent RF channels, and the first isolation trench is filled with a non-conductive dielectric.
[0006] According to the radio frequency switch chip of this application, the first switch and the second switch include transistors, the transistors being located in the device layer; the interconnect layer includes: an interconnect line and a conductive plug connected to the interconnect line, the first switch and the second switch being electrically connected through the interconnect line and the conductive plug; the ground point includes a conductive plug and an interconnect line located in the interconnect layer, or a conductive plug and an interconnect line.
[0007] By setting a first isolation trench filled with a non-conductive medium between the last-stage grounding points of two adjacent RF channels, the common ground return path between the two grounding points can be cut off, so that the ground return paths of the two adjacent RF channels at the last-stage grounding points are isolated from each other, thereby improving the isolation between adjacent RF channels and reducing the interference between adjacent RF channels.
[0008] According to the RF switch chip of this application, the grounding point that has the greatest impact on the inter-channel isolation includes: the grounding point corresponding to the last stage second switch of two adjacent RF channels along the RF transmission direction.
[0009] According to the RF switch chip of this application, the grounding point corresponding to the last stage second switch has at least one grounding bump that is closest to it; the first isolation groove is used to isolate the grounding bumps of the two adjacent RF channels that are closest to the grounding point corresponding to the last stage second switch.
[0010] According to the RF switch chip of this application, one end of the first isolation groove extends to the grounding bump closest to the grounding point corresponding to the last stage second switch.
[0011] According to the RF switch chip of this application, the first isolation groove is a straight line or a broken line in the direction perpendicular to the chip surface.
[0012] According to the RF switch chip of this application, the first isolation trench penetrates the interconnect layer of the RF switch in a direction perpendicular to the chip surface.
[0013] According to the RF switch chip of this application, the two ground bumps adjacent to the ground point corresponding to the last stage second switch of the first RF channel are respectively a first bump and a second bump; the two ground bumps adjacent to the ground point corresponding to the last stage second switch of the second RF channel are respectively a third bump and a fourth bump; the first bump and the third bump are located on the first side of the ground point corresponding to the last stage second switch of two adjacent RF channels; the second bump and the fourth bump are located on the second side of the ground point corresponding to the last stage second switch of two adjacent RF channels; the end of the first side of the first isolation groove extends at least to the line connecting the edges of the first side of the first bump and the third bump, and the end of the second side of the first isolation groove extends at least to the line connecting the edges of the second side of the second bump and the fourth bump.
[0014] By setting the length of the first isolation groove to extend beyond the positions of the two grounding bumps adjacent to the grounding point at both ends, the common ground return path between the two last-stage grounding points can be better cut off, thereby further improving the isolation between adjacent RF channels and reducing interference between adjacent RF channels.
[0015] According to the RF switch chip of this application, the grounding bump on the first side of the grounding point corresponding to the first-level second switch of the first RF channel is a fifth bump, and the grounding bump on the first side of the grounding point corresponding to the first-level second switch of the second RF channel is a sixth bump. The end of the first side of the first isolation groove extends at least to the line connecting the edge of the first side of the fifth bump and the sixth bump.
[0016] By setting the length of the first isolation slot to isolate the grounding points corresponding to all the second switches of two adjacent radio frequency channels, the isolation between adjacent radio frequency channels can be further improved and the interference between adjacent radio frequency channels can be reduced.
[0017] According to the RF switch chip of this application, at least one second isolation trench is further provided on the interconnect layer. The second isolation trench is filled with a non-conductive dielectric. The extension direction of the first isolation trench is a first direction, and the extension direction of the second isolation trench is a second direction. The first direction and the second direction intersect. The second isolation trench is used to isolate the current path between the grounding point with the greatest influence of inter-channel isolation and the grounding point with the least influence of inter-channel isolation.
[0018] According to the RF switch chip of this application, the grounding bump on the second side of the grounding point corresponding to the second switch of the second-to-last level in the first RF channel is the seventh bump, and the grounding bump on the second side of the grounding point corresponding to the second switch of the second-to-last level in the second RF channel is the eighth bump. The second isolation groove is located on the second side of the seventh bump and the eighth bump, and on the first side of the third bump and the fourth bump.
[0019] By setting a second isolation slot that intersects with the first isolation slot, the last-level grounding point of each RF channel is isolated from the penultimate-level grounding point, cutting off the common ground return path between them. This can further improve the isolation between adjacent RF channels and reduce interference between adjacent RF channels.
[0020] According to the RF switch chip of this application, multiple parallel second isolation slots are provided on the interconnect layer, which are respectively used to isolate the grounding points corresponding to two adjacent second switches of the first RF channel and to isolate the grounding points corresponding to two adjacent second switches of the second RF channel.
[0021] Furthermore, setting up multiple second isolation slots to isolate the grounding points of adjacent stages of each RF channel can further improve the isolation between adjacent RF channels and reduce interference between adjacent RF channels.
[0022] According to the radio frequency switch chip of this application, the radio frequency switch chip is packaged on a substrate, the substrate includes X metal layers, where X is an integer ≥2, the metal layers are electrically connected through vias, and a third isolation trench corresponding to the first isolation trench is provided on the first metal layer, the third isolation trench being filled with a non-conductive dielectric.
[0023] According to the radio frequency switch chip of this application, a third isolation trench corresponding to the first isolation trench is respectively provided on the first metal layer to the (X-1)th metal layer.
[0024] According to the RF switch chip of this application, the lateral dimension of the third isolation trench is larger than that of the first isolation trench, and the range of the third isolation trench in the vertical chip direction can completely cover the range of the first isolation trench.
[0025] By incorporating a third isolation trench on the substrate metal layer of the packaging substrate, return current paths that degrade isolation can be separated, thereby further improving the isolation between adjacent RF channels and reducing interference between them. Furthermore, the packaging substrate is larger than a bare chip die and has simpler wiring, providing more space for the isolation trench. Wider and longer isolation trenches further ensure effective isolation. Attached Figure Description
[0026] Figure 1 This is a simplified circuit diagram of the RF switch chip;
[0027] Figure 2 This is a 3D schematic diagram of an RF switch chip;
[0028] Figure 3 This is a simulation diagram illustrating the isolation between the grounding point of an RF switch chip and standard ground under five scenarios: ideal grounding, non-ideal grounding, and standard grounding.
[0029] Figure 4 A cross-sectional schematic diagram of a portion of an RF switch chip;
[0030] Figure 5 A cross-sectional schematic diagram of the functional area of an RF switch chip;
[0031] Figure 6 This is a three-dimensional schematic diagram of a portion of the structure of the radio frequency switch chip involved in this application;
[0032] Figure 7 This is a three-dimensional disassembled schematic diagram of a portion of the structure of the radio frequency switch chip involved in this application;
[0033] Figure 8 This is a top view of a portion of the structure of a typical radio frequency switch chip;
[0034] Figure 9 This is a top view schematic diagram of a portion of the structure of the radio frequency switch chip according to the first embodiment of this application;
[0035] Figure 10 This is a three-dimensional disassembled view of a portion of the structure of the radio frequency switch chip according to the first embodiment of this application;
[0036] Figure 11 This is a top view of the first isolation trench according to the first embodiment of this application;
[0037] Figure 12 This is another top view of the first isolation trench according to the first embodiment of this application;
[0038] Figure 13 This is a top view of the first and second isolation trenches according to the first embodiment of this application;
[0039] Figure 14 for Figure 8 , Figure 11 and Figure 13 The simulation diagram shows the isolation between adjacent RF channels of three different chip structures.
[0040] Figure 15 This is a side view of the radio frequency switch chip including the substrate according to the second embodiment of this application;
[0041] Figure 16 This is a three-dimensional schematic diagram showing the disassembled radio frequency switch chip, including the substrate, according to the second embodiment of this application.
[0042] Figure 17 This is a simulation diagram illustrating the isolation between adjacent RF channels on three different substrates. Detailed Implementation
[0043] The present application will be further described below with reference to specific embodiments and accompanying drawings. It is to be understood that the illustrative embodiments of the present application are merely for explaining the present application and not for limiting the present application. Furthermore, for ease of description, the accompanying drawings show only the parts relevant to the present application, and not all of the structures or processes.
[0044] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Although the description of this application is presented in conjunction with preferred embodiments, this does not mean that the features of this application are limited to this embodiment. On the contrary, the purpose of describing the application in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of this application. To provide a thorough understanding of this application, many specific details will be included in the following description. This application may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of this application, some specific details will be omitted in the description. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0045] Unless the context otherwise specifies, the terms “contains,” “has,” and “includes” are synonyms. The phrase “A / B” means “A or B.” The phrase “A and / or B” means “(A and B) or (A or B).”
[0046] It should be understood that although terms such as "first," "second," etc., may be used herein to describe various components, units, or data, these components, units, or data should not be limited by these terms. These terms are used merely to distinguish one feature from another. For example, without departing from the scope of the exemplary embodiments, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.
[0047] It should be understood that although directional terms such as "up," "down," "left," and "right" may be used here to describe the positional relationship between the various components, these directional terms are only for the convenience of understanding and are not intended to limit the scope of protection of this application.
[0048] It should be noted that in this specification, similar reference numerals and letters in the accompanying drawings indicate similar items. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0050] Figure 1 This is a simplified circuit diagram of an RF switch chip. Figure 1 As shown, the RF switch chip includes n channels, each RF channel comprising a series-parallel switch structure, which can be described as an SR-SH switch, where SR (Series Resonant) represents a series switch and SH (Shunt Resonant) represents a parallel switch. The switch (SR switch) connected in series between the RF input and RF output terminals in an RF channel is defined as the first switch. Along the signal transmission direction, multiple first switches connected in series are successively called the first-stage first switch, the second-stage first switch, and so on. The switch (SH switch) connected in parallel between the RF channel and standard ground in an RF channel is defined as the second switch. Along the signal transmission direction, multiple second switches connected in parallel are successively called the first-stage second switch, the second-stage second switch, and so on.
[0051] exist Figure 1 In the example, RFin is the radio frequency input terminal and RFout is the radio frequency output terminal. Each channel from the radio frequency input terminal to the radio frequency output terminal includes three-stage series first switches (SR switches) and two-stage parallel second switches (SH switches). Each stage of the second switch has a ground point connected to the standard ground. Connecting the second switch to the standard ground provides a path to ground in the switch-off, i.e., isolated state. Figure 1The grounding symbol in the figure represents the grounding point of the second switch, wherein the grounding point of the first-level second switch of the first radio frequency channel is the first grounding point 11, the grounding point of the second-level second switch of the first radio frequency channel is the second grounding point 12, the grounding point of the first-level second switch of the second radio frequency channel is the third grounding point 13, and the grounding point of the second-level second switch of the second radio frequency channel is the fourth grounding point 14.
[0052] For two adjacent RF channels in an RF switch chip, in a series-parallel switch structure, each channel has several SH switches, which is usually referred to as the number of grounding levels. For example... Figure 1 The example in the paper is a two-level grounding structure, but this application is not limited to this. It can also be a single-level grounding, three-level grounding, four-level grounding structure, etc. The commonly used structure is a two-level or three-level grounding structure.
[0053] The specific number of grounding levels used is determined by the overall chip design. Generally, more grounding levels result in higher isolation, but also a larger chip area and higher cost. Furthermore, more grounding levels require more grounding bumps, which, due to limitations in bump spacing, can lead to miniaturization difficulties. In short, the number of grounding levels is determined at the initial design stage, and the location of the SH switch's grounding point is also determined accordingly for the circuit layout.
[0054] Figure 2 This is a 3D schematic diagram of an RF switch chip. Figure 2 As shown, the first to fourth ground points 11-14 of the RF switch chip are connected to the ground plane of the RF switch chip. The ground plane of the RF switch chip is connected to the ground plane or ground area on the substrate through ground bumps. The ground plane or ground area on the substrate is a standard ground. The ground bumps are located at... Figure 2 The surface of the RF chip shown can have a grounding bump, which can be a solder ball, copper pillar bump, hybrid material bump, gold bump, or any other type of bump in the art that can connect the chip to the substrate. The substrate consists of the chip and a PCB board. Figure 2 The transition structure between (not shown) and the substrate serves to support the chip and electrically connect the chip to the PCB board.
[0055] The ground bump is equivalent to an inductance to the standard ground. This equivalent inductance (parasitic inductance) will increase the impedance from the ground point of the corresponding second switch to the standard ground at high frequencies, thus degrading the isolation. In the ideal case of grounding the RF switch chip, the equivalent inductance from the ground bump to the standard ground is 0. However, this is only an ideal case. The ground point of the RF switch chip to the standard ground is usually not ideal.
[0056] Figure 3This diagram illustrates the simulation of isolation between the ground point of an RF switch chip and standard ground in five scenarios: ideal grounding, non-ideal grounding, and standard grounding. (Refer to reference...) Figure 1 and Figure 3 :
[0057] C1 indicates that the first ground point 11 and the second ground point 12 of the first RF channel, the third ground point 13 and the fourth ground point 14 of the second RF channel are all independently grounded, and each ground point is ideally grounded to the standard ground.
[0058] C2 indicates that: the first grounding point 11 and the second grounding point 12 share a common ground, and the third grounding point 13 and the fourth grounding point 14 share a common ground, and each grounding point is ideally grounded to the standard ground;
[0059] C3 indicates that the first grounding point 11 and the third grounding point 13 share a common ground, and each grounding point is ideally grounded to the standard ground;
[0060] C4 indicates that the second grounding point 12 and the fourth grounding point 14 share a common ground, and each grounding point is ideally grounded to the standard ground;
[0061] C5 indicates that the grounding from each grounding point to the standard ground is not ideal, and the equivalent inductance of each grounding bump is 30pH. The first to fourth grounding points 11-14 are grounded through this equivalent inductance.
[0062] like Figure 3 As shown, the horizontal axis represents frequency in GHz, and the vertical axis represents isolation in dB. Among the five cases C1-5 shown in the figure, the isolation between the first and second RF channels is the best in case C1, that is, the isolation between two adjacent RF channels is the highest. In turn, the isolation is the second best in case C2, the next best in case C3, the next best in case C4, and the worst in case C5.
[0063] according to Figure 3 The isolation curve shown leads to the following conclusions:
[0064] (1) In case C3, the first-level grounding point of adjacent RF channels is the same, and in case C4, the second-level grounding point of adjacent RF channels is the same. The isolation of C3 is better than that of C4. That is to say, the closer the grounding point of adjacent RF channels is to the RFout port, the greater the impact on the isolation between adjacent RF channels, which will seriously deteriorate the isolation.
[0065] (2) In case C2, the grounding points of the same RF channel are common ground. In cases C3 and C4, the grounding points of the corresponding levels of adjacent RF channels are common ground. The isolation of C2 is better than that of C3 and C4. That is to say, the common grounding of the grounding points of the same RF channel has less impact on the isolation between adjacent RF channels than the common grounding of the corresponding levels of adjacent RF channels. Therefore, in order to improve the isolation, the grounding points of the corresponding levels of adjacent RF channels need to be isolated.
[0066] according to Figure 3 The conclusion drawn (1) is that the closer the grounding points of adjacent RF channels are to the RFout port, the greater the impact on the isolation between adjacent RF channels, which will seriously deteriorate the isolation. Therefore, in the first embodiment of this application, a first isolation trench is provided on the interconnect layer. The first isolation trench penetrates the interconnect layer of the RF switch in the direction perpendicular to the chip surface to isolate the two grounding points closest to the RFout port of two adjacent RF channels, thereby cutting off the common grounding path that has the greatest impact on the isolation and separating the grounding paths of the two adjacent RF channels at that point. The grounding point corresponding to the last stage second switch has at least one grounding bump that is closest to it. The first isolation trench isolates the grounding bump that is closest to the grounding point corresponding to the last stage second switch of the two adjacent RF channels, and one end of the first isolation trench extends to the grounding bump that is closest to the grounding point in the planar direction of the top view.
[0067] Isolation trenches can be formed on the interconnect layer using chip manufacturing processes such as photolithography and etching. A non-conductive dielectric material is then filled within the isolation trenches to achieve the isolation effect. Specifically, photolithography is first used to define the isolation trench pattern at designated locations on the interconnect layer. A photoresist mask is used to protect the non-etched areas. Then, etching processes, such as reactive ion etching (RIE), are used to selectively etch the interconnect layer, forming isolation trenches with vertical or inclined sidewalls. The non-conductive dielectric material can be SiO2 or Si3N4, filled into the isolation trench using methods such as plasma-enhanced chemical vapor deposition (PECVD); alternatively, polymer materials, such as polyimide (PI), can be used, filled into the isolation trench through spin-coating and curing; or air gaps can be formed, where the non-conductive dielectric material filled into the isolation trench is air or a low-pressure cavity.
[0068] Reference Figure 1 , Figure 4-10 In the first embodiment, the radio frequency switch chip 10 includes: N series-connected first switches, which are connected in series between the radio frequency input terminal and the radio frequency output terminal of the radio frequency channel, where N is an integer ≥1; and M parallel-connected second switches, each of which is connected between the radio frequency channel and the standard ground, where M is an integer ≥1. Figure 1The example shown illustrates a three-stage SR switch and a two-stage SH switch, but this does not constitute a limitation on the technical solution of this application. Each stage's second switch has a grounding point for connection to standard ground, such as... Figure 1 As shown, the first-stage second switch of the first RF channel has a first ground point 11, the second-stage second switch of the first RF channel has a second ground point 12, the first-stage second switch of the second RF channel has a third ground point 13, and the second-stage second switch of the second RF channel has a fourth ground point 14. The surface of the RF switch chip has ground bumps 20, and the first to fourth ground points 11-14 are connected via their corresponding ground bumps 20 (refer to reference). Figure 4 It is electrically connected to standard ground. The RF switch chip also includes: device layer 17 and interconnect layer 18 located on device layer 17. A first isolation slot 41 is provided on interconnect layer 18. The first isolation slot 41 is used to isolate the ground points 12 and 14 corresponding to the last stage second switch of two adjacent RF channels. The first isolation slot is filled with a non-conductive dielectric.
[0069] Figure 4 This is a cross-sectional schematic diagram of a portion of an RF switch chip, where: SI represents silicon, the chip's substrate material; PAD represents solder pads, used for electrical connections; OXIDE represents oxide, used as an insulating layer; PI represents polyimide, used for insulation and protection; TI / CU represents titanium / copper, used as a metallization layer for electrical connections; CU represents copper, used as the main body of the ground bump for electrical connections; SN / AG represents tin / silver, used as solder; and NI represents nickel, used to prevent copper diffusion. Figure 4 As shown, the RF switch chip includes a substrate 15 and a functional area 16 that implements the chip's circuitry. The material selection for the substrate 15 must balance high-frequency performance, loss control, integration density, and cost. To improve isolation, RF switch chips typically use silicon-on-insulator (SOI) as the substrate, but this application is not limited to this; single-crystal silicon, gallium arsenide (GaAs), gallium nitride (GaN), sapphire (Al2O3), and other materials can also be used as the substrate. The RF switch chip also includes a ground bump 20 disposed on the chip surface. The ground bump 20 is a copper pillar bump, one end of which is electrically connected to a pad (PAD), and the other end is electrically connected to the substrate (SPECTION) via tin / silver (SN / AG) solder. Figure 4 (Not shown)
[0070] Figure 5 This is a cross-sectional schematic diagram of the functional area of an RF switch chip. (Example:) Figure 5As shown, the functional region 16 of the RF switch chip includes a device layer 17 and an interconnect layer 18. The device layer 17 is the active region, on which a first switch and a second switch, including NMOS and / or PMOS transistors, are formed in the substrate material using photolithography. The switches are not limited to MOS transistors; other device structures that can be used as switches can also be employed. The interconnect layer 18 covers the device layer 17 and consists of multiple layers of copper / gold interconnects 181 and tungsten / copper conductive plugs 182. The conductive plugs 182 enable low-impedance interlayer connections, and the switches form signal paths through the interconnects 181 and conductive plugs 182. The ground point of the RF switch chip is located in the interconnect layer. It can use a single conductive plug as the ground point, or a single interconnect as the ground point to form a mesh-like low-impedance grounding network, or a combination of interconnects and conductive plugs as the ground point.
[0071] The RF switch chip also includes a chip ground layer or a chip ground region. The chip ground layer or chip ground region can be configured in one or more layers depending on the actual situation; for example, it can be located in one or more interconnect layers. The grounding point of the RF switch chip is the connection point between the second switch and the chip ground layer or chip ground region. Similarly, the substrate's ground layer or ground region can also be configured in one or more layers depending on the actual situation. Here, a ground layer refers to a basically entire metal layer as a ground layer, and a ground region refers to a portion of an entire metal layer as a ground region. This application... Figure 6-13 The chip ground layer 10 and substrate ground layer 30 shown are for illustrative purposes only. The number of chip ground layers 10 and substrate ground layers 30, and their locations, need to be determined based on the specific chip structure and substrate structure. In this embodiment, the chip ground layer 10 and substrate ground layer 30 are described as a single layer of metal.
[0072] Figure 6 This is a three-dimensional schematic diagram of a portion of the structure of the radio frequency switch chip involved in this application. Figure 7 This is a three-dimensional disassembled schematic diagram of a portion of the structure of the radio frequency switch chip involved in this application. Figure 6 and Figure 7 As shown, reference numeral 10 indicates the ground plane of the RF switch chip, reference numeral 20 indicates the ground bump, and reference numeral 30 indicates the ground plane of the substrate. The ground point of the RF switch chip is located in the ground plane 10 of the RF switch chip and is connected to the ground plane 30 of the substrate through the ground bump 20.
[0073] Figure 8 This is a top view of a portion of the structure of a typical radio frequency switch chip. (Example:) Figure 8As shown, viewed from above, the first to fourth grounding points 11-14, represented by the black squares, are located between the two grounding bumps 20. This arrangement of the relative positions of the grounding points and grounding bumps will cause the return path of the SH switch on the interconnect layer to become longer, thereby increasing the parasitic inductance from the grounding point to the standard ground and reducing the isolation between adjacent RF channels.
[0074] Figure 9 This is a top view schematic diagram of a portion of the structure of the radio frequency switch chip according to the first embodiment of this application. Figure 10 This is a three-dimensional schematic diagram showing a partial structure of the radio frequency switch chip according to the first embodiment of this application. Figure 9 and Figure 10 As shown, reference numeral 41 indicates the first isolation slot provided on the RF switch chip. The first isolation slot 41 is located between the second ground point 12 and the fourth ground point 14 (wherein... Figure 10 (The grounding point is omitted). The second grounding point 12 is the grounding point corresponding to the second-level SH switch of the first RF channel, and the fourth grounding point 14 is the grounding point corresponding to the second-level SH switch of the second RF channel. That is to say, the second grounding point 12 and the fourth grounding point 14 are the two grounding points closest to the RFout port of adjacent RF channels. The common ground path between the second grounding point 12 and the fourth grounding point 14, which have the greatest impact on the isolation, is cut off by the first isolation slot 41, thereby improving the isolation. The grounding points 12 and 14 of the last-stage SH switch are located on the ground layer 10 of the RF switch chip and are connected to the ground layer 30 (standard ground) of the substrate through the grounding bumps 20. The first isolation groove 41 can extend the return path between grounding points 12 and 14. That is to say, when the signal of the right channel is connected to the ground layer 30 of the substrate from grounding point 12, if there is no first isolation groove 41, in addition to going to the ground layer of the substrate through the two grounding bumps 20 adjacent to grounding point 12, the signal will also flow to the two grounding bumps 20 adjacent to grounding point 14, which may affect the left channel through grounding point 14.
[0075] Figure 11 This is a top view schematic diagram of the first isolation trench according to the first embodiment of this application. Utilizing Figure 11 Further explanation of the first isolation slot 41: the second grounding point 12 of the second-stage SH switch of the first RF channel corresponds to two adjacent grounding bumps, the first bump 21 and the second bump 22; the fourth grounding point 14 of the second-stage SH switch of the second RF channel corresponds to two adjacent grounding bumps, the third bump 23 and the fourth bump 24. The first bump 21 is located on the first side of the second grounding point 12, and the third bump 23 is located on the first side of the fourth grounding point 14. The first side is... Figure 11On the upper side, that is, the side near the grounding point of the first-stage SH switch, the second protrusion 22 is located on the second side of the second grounding point 12, and the fourth protrusion 24 is located on the second side of the fourth grounding point 14. The second side is... Figure 11 The lower side of the grounding point, i.e., the side away from the grounding point of the first-stage SH switch. In the illustrated example, dashed line 43 represents the line connecting the edges of the first side of the first protrusion 21 and the third protrusion 23, and dashed line 44 represents the line connecting the edges of the second side of the second protrusion 22 and the fourth protrusion 24. It should be noted that dashed lines 43 and 44 are not actual lines, but are virtual lines used for illustrative purposes. Since the second grounding point 12 can form a ground loop with the adjacent first protrusion 21 and the second protrusion 22 respectively, and the fourth grounding point 14 can form a ground loop with the adjacent third protrusion 23 and the fourth protrusion 24 respectively, in order to completely cut off the common ground path between the second grounding point 12 and the fourth grounding point 14, the length of the first isolation groove 41 needs to extend at least from dashed line 43 to dashed line 44. That is, the length of the first isolation groove 41 needs to extend from the edges of the first side of the first protrusion 21 and the third protrusion 23 to the edges of the second side of the second protrusion 22 and the fourth protrusion 24. In this application, the grounding bumps (first bump 21 and second bump 22, third bump 23 and fourth bump 24) corresponding to the second grounding point and the fourth grounding point are symmetrically distributed, but this application is not limited to the case of symmetrical distribution, and the grounding bump corresponding to the first grounding point and the second grounding point can also be a single bump.
[0076] according to Figure 3 The conclusion obtained (2) is that in order to further improve the isolation, the grounding points of the corresponding levels of adjacent RF channels need to be isolated. In the first embodiment of this application, the length of the first isolation groove can be further extended, for example, it can be extended to the edge of the grounding bump of the first side of the grounding point of the first level SH switch of the two adjacent RF channels, so as to isolate the grounding points of the second switches of the first to M levels of the two adjacent RF channels. Figure 12 This is another top view of the first isolation trench according to the first embodiment of this application, as shown below. Figure 12As shown, the grounding bump located on the first side of the first grounding point 11 is the fifth bump 25, and the grounding bump located on the first side of the third grounding point 13 is the sixth bump 26. The end of the first side of the first isolation groove 41 extends further to the line 43 connecting the first side edges of the fifth bump 25 and the sixth bump 26. It should be further pointed out that isolating the grounding points corresponding to the first to M level second switches of adjacent RF channels here means isolating the grounding point of the first level SH switch of the first RF channel from the grounding point of the first level SH switch of the second RF channel, isolating the grounding point of the second level SH switch of the first RF channel from the grounding point of the second level SH switch of the second RF channel, and so on, until the grounding point of the M level SH switch of the first RF channel from the grounding point of the M level SH switch of the second RF channel is isolated.
[0077] Figure 9-12 The illustration shows the first isolation trench as a straight line in the direction perpendicular to the chip surface, but this application is not limited to this. Depending on the actual distribution of the grounding points, the first isolation trench can also be set as a broken line.
[0078] To further improve isolation, in the first embodiment of this application, at least one second isolation trench can be provided in the interconnect layer of the RF switch chip to isolate the grounding point of the M-th level SH switch and the grounding point of the (M-1)-th level SH switch of the RF channel. For example, in a two-level grounding structure, a second isolation trench is provided on the interconnect layer to isolate the grounding point of the 2nd level SH switch and the grounding point of the 1st level SH switch of the RF channel. Figure 13 This is a top view schematic diagram of the first and second isolation trenches according to the first embodiment of this application. Figure 13 As shown, the second isolation trench 42 is disposed in the interconnect layer of the RF switch chip 10. The extension direction of the first isolation trench 41 is defined as the first direction, and the extension direction of the second isolation trench 42 is defined as the second direction. The first direction and the second direction intersect each other. The second isolation trench defines the current path between the grounding point with the greatest impact on isolation between the isolation channels and the grounding point with the least impact on isolation between the isolation channels. The grounding bump located on the second side of the first grounding point 11 is the seventh bump 27, and the grounding bump located on the second side of the third grounding point 13 is the eighth bump 28. The second isolation trench 42 is located on the second side of the seventh bump 27 and the eighth bump 28, and on the first side of the third bump 23 and the fourth bump 24, for isolating the first grounding point 11 and the second grounding point 12, and isolating the third grounding point 13 and the fourth grounding point 14. Figure 13In the preferred embodiment shown, the end of the first side of the first isolation trench 41 extends exactly to the second isolation trench 42. However, this application is not limited to this; as long as the first isolation trench 41 can completely cut off the common ground path between the second ground point 12 and the fourth ground point 14, it may not extend to the second isolation trench 42. In addition, the first isolation trench may also extend past the second isolation trench, that is, after the first isolation trench and the second isolation trench intersect, it continues to extend along the second direction, thereby isolating the ground points corresponding to the first to M level second switches of adjacent RF channels. Figure 13 The illustration shows a scenario where the first and second isolation trenches are straight lines and perpendicular to each other. However, this application is not limited to this configuration. Depending on the actual distribution of the grounding points, the first and second isolation trenches can also be arranged as broken lines, and the first direction of the extension of the first isolation trench and the second direction of the extension of the second isolation trench can intersect at any angle. Figure 13 The illustration only shows a second isolation slot in a two-level grounding structure to isolate the grounding point of the second-level SH switch from the grounding point of the first-level SH switch. However, this application is not limited to this. The RF switch chip can be a three-level, four-level, or five-level grounding structure, and multiple second isolation slots can be set to isolate the grounding points of each level of SH switch.
[0079] Reference Figure 5 In this application, the first isolation trench and the second isolation trench can extend from the surface of the RF switch to the bottom layer of the interconnect layer and stop above the device layer 17 (the word "above" here does not mean directly above, but is only used to illustrate the relative positional relationship between the upper and lower layers), and can penetrate the bottom layer of the interconnect layer. The purpose of the first isolation trench and the second isolation trench is to isolate the conduction path between two adjacent grounding points. As long as the first isolation trench and the second isolation trench can meet this requirement, they are all technical solutions to be protected in this application.
[0080] To further improve isolation, in the first embodiment of this application, multiple parallel second isolation slots can be provided on the interconnect layer, which are used to isolate the grounding points corresponding to the adjacent two-stage second switches of the first radio frequency channel and the grounding points corresponding to the adjacent two-stage second switches of the second radio frequency channel.
[0081] Figure 14 for Figure 8 , Figure 11 and Figure 13 The diagram shows a simulation of the isolation between adjacent RF channels for three different chip structures, where "Structure 1" is represented by a solid line. Figure 8 The isolation curves between adjacent RF channels in the conventional chip structure shown are illustrated by the long dashed line "Structure 2". Figure 11The diagram shows the isolation curves between adjacent RF channels in a chip structure with a first isolation trench. The short dashed line "Structure 3" indicates... Figure 13 The diagram shows the isolation curves between adjacent RF channels in a chip structure with a first isolation trench and a second isolation trench. Figure 14 It is clear that setting isolation slots on the interconnects of RF switch chips to isolate grounding points can effectively improve isolation.
[0082] The above analysis and explanation of the on-chip interconnect layer (including ground bumps) isolation treatment of high isolation RF switch chips have been provided. In chip product design, RF switch chips also need to be packaged together, such as FCLGA (Flip Chip Land Grid Array) packaging, and designed as a whole product. Therefore, isolation on the packaging substrate is also a key consideration in chip design. Figure 15 This is a side view of the radio frequency switch chip, including the substrate structure, according to the second embodiment of this application. Figure 16 This is a three-dimensional schematic diagram showing the disassembled radio frequency switch chip, including its substrate structure, according to the second embodiment of this application. Figure 15 and Figure 16 As shown, the ground layer 10 of the RF switch chip is connected to the ground layer 30 of the substrate via ground bumps 20. The ground layer 30 of the substrate includes four metal layers, namely, the first metal layer 31, the second metal layer 32, the third metal layer 33, and the fourth metal layer 34, starting from the ground layer 10 side of the RF switch chip. It is easy to see that the number of metal layers in the substrate structure can be set according to the needs of the chip design, for example, it can be two, three, five, or six layers. The substrate metal layers are electrically connected through vias 36. A third isolation trench 35 corresponding to the first isolation trench 41 is provided on the first metal layer 31, and the third isolation trench 35 is filled with a non-conductive dielectric. The non-conductive dielectric filling the third isolation trench 35 can be a polymer material, such as polyimide (PI), which is filled into the third isolation trench by spin-coating and curing.
[0083] Furthermore, a third isolation trench 35 corresponding to the first isolation trench 41 can also be provided on the second and third metal layers, thereby further improving the isolation of the RF switch chip. It should be further noted that the lateral dimension of the third isolation trench is larger than that of the first isolation trench, and the range of the third isolation trench in the vertical chip direction can completely cover the range of the first isolation trench.
[0084] Figure 17This diagram illustrates the simulation of isolation between adjacent RF channels for three different substrate structures. Solid lines represent the isolation curve without a third isolation trench in the substrate structure; long dashed lines represent the isolation curve with a third isolation trench only in the first metal layer of the substrate structure; and short dashed lines represent the isolation curve with third isolation trenches in the first to third metal layers of the substrate structure. Figure 17 It can be seen that setting a third isolation trench on the metal layer in the substrate structure, corresponding to the first isolation trench, can significantly improve the isolation of the RF switch chip. Moreover, the more metal layers on which the third isolation trench is set, the better the improvement in isolation.
[0085] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Where there is no conflict, the embodiments and features described in the embodiments of this application can be combined with each other. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A radio frequency switch chip, characterized in that, It includes at least an adjacent first radio frequency channel and a second radio frequency channel, each radio frequency channel including a series-parallel switch structure, the series-parallel switch structure including: The first switch in the N-stage series is connected in series between the RF input terminal and the RF output terminal of the RF channel, where N is an integer ≥ 1; The second switches are connected in parallel in M stages, with each stage of the second switch connected between the radio frequency channel and the standard ground, where M is an integer ≥1. Each stage of the second switch has a grounding point for connection to the standard ground. The surface of the radio frequency switch chip has grounding bumps, and each grounding point is electrically connected to standard ground through its corresponding grounding bump. The radio frequency switch chip further includes: a device layer and an interconnect layer located on the device layer; A first isolation slot is provided on the interconnect layer. The first isolation slot is used to isolate the grounding point that has the greatest impact on the isolation between two adjacent radio frequency channels. The first isolation slot is filled with a non-conductive dielectric.
2. The radio frequency switch chip as described in claim 1, characterized in that, The first switch and the second switch each include a transistor, and the transistor is located in the device layer; The interconnect layer includes: an interconnect line and a conductive plug connected to the interconnect line; the first switch and the second switch are electrically connected through the interconnect line and the conductive plug. The grounding point includes a conductive plug, an interconnect, or a conductive plug and an interconnect located in the interconnect layer.
3. The radio frequency switch chip as described in claim 1, characterized in that, The grounding points that have the greatest impact on the isolation between channels include: the grounding points corresponding to the last stage second switches of two adjacent radio frequency channels along the radio frequency transmission direction.
4. The radio frequency switch chip as described in claim 1, characterized in that, The grounding point corresponding to the last-stage second switch has at least one grounding bump that is closest to it; The first isolation groove is used to isolate the grounding bumps of two adjacent radio frequency channels that are closest to the grounding point corresponding to the last stage second switch.
5. The radio frequency switch chip as described in claim 1, characterized in that, One end of the first isolation groove extends to the grounding bump closest to the grounding point corresponding to the last stage second switch.
6. The radio frequency switch chip as described in claim 1, characterized in that, The first isolation trench is a straight line or a broken line in the direction perpendicular to the chip surface.
7. The radio frequency switch chip as described in claim 1, characterized in that, The first isolation trench penetrates the interconnect layer of the RF switch in the direction perpendicular to the chip surface.
8. The radio frequency switch chip as described in claim 1, characterized in that, The two grounding bumps adjacent to the grounding point corresponding to the last stage second switch of the first RF channel are the first bump and the second bump, respectively. The two grounding bumps adjacent to the grounding point corresponding to the last stage second switch of the second RF channel are the third bump and the fourth bump, respectively; The first bump and the third bump are located on the first side of the grounding point corresponding to the last stage second switch of two adjacent radio frequency channels; The second bump and the fourth bump are located on the second side of the grounding point corresponding to the last stage second switch of two adjacent radio frequency channels; The end of the first side of the first isolation groove extends at least to the line connecting the edges of the first protrusion and the first side of the third protrusion, and the end of the second side of the first isolation groove extends at least to the line connecting the edges of the second protrusion and the second side of the fourth protrusion.
9. The radio frequency switch chip as described in claim 8, characterized in that, The grounding bump on the first side of the grounding point corresponding to the first-level second switch of the first radio frequency channel is the fifth bump, and the grounding bump on the first side of the grounding point corresponding to the first-level second switch of the second radio frequency channel is the sixth bump. The end of the first side of the first isolation groove extends at least to the line connecting the edge of the first side of the fifth bump and the sixth bump.
10. The radio frequency switch chip as described in claim 8, characterized in that, At least one second isolation trench is also provided on the interconnect layer. The second isolation trench is filled with a non-conductive dielectric. The extension direction of the first isolation trench is a first direction, and the extension direction of the second isolation trench is a second direction. The first direction and the second direction intersect. The second isolation trench is used to isolate the current path between the grounding point with the greatest impact of inter-channel isolation and the grounding point with the least impact of inter-channel isolation.
11. The radio frequency switch chip as described in claim 10, characterized in that, The grounding bump on the second side of the grounding point corresponding to the second switch of the second-to-last level in the first RF channel is the seventh bump, and the grounding bump on the second side of the grounding point corresponding to the second switch of the second-to-last level in the second RF channel is the eighth bump. The second isolation groove is located on the second side of the seventh bump and the eighth bump, and on the first side of the third bump and the fourth bump.
12. The radio frequency switch chip as described in claim 10, characterized in that, Multiple parallel second isolation slots are provided on the interconnect layer to isolate the grounding points corresponding to the two adjacent second switches of the first RF channel and the two adjacent second switches of the second RF channel, respectively.
13. The radio frequency switch chip according to any one of claims 1-12, characterized in that, The radio frequency switch chip is packaged on a substrate, which includes X metal layers, where X is an integer ≥2. The metal layers are electrically connected through vias. A third isolation trench corresponding to the first isolation trench is provided on the first metal layer, and the third isolation trench is filled with a non-conductive dielectric.
14. The radio frequency switch chip as described in claim 13, characterized in that, A third isolation trench corresponding to the first isolation trench is provided on the first metal layer to the (X-1)th metal layer respectively.
15. The radio frequency switch chip as described in claim 13, characterized in that, The lateral dimension of the third isolation trench is larger than that of the first isolation trench, and the range of the third isolation trench in the vertical chip direction can completely cover the range of the first isolation trench.