Display panel and display device

Abstract

The application discloses a display panel and a display device, and belongs to the technical field of display. The display panel comprises a display area and a non-display area, the non-display area comprises a driving chip, at least one demultiplexing chip and at least one first switch module for inputting a predetermined high level; the demultiplexing chip comprises at least one first transistor, and one first transistor is arranged in correspondence with each output channel of the demultiplexing chip; the display area is connected with the first electrode of the first transistor through a first signal line, and one first signal line is connected with one first transistor; the second electrode of the first transistor is connected with the driving chip through a second signal line, and one second signal line is connected with a plurality of first transistors; and the gate of the first transistor is connected with the first switch module. In this way, the dynamic adjustment of chip matching can be realized based on the on-off control of the switch module and the transistor, so that the number of wirings is reduced and the control flexibility is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] The number of signal traces directly affects the size of the display product's bezel. Taking a mainstream 4K (3840RGBx2160) resolution product as an example, it requires 3840*3=11520 fanout signal traces. If a solution using 12 chip-on-film (COF) integrated circuits is adopted, each fanout requires 960 traces, resulting in a larger bezel. Moreover, because the mobility of currently used amorphous silicon (a-Si) semiconductor panels or metal-oxide semiconductor panels is relatively low, it may lead to insufficient driving, making it difficult to deploy demultiplexer (demux) circuits in the display area. Furthermore, the flexibility of using demux circuits is poor, making it difficult to meet the needs of different scenarios. Utility Model Content

[0003] This application provides a display panel and a display device to solve the technical problem of poor flexibility of demux in dealing with different panel types and scenarios.

[0004] According to a first aspect of the present application, a display panel is provided, the display panel comprising: a display area and a non-display area, the non-display area comprising a driver chip, at least one demultiplexing chip, and at least one first switch module for inputting a predetermined high level; the demultiplexing chip comprises: at least one first transistor, each output channel of the demultiplexing chip corresponding to one first transistor; the display area is connected to the first terminal of the first transistor via a first signal line, and one first signal line connects to one first transistor; the second terminal of the first transistor is connected to the driver chip via a second signal line, and one second signal line connects to multiple first transistors; the gate of the first transistor is connected to the first switch module; wherein, the non-display area comprises a first fan-out area and a second fan-out area, the first fan-out area comprising the first signal line, the second fan-out area comprising the second signal line, and the number of the first signal lines equal to the product of the number of the second signal lines, the number of the demultiplexing chips, and the number of output channels of a single demultiplexing chip.

[0005] In one possible implementation, when the number of demultiplexing chips is greater than 1, one of the first switching modules is simultaneously connected to the gate of one of the first transistors in each of the demultiplexing chips.

[0006] In one possible implementation, the non-display area further includes: at least one second switch module for inputting a predetermined high level; each of the demultiplexing chips further includes: at least one second transistor; the gate of one second transistor is connected to one of the second switch modules; in one of the demultiplexing chips, the first terminal of one second transistor is connected to the second terminals of a predetermined number of first transistors; the second terminals of the second transistors are connected to the driver chip via a second signal line; the number of first transistors is equal to the product of the number of second transistors and the predetermined number.

[0007] In one possible implementation, when the number of demultiplexing chips is greater than 1, one of the second switching modules is simultaneously connected to the gate of one of the second transistors in each of the demultiplexing chips.

[0008] In one possible implementation, the number of output channels of a single demultiplexing chip is 3 to 300.

[0009] In one possible implementation, the display panel has a resolution of 4K, the number of output channels of a single demultiplexing chip is 288, the number of demultiplexing chips is 2, the second signal line includes a plurality of second signal line groups, the number of the second signal line groups is equal to the number of demultiplexing chips, and the number of signal lines in each second signal line group is 20.

[0010] In one possible implementation, the display area is connected to the first terminal of the first transistor in the at least one demultiplexing chip via the first signal line with a 1:1 routing ratio.

[0011] In one possible implementation, when the number of demultiplexing chips is greater than 1, the demultiplexing chips are arranged side by side with respect to the edge of the display area closest to the driver chip and along the parallel direction of the edge.

[0012] In one possible implementation, the display panel is an amorphous silicon semiconductor panel or a metal oxide semiconductor panel.

[0013] According to a second aspect of the embodiments of this application, a display device is provided, the display device comprising the display panel described in any of the first aspects above.

[0014] This application provides a display panel and a display device. The display panel includes a display area and a non-display area. The non-display area includes a driver chip, at least one demultiplexing chip, and at least one first switch module for inputting a predetermined high level. The demultiplexing chip includes at least one first transistor, and each output channel of the demultiplexing chip corresponds to one first transistor. The display area is connected to the first terminal of the first transistor via a first signal line, and one first signal line connects to one first transistor. The second terminal of the first transistor is connected to the driver chip via a second signal line, and one second signal line connects to multiple first transistors. The gate of the first transistor is connected to the first switch module. The non-display area includes a first fan-out area and a second fan-out area. The first fan-out area includes the first signal line, and the second fan-out area includes the second signal line. The number of first signal lines is equal to the product of the number of second signal lines, the number of demultiplexing chips, and the number of output channels of a single demultiplexing chip. Thus, by placing the demultiplexing circuit on a separate chip outside the display area, the limitations of low panel mobility that prevents support for larger demultiplexing ratios can be avoided. This allows for a significant reduction in the actual number of traces connected to the driver chip, based on a larger demultiplexing ratio, thereby comprehensively reducing the bezel size. Furthermore, it eliminates the insufficient drive caused by some panel types' inability to support large demultiplexing ratios, improving the operational stability of different types of display panels. Moreover, by flexibly controlling the on / off state of the transistors within the demultiplexing chip through the switch module, the number of output channels connected to the driver chip can be flexibly controlled. Therefore, the demultiplexing ratio can be dynamically adjusted by switching the switch module state under different scenario requirements, improving flexibility in practical applications. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of the structure of a demultiplexing chip provided in an embodiment of this application;

[0018] Figure 3 This is a schematic diagram of the structure of a demultiplexing chip provided in an embodiment of this application;

[0019] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0020] Figure 5 This is a schematic diagram of the structure of a demultiplexing chip provided in an embodiment of this application;

[0021] Figure 6 This is a schematic diagram of the structure of a demultiplexing chip provided in an embodiment of this application.

[0022] Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0023] Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0024] Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0025] Explanation of reference numerals in the attached figures

[0026] 1. Display area; 2. Non-display area; 3. First signal line; 4. Second signal line; 21. Driver chip; 22. Demultiplexing chip; 23. First switch module; 24. Second switch module; 221. First transistor; 222. Second transistor. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present application can be combined with each other.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] This embodiment provides a display panel. Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. For example... Figure 1 and 2 As shown, the display panel includes a display area 1 and a non-display area 2. The non-display area 2 includes a driver chip 21, at least one demultiplexing chip 22, and at least one first switch module 23 for inputting a predetermined high level. The demultiplexing chip 22 includes at least one first transistor 221, and each output channel of the demultiplexing chip 22 is provided with one first transistor 221.

[0030] The display area 1 is connected to the first terminal of the first transistor 221 via a first signal line 3, and one first signal line 3 connects to one first transistor 221; the second terminal of the first transistor 221 is connected to the driving chip 21 via a second signal line 4, and one second signal line 4 connects to multiple first transistors 221; the gate of the first transistor 221 is connected to the first switching module 23.

[0031] The non-display area 2 includes a first fan-out area and a second fan-out area. The first fan-out area includes the first signal line 3, and the second fan-out area includes the second signal line 4. The number of the first signal lines 3 is equal to the product of the number of the second signal lines 4, the number of the demultiplexing chips 22, and the number of output channels of a single demultiplexing chip 22.

[0032] In this embodiment, the display panel can be used to display content, and the display area 1 included therein is used to perform display operations, such as display area 1 containing a pixel array. The non-display area 2 can be the border area of ​​the display panel, etc. The driving chip 21 can be set in the non-display area 2 of the display panel, for example, it can be a COF-IC, used to drive the pixel array in the display area 1 for display, etc.

[0033] Here, the driver chip 21 can be located in the border area of ​​the display panel, i.e., the non-display area 2. For example, the border area is the area in the display device that surrounds the display area 1.

[0034] In one embodiment, the driver chip 21 is located in the lower border area of ​​the display panel, which refers to the border area below the display area 1. Correspondingly, the demultiplexing chip 22 is located near the edge of the display area 1 closest to the driver chip 21, i.e., the lower edge of the display area 1.

[0035] For example, the display panel includes a demultiplexing chip 22, which is located close to the lower edge of the display area 1, and the demultiplexing chip 22 is connected to the driving chip 21 located in the lower frame area via a second signal line 4.

[0036] For example, the display panel includes multiple demultiplexing chips 22, which are disposed close to the lower edge of the display area 1 and arranged side by side along the lower edge. The second signal lines 4 of the connecting driver chip 21 corresponding to the multiple demultiplexing chips 22 are also arranged side by side along the lower edge.

[0037] In one embodiment, the display panel may contain only one driver chip 21, which may be a COF-IC.

[0038] In one embodiment, the display panel may include one demultiplexing chip 22, or two or more demultiplexing chips 22. Here, the demultiplexing chip 22 may be a chip containing demultiplexing circuitry, which may contain only demultiplexing circuitry or other circuitry.

[0039] In one embodiment, the first and second terminals of the first transistor 221 can be the output and input terminals of the first transistor 221, respectively. The second terminal of the first transistor 221 can be used to input the data signal generated by the driver chip 21 via the second signal line 4. The first switch module 23 may include a switch circuit, a switch element, or other types of gating elements. When the first switch module 23 is turned on, a predetermined high-level input is applied to the gate of the first transistor 221 connected to the first switch module 23. At this time, the first transistor 221 is turned on, and the data signal is transmitted to the display area 1 through the output channel corresponding to the first transistor 221.

[0040] In one embodiment, a demultiplexing chip 22 can connect to multiple second signal lines 4, and each second signal line 4 can connect to the second pole of multiple first transistors 221. In a demultiplexing chip 22, the product of the number of second signal lines 4 and the number of first transistors 221 connected to each second signal line 4 is equal to the total number of first transistors 221 in a demultiplexing chip 22.

[0041] For example, each second signal line 4 connects to the second terminal of 3 first transistors 221. When the total number of first transistors 221 is 300, the number of second signal lines 4 is 100.

[0042] In one embodiment, different first transistors 221 are connected to different first switching modules 23. For example, such as Figure 3As shown, the first switch module 23 may include sw1, sw2, and sw3, which are respectively connected to the first transistors Ma, Mb, and Mc. When sw1 is turned on, Ma is turned on, and the output channel s1 corresponding to Ma is turned on. At this time, the ratio of the multiplexing chip 22 is 1:1. When sw1 and sw2 are turned on, Ma and Mb are turned on, and the output channels s1 and s2 corresponding to Ma and Mb are turned on. At this time, the ratio of the multiplexing chip 22 is 1:2. When sw1, sw2, and sw3 are turned on, Ma, Mb, and Mc are turned on, and the output channels s1, s2, and s3 corresponding to Ma, Mb, and Mc are turned on. At this time, the ratio of the multiplexing chip 22 is 1:3.

[0043] Thus, by flexibly controlling the on / off state of the first transistor 221 in the demultiplexing chip 22 based on the first switch module 23, the number of output channels connected to the driver chip 21 can be flexibly controlled. Therefore, under different scenario requirements, the ratio of the demultiplexing chip 22 can be dynamically adjusted by switching the on / off state of the switch module, thereby improving the application flexibility of the demultiplexing chip 22 under diverse scenario requirements.

[0044] In one embodiment, the fanout area of ​​the non-display area 2 may include a first fanout area and a second fanout area. The first signal line 3 of the first fanout area corresponds to the input / output port in the display area 1, and can be connected to the first terminal of the first transistor 221 through the first signal line 3. The first terminal of the first transistor 221 can be connected to the input / output port of the display area 1 as the first terminal of the demultiplexing chip 22.

[0045] The second terminal of the first transistor 221 can be used as the second terminal of the demultiplexing chip 22 and connected to the driver chip 21 via the second signal line 4. The demultiplexing chip 22 has a certain ratio, which can be consistent with the number of output channels of a single demultiplexing chip 22. For example, a ratio of 1:300 indicates that the number of output channels of a single demultiplexing chip 22 is 300.

[0046] For example, taking a 4K resolution display panel as an example, the number of fan-out traces, i.e., the first signal lines 3, required for this display panel is 3840*3=11520. Based on the 1:288 ratio of the demultiplexing chip 22, that is, the number of output channels of a single demultiplexing chip 22 is 288, when two demultiplexing chips 22 are used, the number of second signal lines 4 connecting each demultiplexing chip 22 to the driver chip 21 is only 11520 / (288*2)=20.

[0047] In one embodiment, the demultiplexing chip 22 may include multiple demultiplexing circuits, each of which may have a certain ratio, such as 1:288, thereby further increasing the input-output ratio of the demultiplexing chip 22 and further saving the number of traces.

[0048] In related technologies, 4K resolution display panels use 12 COF-ICs, and the number of traces required for each COF-IC is 11520 / 12 = 960.

[0049] In one embodiment, such as Figure 4 As shown, the display panel includes two demultiplexing chips 22 and one driver chip 21 (COF-IC) for driving the display area 1. The first end of each demultiplexing chip 22 is connected to the display area 1, and the second end of each demultiplexing chip 22 is connected to the driver chip 21. Here, the portion of the demultiplexing chip 22 connected to the display area 1 can form a second fan-out area, which includes a second signal line 4; the portion of the demultiplexing chip 22 connected to the driver chip 21 can form a first fan-out area, which includes a first signal line 3.

[0050] For example, if the display panel has a 4K resolution and the demultiplexing chips 22 are configured in a 1:288 ratio, then the first number is 288, the third number is 2, and the second number is 20. Each demultiplexing chip 22 is connected to the driver chip 21 through 20 signal lines. In this way, the number of signal lines required for each demultiplexing chip 22 to connect to the COF-IC is reduced from 960 to only 20, significantly reducing the number of traces, i.e., the number of COF-ICs. Moreover, two demultiplexing chips 22 can ensure that the demultiplexing function will not be completely disabled due to the failure of one chip, and will not occupy bezel space due to too many demultiplexing chips 22.

[0051] In some embodiments, when the number of demultiplexing chips 22 is greater than 1, one of the first switch modules 23 is simultaneously connected to the gate of one of the first transistors 221 in each of the demultiplexing chips 22.

[0052] Here, the number of first transistors 221 connected to each first switch module 23 can be equal to the number of demultiplexing chips 22.

[0053] In one embodiment, a first switch module 23 can simultaneously connect to the gate of one or more first transistors 221 in each demultiplexing chip 22.

[0054] In one embodiment, the number of first transistors 221 connected to a first switch module 23 is the same in the plurality of demultiplexing chips 22, that is, each demultiplexing chip 22 has n first transistors 221 connected to the first switch module 23, where n is a positive integer less than or equal to the total number of first transistors 221 in the demultiplexing chip 22.

[0055] In this way, one switching module can simultaneously control the first transistor 221 specified in multiple demultiplexing chips 22, thereby synchronously controlling the output channels in multiple demultiplexing chips 22, which helps to reduce the number of switching modules.

[0056] In some embodiments, such as Figure 5 As shown, the non-display area 2 further includes: at least one second switch module 24 for inputting a predetermined high level; each of the demultiplexing chips 22 further includes: at least one second transistor 222; the gate of one second transistor 222 is connected to one second switch module 24;

[0057] In one of the demultiplexing chips 22, the first terminal of one of the second transistors 222 is connected to the second terminals of a predetermined number of the first transistors 221; the second terminal of the second transistor 222 is connected to the driver chip 21 through the second signal line 4; the number of the first transistors 221 is equal to the product of the number of the second transistors 222 and the predetermined number.

[0058] Here, the second terminal of the first transistor 221 is connected to the second signal line 4 through the second transistor 222, and the first and second terminals of the second transistor 222 can be the output terminal and the input terminal of the second transistor 222, respectively.

[0059] In one embodiment, the predetermined number may be, for example, 3, 4, 8, 72 or 144, etc., each second transistor 222 is connected to a predetermined number of first transistors 221, and different second transistors 222 are connected to different first transistors 221.

[0060] In one embodiment, the second switch module 24 may include a switch circuit, a switch element, or other type of gating element. When the second switch module 24 is turned on, a predetermined high-level input is applied to the gate of the second transistor 222 connected to the second switch module 24. At this time, the second transistor 222 is turned on, and the data signal is transmitted through the second transistor 222 to the first transistor 221 connected to the second transistor 222, and then transmitted to the display area 1 through the output channel corresponding to the first transistor 221.

[0061] In one embodiment, a demultiplexing chip 22 can be connected to multiple second signal lines 4, and each second signal line 4 can be connected to the second pole of multiple second transistors 222.

[0062] In one embodiment, different second transistors 222 are connected to different second switching modules 24. For example, such as Figure 6 As shown, the second switch module 24 may include sw4, sw5 and sw6, which are connected to the second transistors M1, M2 and M3 respectively. When sw4 is turned on, M1 is turned on. When sw1 is turned on, the output channel corresponding to the first transistor Ma connected to M1 is turned on. At this time, the ratio of the demultiplexing chip 22 is 1:1. When sw1 and sw2 are turned on, the output channels s1 and s2 corresponding to the first transistors Ma and Mb connected to M1 are turned on. At this time, the ratio of the demultiplexing chip 22 is 1:2.

[0063] When sw4 and sw5 are turned on, M1 and M2 are turned on. The first transistor 221 connected to M1 and M2 is turned on when the corresponding first switch module 23 is turned on, and the corresponding output channel is turned on. When sw4, sw5 and sw6 are turned on, M1, M2 and M3 are turned on. The first transistor 221 connected to M1, M2 and M3 is turned on when all the corresponding first switch modules 23 are turned on, and all the output channels corresponding to the first transistor 221 connected to the second transistor 222 are turned on. At this time, the ratio of the multiplexing chip 22 is 1:9.

[0064] Thus, by forming a multi-level ratio control through the first transistor 221 and the second transistor 222, the ratio of the demultiplexing chip 22 can be controlled with finer granularity. This allows for more precise and accurate dynamic adjustment of the output channel control of the demultiplexing chip 22, further enhancing the application flexibility under different scenario requirements.

[0065] In one embodiment, when the number of demultiplexing chips 22 is greater than 1, one of the second switch modules 24 is simultaneously connected to the gate of one of the second transistors 222 in each of the demultiplexing chips 22.

[0066] Here, the number of second transistors 222 connected to each second switch module 24 can be equal to the number of demultiplexing chips 22.

[0067] In one embodiment, a second switch module 24 may simultaneously connect to the gate of one or more second transistors 222 in each demultiplexing chip 22.

[0068] In one embodiment, the number of second transistors 222 connected to a second switch module 24 is the same in the plurality of demultiplexing chips 22, that is, each demultiplexing chip 22 has m second transistors 222 connected to the second switch module 24, where m is a positive integer less than or equal to the total number of second transistors 222 in the demultiplexing chip 22.

[0069] In this way, one switching module can simultaneously control the second transistor 222 specified in multiple demultiplexing chips 22, thereby synchronously controlling the output channels in multiple demultiplexing chips 22, which helps to reduce the number of switching modules.

[0070] In one embodiment, such as Figure 7 As shown, the display device includes one demultiplexing chip 22 and one driver chip 21 (COF-IC) for driving the display area 1. The first end of the demultiplexing chip 22 is connected to the display area 1, and the second end of the demultiplexing chip 22 is connected to the driver chip 21. If the display panel has a 4K resolution and the demultiplexing chip 22 uses a 1:288 ratio, then the number of output channels of the demultiplexing chip 22 is 288, the number of demultiplexing chips 22 is 1, and the number of second signal lines 4 is 40. The demultiplexing chip 22 is connected to the driver chip 21 through 40 second signal lines 4.

[0071] In one embodiment, the display area 1 is rectangular, and the demultiplexing chip 22 is disposed on the outer side of one side of the display area 1. The input / output port is connected to the demultiplexing chip 22 through this side. The second fan-out area formed by the connection between the second end and the driver chip 21 through the second signal line 4, and the first fan-out area formed by the connection between the input / output port and the first end, can together constitute the fanout area of ​​the non-display area 2 of the display panel. This fanout area can be located in the border area around the display panel.

[0072] In one embodiment, with the same display panel resolution and the same demultiplexing ratio, the more demultiplexing chips 22 there are, the fewer second signal lines 4 are required for each demultiplexing chip 22, resulting in a greater reduction in bezel size. When the number of demultiplexing chips 22 is greater than one, the multiple demultiplexing chips 22 are arranged parallel to each other along the direction of the edge closest to the display area 1. In this way, the multiple parallel demultiplexing chips 22 can be arranged based on fewer signal lines per demultiplexing chip 22 in the vertical direction, further reducing the width of the bezel in the vertical direction.

[0073] Thus, by placing the demultiplexing circuit on a separate chip outside the display area 1, the low mobility of the display panel can be avoided, preventing it from supporting a large demultiplexing ratio. This allows for a significantly reduced number of traces connected to the driver chip 21, and consequently, a much smaller number of driver chips 21 are eliminated, resulting in a substantial reduction in bezel size. Furthermore, this eliminates the drive insufficiency caused by the panel's inability to support large demultiplexing ratios, improving the display panel's operational stability.

[0074] In some embodiments, the demultiplexing chip 22 is a single-crystal silicon-based chip.

[0075] Here, the demultiplexing chip 22 can be a single-crystal silicon-based demultiplexing functional integrated chip with demultiplexing circuits, that is, the substrate material of the demultiplexing chip 22 is single-crystal silicon.

[0076] In related technologies, a-si panels and oxide panels have extremely low mobility and can only support demultiplexing functions with a maximum ratio of 1:3. Even if 12 driver chips 21 are set up, the fanout area still requires 11520 / (12*3) = 320 traces to connect each driver chip 21.

[0077] In one embodiment, based on the single-crystal silicon chip, the number of output channels of a single demultiplexing chip 22 is 3 to 300, that is, the ratio of the demultiplexing chips 22 is in the range of 1:(3 to 300). Specifically, the ratio of the demultiplexing chips 22 is at least 1:3 and at most 1:300. Preferably, the ratio is 1:288, in which case only one driver chip 21 COF-IC is needed. When using two demultiplexing chips 22, each demultiplexing chip 22 only requires 20 second signal lines 4 to connect to the driver chip 21.

[0078] Thus, a chip based on single-crystal silicon with independently integrated demultiplexing function can avoid the inability to support high-ratio demultiplexing function in display area 1 due to the extremely low mobility of the panel. The high mobility of silicon can support a ratio of up to 1:300, greatly reducing the number of traces and eliminating the need for a large number of COF-ICs, thereby significantly reducing the space occupied by the bezel.

[0079] In some embodiments, the more demultiplexing chips 22 there are, the fewer second signal lines 4 each demultiplexing chip 22 corresponds to.

[0080] Here, with the same display panel resolution and the same demultiplexing ratio, the more demultiplexing chips 22 there are, the fewer second signal lines 4 are required for each demultiplexing chip 22, and the greater the reduction in bezel size.

[0081] In one embodiment, the higher the ratio of the demultiplexing chip 22, the fewer the number of the second signal lines 4.

[0082] Here, with the same display panel resolution and the same number of demultiplexing chips 22, the higher the ratio of demultiplexing chips 22, the fewer second signal lines 4 are required for each demultiplexing chip 22, and the greater the reduction in bezel size.

[0083] In one embodiment, the display panel has a resolution of 4K, the number of output channels of a single demultiplexing chip 22 is 288, the number of demultiplexing chips 22 is 2, the second signal line 4 includes a plurality of second signal line groups, the number of the second signal line groups is equal to the number of demultiplexing chips 22, and the number of signal lines in each second signal line group is 20.

[0084] Here, each demultiplexing chip 22 can be connected to the driver chip 21 through a second signal line group, and the second signal line group connected to different demultiplexing chips 22 is different.

[0085] In one embodiment, the number of demultiplexing chips 22 can be determined based on the size of the demultiplexing chips 22 and the size of the display area 1. For example, it can be determined based on the size of the demultiplexing chips 22 and the length of the side of the demultiplexing chip 22 closest to the display area 1.

[0086] In one embodiment, the number of demultiplexing chips 22 is greater than one. That is, when the display panel contains multiple demultiplexing chips 22, the demultiplexing chips 22 are arranged side by side along the edge of the nearest display area 1, and the total length of the multiple demultiplexing chips 22 along the edge of the nearest display area 1 does not exceed the length of that edge. Alternatively, the total length of the multiple demultiplexing chips 22 along the edge of the nearest display area 1 does not exceed the length of that edge, and the difference between the total length and the length of that edge is within a predetermined range, such as not exceeding a predetermined threshold. In this way, the number of demultiplexing chips 22 can be increased to further reduce the number of traces required for each demultiplexing chip 22, and the multiple demultiplexing chips 22 arranged side by side will not generate a larger space occupation in the vertical direction, nor will they exceed the length of the display area 1 in the horizontal direction, resulting in an increase in the bezel size.

[0087] In one embodiment, the number of demultiplexing chips 22 may be less than a predetermined number, wherein the predetermined number may refer to the maximum number of demultiplexing chips 22 that can be arranged side by side along the parallel direction of the nearest edge of the display area 1, for example, 3.

[0088] In this way, the number of demultiplexing chips 22 can be increased, thereby further reducing the number of signal lines required for each demultiplexing chip 22, and further reducing the space occupied in the bezel area.

[0089] In some embodiments, the display area 1 is connected to the first terminal of the first transistor 221 in the at least one demultiplexing chip 22 via the first signal line 3 with a 1:1 routing ratio.

[0090] For example, the input / output ports of display area 1 are connected to the first terminal of the first transistor 221 in at least one demultiplexing chip 22 via the first signal line 3 with a 1:1 wiring ratio.

[0091] In one embodiment, the demultiplexing chip 22 can be attached to the display panel, so that the first end of the demultiplexing chip 22 and the first fan-out area formed by the display area 1 based on a 1:1 wiring ratio will not affect the vertical dimension, that is, it will not affect the dimension of the bezel area.

[0092] In one embodiment, the demultiplexing chip 22 may include one or more demultiplexing circuits, and the wiring ratio connecting the input / output ports to the first end of the at least one demultiplexing chip 22 may also be determined according to the number of demultiplexing circuit stages included in the demultiplexing chip 22.

[0093] In one embodiment, the demultiplexing chip 22 may include one or more demultiplexing circuits, and the ratio of at least one demultiplexing chip 22 may also be determined according to the number of demultiplexing circuit stages included in the demultiplexing chip 22.

[0094] In this way, by dividing the fan-out area into two parts and connecting them in the middle with the demultiplexing chip 22, the design can be carried out without changing the area where the fan-out area is located, reducing changes to the original product design and significantly reducing the bezel size.

[0095] In some embodiments, when the number of demultiplexing chips 22 is greater than 1, the multiple demultiplexing chips 22 are arranged side by side with respect to the edge of the display area 1 closest to the driver chip 21 and along the parallel direction of the edge.

[0096] In one embodiment, when the number of demultiplexing chips 22 is greater than 1, the display panel includes multiple demultiplexing chips 22, i.e., two or more. The display area 1 can be rectangular, and the multiple demultiplexing chips 22 can be arranged close to one side of the display area 1 and side by side along the parallel direction of the side.

[0097] In one embodiment, the length direction of the demultiplexing chip 22 can be parallel to the edge of the nearest display area 1. Because the length direction of the demultiplexing chip 22 is close to and parallel to the display area 1, the area connected between the display area 1 and the first end of the demultiplexing chip 22, i.e., the first fan-out area, receives a significant reduction in both the frame and trace resistance.

[0098] In one embodiment, the thickness direction of the demultiplexing chip 22 can be parallel to the edge of the nearest display area 1. The length direction of the demultiplexing chip 22 is close to and parallel to the display area 1, so the area connected between the display area 1 and the first end of the demultiplexing chip 22, i.e., the first fan-out area, has a larger reduction in the frame and trace resistance.

[0099] In one embodiment, the demultiplexing chip 22 is close to the side, which can mean that the demultiplexing chip 22 is set close to the side, or that the distance between the demultiplexing chip 22 and the side does not exceed a predetermined value.

[0100] In one embodiment, the area where the second end of the demultiplexing chip 22 is connected to the driver chip 21 via the second signal line 4 constitutes the second fan-out area, and all the second fan-out areas corresponding to the demultiplexing chips 22 are arranged side by side along the parallel direction of the edge.

[0101] In one embodiment, the area where the display area 1 is connected to the first end of the demultiplexing chip 22 constitutes a first fan-out area, and all the first fan-out areas corresponding to the demultiplexing chips 22 are arranged side by side along the parallel direction of the edge.

[0102] Thus, the demultiplexing chip 22 is close to the display area 1. Therefore, the area connected between the display area 1 and the first end of the demultiplexing chip 22, i.e. the first fan-out area, has a significantly reduced frame area and trace resistance. Furthermore, the multiple demultiplexing chips 22 are arranged parallel to the edge of the display area 1. The signal lines of the multiple demultiplexing chips 22 connected to the driver chip 21 do not overlap vertically. On the basis of greatly reducing the number of traces, even if the number of demultiplexing chips 22 is increased, it will only further reduce the number of traces without indirectly increasing the area occupied by the traces, thereby better reducing the frame space occupied by the traces.

[0103] In some embodiments, the display area 1 is an amorphous silicon (a-si) semiconductor panel or a metal oxide (oxide) semiconductor panel. Due to the low mobility of a-si and oxide panels in related technologies, demultiplexing circuits cannot be applied to the flexible circuit board within the panel, or can only be applied at a maximum ratio of 1:3.

[0104] In this embodiment, based on the independent setting of the demultiplexing chip 22, preferably based on the single-crystal silicon-based demultiplexing chip 22, it is no longer constrained by the mobility of the panel itself. The a-si panel and the oxide panel can also be connected to the driver chip 21 through a larger ratio of demultiplexing, thereby greatly reducing the number of signal traces.

[0105] This application also provides a display device, wherein the display device includes the display panel described in any one or more of the foregoing embodiments.

[0106] Here, the display device can be any device with display function, such as a mobile phone, watch, tablet, television or computer.

[0107] As one possible implementation, a display device is provided, such as Figure 8 and 9 As shown, a new demultiplexing chip, namely demultiplexing chip 22, is added to take advantage of the ultra-high mobility of single-crystal silicon of 1000-1500. Figure 8 It contains two demultiplexing chips. Figure 9 It includes one demultiplexing IC. In this embodiment, the demultiplexing circuit is designed separately on the demultiplexing chip. Because the demultiplexing circuit is simple, the cost and size of the demultiplexing chip are extremely small. By using a demultiplexing chip + COF-IC design, the number of COF-ICs can be reduced to one, while the bezel is reduced by more than 2 / 3.

[0108] Taking a 4K resolution panel as an example, a design using one COF-IC and two demultiplexing chips reduces the number of ICs from 12 to just one. The fanout area is divided into two sections. Since the mobility of monocrystalline silicon is more than 100 times that of oxide, using the demultiplexing chip 22 can achieve a 1:300 ratio, for example, a 1:288 ratio. Thus, the first fanout section (the connection between the COF-IC and the demultiplexing IC) requires only 20*2 traces. The number of traces is reduced from 960 to 20, resulting in a significantly smaller bezel. The second fanout section, the first fanout area, uses a 1:1 ratio to connect to display area 1, requiring 3840*3 traces. Because multiple demultiplexing chips can be used here, and their length and distance are close to display area 1, the bezel and resistance of this section are very low, further reducing the bezel size.

[0109] Additionally, the number of demultiplexing chips used can range from 1 to n ICs; the more chips used, the more pronounced the narrow bezel effect. This embodiment not only significantly reduces the number of COF-ICs required but also achieves extremely narrow bezels. Furthermore, existing a-Si semiconductor panels that cannot use demultiplexing technology can also utilize it, resulting in substantial cost savings. With further increases in resolution, such as 8K and 6K technologies, the cost savings become even more significant.

[0110] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0111] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

[0112] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area. The non-display area includes a driver chip, at least one demultiplexing chip, and at least one first switch module for inputting a predetermined high level. The demultiplexing chip includes at least one first transistor, and each output channel of the demultiplexing chip is provided with one first transistor. The display area is connected to the first terminal of the first transistor via a first signal line, and one first signal line connects to one first transistor; the second terminal of the first transistor is connected to the driving chip via a second signal line, and one second signal line connects to multiple first transistors; the gate of the first transistor is connected to the first switching module. The non-display area includes a first fan-out area and a second fan-out area. The first fan-out area includes the first signal line, and the second fan-out area includes the second signal line. The number of the first signal lines is equal to the product of the number of the second signal lines, the number of the demultiplexing chips, and the number of output channels of a single demultiplexing chip.

2. The display panel according to claim 1, characterized in that, When the number of demultiplexing chips is greater than 1, one of the first switch modules is simultaneously connected to the gate of one of the first transistors in each of the demultiplexing chips.

3. The display panel according to claim 1 or 2, characterized in that, The non-display area further includes: at least one second switch module for inputting a predetermined high level; each of the demultiplexing chips further includes: at least one second transistor; the gate of one of the second transistors is connected to one of the second switch modules; In one of the demultiplexing chips, the first terminal of a second transistor is connected to the second terminals of a predetermined number of first transistors, and the second terminals of the second transistors are connected to the driver chip via a second signal line. The number of first transistors is equal to the product of the number of second transistors and the predetermined number.

4. The display panel according to claim 3, characterized in that, When the number of demultiplexing chips is greater than 1, one of the second switching modules is simultaneously connected to the gate of one of the second transistors in each of the demultiplexing chips.

5. The display panel according to claim 1, characterized in that, The number of output channels of a single demultiplexing chip is 3 to 300.

6. The display panel according to claim 1, characterized in that, The display panel has a resolution of 4K, the number of output channels of a single demultiplexing chip is 288, the number of demultiplexing chips is 2, the second signal line includes multiple second signal line groups, the number of second signal line groups is equal to the number of demultiplexing chips, and the number of signal lines in each second signal line group is 20.

7. The display panel according to claim 1, characterized in that, The display area is connected to the first terminal of the first transistor in the at least one demultiplexing chip via the first signal line with a 1:1 routing ratio.

8. The display panel according to claim 1, characterized in that, When the number of demultiplexing chips is greater than 1, the demultiplexing chips are arranged side by side with the display area closest to the driver chip along the direction parallel to the edge.

9. The display panel according to claim 1, characterized in that, The display panel is an amorphous silicon semiconductor panel or a metal oxide semiconductor panel.

10. A display device, characterized in that, The display device comprises the display panel according to any one of claims 1 to 9.

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