A high-bandwidth flash memory chip and electronic device
By employing a vertical stacking structure of storage array layer and functional circuit layer in high-bandwidth flash memory chips, and utilizing a vertical interconnect structure to achieve direct connection between storage cells and sensitive amplifier circuits, the problem of large area occupation of sensitive amplifiers and input/output interfaces is solved, achieving higher data bandwidth and storage density, reducing latency and resistance, and making it suitable for artificial intelligence training servers and high-speed solid-state drives.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- LIANHE STORAGE (BEIJING) TECHNOLOGY CO LTD
- Filing Date
- 2025-07-11
- Publication Date
- 2026-07-21
AI Technical Summary
In high-bandwidth flash memory chips, sensitive amplifiers and input/output interface circuits occupy a large amount of layout area, resulting in problems such as large chip area, long signal transmission path, and high latency.
The system employs a top-level memory array layer and a bottom-level functional circuit layer. A vertical interconnect structure enables direct connection between the memory cells and the sensitive amplifier circuit. Copper interconnects are used to connect the sensitive amplifier circuit and the input/output interface circuit on the same layer. Tungsten via arrays are used to maximize the use of vertical space.
It effectively reduces chip area by 28%, shortens signal transmission path by 40%, increases data bandwidth by 42.9%, increases storage density per unit area by 35%, reduces via resistance by 50%, improves read/write endurance, and reduces latency to 15ns, meeting PCIe 5.0 protocol requirements.
Smart Images
Figure CN224536703U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of storage technology, and in particular to a high-bandwidth flash memory chip and electronic device. Background Technology
[0002] In NAND flash products, data is stored in an array of storage cells. When a user reads data, the data is transmitted from the array to the sensitive amplifier and then to the input / output interface.
[0003] In current product designs, the sensitive amplifier and input / output interfaces are located next to the memory array, occupying separate layout areas. High-bandwidth flash memory chips contain multiple arrays and corresponding sensitive amplifier and input / output interface circuits; these two circuit components account for a significant portion of the total chip area. Utility Model Content
[0004] In view of this, the purpose of this utility model is to provide a high-bandwidth flash memory chip and electronic device to solve the problems mentioned in the background art.
[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0006] A high-bandwidth flash memory chip includes a top-level memory array layer, a bottom-level functional circuit layer, and a vertical interconnect structure. The memory array layer includes multiple rows and columns of memory cells. The functional circuit layer includes horizontally adjacent sensitive amplifier circuits and input / output interface circuits. The vertical interconnect structure extends through the memory array layer and the functional circuit layer, enabling direct connection between the memory cells and the sensitive amplifier circuits.
[0007] Furthermore, the sensitive amplifier circuit and the input / output interface circuit are connected on the same layer via copper interconnects, with an interconnect density ≥10. 4 Line / mm 2 .
[0008] Furthermore, the projected area overlap between the storage array layer and the functional circuit layer is ≥90%, and the vertical interconnect structure is a tungsten via array.
[0009] Furthermore, the aspect ratio of the vertical interconnect structure is ≥10:1, and the via diameter is ≤100nm.
[0010] Furthermore, a phosphorus-doped polysilicon layer is provided on the surface of the functional circuit layer, the thickness of the phosphorus-doped polysilicon layer being ≤20 nm and the concentration ranging from 1×10⁻⁶. 20 -1×10 22 atoms / cm 3 A storage array layer is formed on the surface of the phosphorus-doped polycrystalline silicon layer.
[0011] An electronic device including a high-bandwidth flash memory chip.
[0012] Furthermore, the electronic device is an artificial intelligence training server or a high-speed solid-state drive.
[0013] The beneficial effects of this utility model are:
[0014] This invention provides a high-bandwidth flash memory chip, comprising a top-level memory array layer, a bottom-level functional circuit layer, and a vertical interconnect structure. The memory array layer includes multiple rows and columns of memory cells. The functional circuit layer includes horizontally adjacent sensitive amplifier circuits and input / output interface circuits. The vertical interconnect structure penetrates the memory array layer and the functional circuit layer, enabling direct connection between the memory cells and the sensitive amplifier circuits. This structure forms a vertically stacked structure between the functional circuit layer and the memory array layer, effectively reducing the chip area by 28%, shortening the signal transmission path by 40%, and reducing the latency to 15ns. Attached Figure Description
[0015] Figure 1 The diagram shown is a structural schematic of a high-bandwidth flash memory chip according to this utility model;
[0016] Explanation of icon numbers:
[0017] 1-Functional circuit layer; 11-Sensitive amplifier circuit; 12-Input / output interface circuit; 2-Storage array layer; 3-Vertical interconnect structure. Detailed Implementation
[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments:
[0019] like Figure 1 As shown, the present invention provides a high-bandwidth flash memory chip, including a top-level storage array layer, a bottom-level functional circuit layer, and a vertical interconnect structure; the storage array layer includes multiple rows and columns of storage cells; the functional circuit layer includes horizontally adjacent sensitive amplifier circuits and input / output interface circuits; the vertical interconnect structure penetrates the storage array layer and the functional circuit layer, realizing direct connection between the storage cells and the sensitive amplifier circuits.
[0020] The beneficial effects of this utility model are:
[0021] This invention provides a high-bandwidth flash memory chip, comprising a top-level memory array layer, a bottom-level functional circuit layer, and a vertical interconnect structure. The memory array layer includes multiple rows and columns of memory cells. The functional circuit layer includes horizontally adjacent sensitive amplifier circuits and input / output interface circuits. The vertical interconnect structure penetrates the memory array layer and the functional circuit layer, enabling direct connection between the memory cells and the sensitive amplifier circuits. This structure forms a vertically stacked structure between the functional circuit layer and the memory array layer, effectively reducing the chip area by 28%, shortening the signal transmission path by 40%, and reducing the latency to 15ns.
[0022] Furthermore, the sensitive amplifier circuit and the input / output interface circuit are connected on the same layer via copper interconnects, with an interconnect density ≥10. 4 Line / mm 2 .
[0023] As described above, the above method can avoid cross-layer interconnect capacitors and increase data bandwidth by 42.9% to 400GB / s.
[0024] Furthermore, the projected area overlap between the storage array layer and the functional circuit layer is ≥90%, and the vertical interconnect structure is a tungsten via array.
[0025] As can be seen from the above description, the above method can maximize the use of vertical space and increase the storage density per unit area by 35%.
[0026] Furthermore, the aspect ratio of the vertical interconnect structure is ≥10:1, and the via diameter is ≤100nm.
[0027] As described above, the via resistance is reduced by 50% using this method, supporting 10 10 Read / write endurance.
[0028] Furthermore, a phosphorus-doped polysilicon layer is provided on the surface of the functional circuit layer, the thickness of the phosphorus-doped polysilicon layer being ≤20 nm and the concentration ranging from 1×10⁻⁶. 20 -1×10 22 atoms / cm 3 A storage array layer is formed on the surface of the phosphorus-doped polycrystalline silicon layer.
[0029] An electronic device including a high-bandwidth flash memory chip.
[0030] As described above, it is suitable for AI servers, achieving 800GB / s board-level storage bandwidth.
[0031] Furthermore, the electronic device is an artificial intelligence training server or a high-speed solid-state drive.
[0032] As described above, the electronic device is a high-speed solid-state drive with read / write latency reduced to 15μs (traditional 22μs), meeting the requirements of the PCIe 5.0 protocol.
[0033] The following are several preferred embodiments or application embodiments to help those skilled in the art better understand the technical content of this utility model and the technical contributions made by this utility model compared with the prior art:
[0034] Preferred embodiment 1:
[0035] like Figure 1 As shown, the present invention provides a high-bandwidth flash memory chip, including a top storage array layer 2, a bottom functional circuit layer 1, and a vertical interconnect structure 3; the storage array layer 2 includes multiple rows and columns of storage cells; the functional circuit layer 1 includes horizontally adjacent sensitive amplifier circuits 11 and input / output interface circuits 12; the vertical interconnect structure 3 penetrates the storage array layer 2 and the functional circuit layer 1, realizing direct connection between the storage cells and the sensitive amplifier circuits.
[0036] The sensitive amplifier circuit 11 and the input / output interface circuit 12 are connected on the same layer via copper interconnects, with an interconnect density ≥10. 4 Line / mm 2 By using the above method, cross-layer interconnect capacitors can be avoided, and data bandwidth is increased by 42.9% to 400GB / s (compared to the traditional 280GB / s).
[0037] The projected area overlap between the storage array layer and the functional circuit layer is ≥90%, and the vertical interconnect structure is a tungsten via array. This approach maximizes the utilization of vertical space, increasing storage density per unit area by 35%.
[0038] The aspect ratio of the vertical interconnect structure is ≥10:1, and the via diameter is ≤100nm. Through this method, the via resistance is reduced by 50%, supporting 10 10 Read / write endurance.
[0039] A phosphorus-doped polysilicon layer is disposed on the surface of the functional circuit layer, the thickness of the phosphorus-doped polysilicon layer being ≤20 nm and the concentration ranging from 1×10⁻⁶. 20 -1×10 22 atoms / cm 3 A storage array layer is formed on the surface of the phosphorus-doped polycrystalline silicon layer.
[0040] Specifically: depositing a phosphorus-doped polycrystalline silicon layer with a thickness ≤20nm and a concentration ranging from 1×10⁻⁶. 20 -1×10 22 atoms / cm 3(i.e., between 1e20 and 1e22); the polysilicon layer is grown using furnace deposition. The deposition temperature range for the polysilicon layer is 500℃-700℃, preferably 510℃; the resistivity is 100±5 ohms / cubic meter. Low-temperature processing reduces the thermal budget by 30%, preventing performance degradation of underlying circuitry. Due to grain boundary leakage issues in polysilicon, the thickness of the polysilicon layer needs to be controlled to no more than 20nm to suppress leakage. In this design, the polysilicon layer thickness is preferably 10nm.
[0041] Preferred embodiment two:
[0042] An electronic device includes a high-bandwidth flash memory chip as described in Embodiment 1 above, making the electronic device suitable for AI servers and achieving 800GB / s board-level storage bandwidth.
[0043] The electronic device is either an artificial intelligence training server or a high-speed solid-state drive. If the electronic device is a high-speed solid-state drive, the read / write latency is reduced to 15μs (traditional 22μs), meeting the PCIe 5.0 protocol requirements.
[0044] This utility model has been described with reference to the above-described embodiments and accompanying drawings. However, the above embodiments are merely examples for implementing this utility model. It must be noted that the disclosed embodiments do not limit the scope of this utility model. On the contrary, modifications and equivalent provisions included in the spirit and scope of the claims are all included within the scope of this utility model.
Claims
1. A high-bandwidth flash memory chip, characterized in that, It includes a top-level memory array layer, a bottom-level functional circuit layer, and a vertical interconnect structure; the memory array layer includes multiple rows and columns of memory cells; the functional circuit layer includes horizontally adjacent sensitive amplifier circuits and input / output interface circuits; the vertical interconnect structure runs through the memory array layer and the functional circuit layer, realizing a direct connection between the memory cells and the sensitive amplifier circuits.
2. The high-bandwidth flash memory chip according to claim 1, characterized in that, The sensitive amplifier circuit and the input / output interface circuit are connected on the same layer via copper interconnects, with an interconnect density ≥10. 4 Line / mm 2 .
3. A high-bandwidth flash memory chip according to claim 1, characterized in that, The projected area overlap between the storage array layer and the functional circuit layer is ≥90%, and the vertical interconnect structure is a tungsten via array.
4. A high-bandwidth flash memory chip according to claim 3, characterized in that, The aspect ratio of the vertical interconnect structure is ≥10:1, and the diameter of the via is ≤100nm.
5. A high-bandwidth flash memory chip according to claim 1, characterized in that, A phosphorus-doped polysilicon layer is disposed on the surface of the functional circuit layer, the thickness of the phosphorus-doped polysilicon layer being ≤20 nm and the concentration ranging from 1×10⁻⁶. 20 -1×10 22 atoms / cm 3 A storage array layer is formed on the surface of the phosphorus-doped polycrystalline silicon layer.
6. An electronic device, characterized in that, Includes the high-bandwidth flash memory chip as described in any one of claims 1-5.
7. The electronic device according to claim 6, characterized in that, The electronic device is an artificial intelligence training server or a high-speed solid-state drive.