Shunt resistor, detection chip

Abstract

The utility model discloses a shunt resistor, detection chip, shunt resistor includes the interconnection layer that presses together, second insulating layer, first shunt resistance layer, first insulating layer, second shunt resistance layer, third insulating layer and the conductive layer with pin, first shunt resistance layer has first resistance line for forming first shunt resistance, second shunt resistance layer has second resistance line for forming second shunt resistance, the thickness of second resistance line is greater than the thickness of first resistance line, and the width of second resistance line is greater than the width of first resistance line. In this application, because first shunt resistance and second shunt resistance are arranged in the same substrate, the first shunt resistance layer and the second shunt resistance layer have the same temperature coefficient, when it is applied to current detection, the current to be measured is shunted through two shunt resistors with the same temperature coefficient, which can reduce the influence of temperature drift on current detection accuracy.

Description

Technical Field

[0001] This utility model relates to the field of shunt resistor technology, and in particular to a shunt resistor and a detection chip. Background Technology

[0002] In the field of current sensing technology, shunt resistors are key components for current measurement, and their performance directly affects the accuracy and reliability of current detection. Currently, most shunt resistors in existing technologies are made of manganese copper. Manganese copper, with its good temperature characteristics, can ensure the performance stability of shunt resistors under different temperature environments to a certain extent, and is widely used in various current sensing scenarios. However, manganese copper has the problem of large resistance differences between individual units. This means that even when using manganese copper shunt resistors of the same specifications, their actual resistance values ​​may deviate significantly during actual production and application, thus adversely affecting the accuracy of current detection and making it difficult to meet the requirements of high-precision current sensing.

[0003] In addition, in some applications, lead frames within integrated circuit packages are used as shunt resistors. While this approach simplifies the circuit structure and reduces costs to some extent, the lead frames themselves have significant drawbacks. Firstly, the resistance of the lead frame is typically small, making it difficult to control its resistance accuracy during manufacturing and achieving precise resistance settings. Secondly, the temperature coefficient of resistance in the lead frame is large, meaning its resistance changes significantly with temperature, leading to substantial errors in current detection results. To ensure detection accuracy, additional temperature compensation circuits or complex temperature compensation algorithms must be added, increasing both circuit design complexity and production costs, thus limiting the widespread adoption of this approach in cost- and circuit-complex-sensitive applications.

[0004] Therefore, a new shunt resistor needs to be proposed to solve the above problems. Utility Model Content

[0005] In view of the above problems, the purpose of this utility model is to provide a shunt resistor and a detection chip, thereby reducing the impact of temperature drift on the accuracy of current detection.

[0006] According to a first aspect of the present invention, a shunt resistor is provided, comprising an interconnect layer, a second insulating layer, a first shunt resistor layer, a second shunt resistor layer, a third insulating layer, and a conductive layer with leads, all laminated together. The first insulating layer is located between the first shunt resistor layer and the second shunt resistor layer, the second insulating layer is located between the first shunt resistor layer and the interconnect layer, and the third insulating layer is located between the second shunt resistor layer and the conductive layer. The interconnect layer is used to interconnect the shunt resistor with a current-sensing operational amplifier. The first shunt resistor layer has a first resistance line for forming a first shunt resistor. The second shunt resistor layer has a second resistance line for forming a second shunt resistor. The thickness of the second resistance line is greater than the thickness of the first resistance line, and the width of the second resistance line is greater than the width of the first resistance line.

[0007] Optionally, the first shunt resistor layer further includes a first contact terminal and a second contact terminal. The first resistance wire is connected to the first contact terminal and the second contact terminal. The first resistance wire extends in a zigzag pattern between the first contact terminal and the second contact terminal. The first resistance wire includes a plurality of first bends and a plurality of first straight sections. The first contact terminal is the first end of the first shunt resistor, and the second contact terminal is the second end of the first shunt resistor. The second resistance wire includes a plurality of second bends and a plurality of second straight sections. The extension direction of the first straight sections is perpendicular to the extension direction of the second straight sections.

[0008] Optionally, the conductive layer includes a plurality of first pins corresponding to the plurality of second straight sections, as well as second pins, third pins, and fourth pins. Each first pin is connected to its corresponding second straight section via a connecting hole. The second pin is connected to the first end of the second shunt resistor via at least one first pin. The second contact terminal is electrically connected to the second pin via a conductive channel and is also electrically connected to an external circuit via the second pin. The third pin is connected to the second end of the second shunt resistor via at least one first pin. The connecting lines between the first pin, the second pin, and the third pin are of equal length. The first contact terminal is electrically connected to the fourth pin via a conductive channel and is also electrically connected to an external circuit via the fourth pin. The plurality of first pins connected to an odd number of second straight sections are short-circuited through a first printed circuit board and serve as the first end of the second shunt resistor. The plurality of first pins connected to an even number of second straight sections are short-circuited through a second printed circuit board and serve as the second end of the second shunt resistor.

[0009] Optionally, the first pin is narrower near the connection hole than it is far from the connection hole.

[0010] Optionally, the shunt resistor further includes a solder resist layer disposed on the surface of the interconnect layer and the conductive layer in areas where external connections are not required; and a nickel-gold layer disposed on the surface of the interconnect layer and the conductive layer in areas where external connections are required.

[0011] Optionally, the resistance ratio between the first shunt resistor and the second shunt resistor is greater than or equal to 10000:1.

[0012] Optionally, the insulating materials of the first insulating layer, the second insulating layer, and the third insulating layer include prepreg, polyimide, and encapsulating molding compound.

[0013] Optionally, both the first shunt resistor layer and the second shunt resistor layer are made of copper foil.

[0014] Optionally, both the first shunt resistor layer and the second shunt resistor layer are multilayered.

[0015] According to a second aspect of the present invention, a detection chip is provided, comprising: a shunt resistor as described above; and a current detection chip, the current detection chip including a current detection operational amplifier, the current detection chip being electrically connected to the interconnect layer of the shunt resistor, wherein the current detection chip and the shunt resistor are packaged together, the negative input terminal of the current detection operational amplifier is connected to the second terminal of the second shunt resistor, the positive input terminal of the current detection operational amplifier is connected to the first terminal of the first shunt resistor, and the second terminal of the first shunt resistor is connected to the first terminal of the second shunt resistor.

[0016] This utility model provides a shunt resistor and a detection chip. The shunt resistor includes an interconnect layer, a second insulating layer, a first shunt resistor layer, a second shunt resistor layer, a third insulating layer, and a conductive layer with leads, all laminated together. The first shunt resistor layer has a first resistance line for forming a first shunt resistor; the second shunt resistor layer has a second resistance line for forming a second shunt resistor; the thickness of the second resistance line is greater than the thickness of the first resistance line, and the width of the second resistance line is greater than the width of the first resistance line. In this application, because the first and second shunt resistors are disposed in the same substrate, the first and second shunt resistor layers have the same temperature coefficient. When applied to current detection, the current to be measured is shunted through two shunt resistors with the same temperature coefficient, which can reduce the impact of temperature drift on the accuracy of current detection. Furthermore, the detection chip integrates the shunt resistor and the current detection chip, allowing for precise calibration at the factory, thereby improving the accuracy of current detection while reducing the difficulty of using the current detection chip. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A flowchart illustrating a method for manufacturing a shunt resistor according to an embodiment of the present invention is shown;

[0019] Figure 2 It shows the use of Figure 1 A longitudinal cross-sectional view of the shunt resistor formed by the manufacturing method;

[0020] Figure 3 A top view of the first shunt resistor layer according to an embodiment of the present invention is shown;

[0021] Figure 4 A top view of a portion of a shunt resistor according to an embodiment of the present invention is shown. Detailed Implementation

[0022] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0023] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0024] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0025] In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing the memory device, including all layers or regions that have been formed. Many specific details of the present invention, such as the device structure, materials, dimensions, processing techniques, and methods, are described below to provide a clearer understanding of the present invention. However, as those skilled in the art will understand, the present invention may be implemented without adhering to these specific details.

[0026] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] Figure 1 A flowchart illustrating a method for manufacturing a shunt resistor according to an embodiment of the present invention is shown.

[0028] See Figure 1 This utility model provides a method for manufacturing a shunt resistor, including steps S1-S8.

[0029] In step S1, the first metal layer, the first insulating layer, and the second metal layer are pressed together, with the first insulating layer located between the first metal layer and the second metal layer, and the thickness of the second metal layer being greater than the thickness of the first metal layer.

[0030] When pressing the first metal layer, the first insulating layer and the second metal layer together, the pressing tools can be traditional hot presses, vacuum laminators, vacuum fast presses, roller presses, hydraulic presses, flat vulcanizing machines, etc.

[0031] Preferably, a vacuum laminator is used for pressing. The vacuum laminator mainly controls parameters such as temperature, time, and pressure to solidify the layer to be pressed. The pressing temperature is divided into a heating section, a constant temperature section, and a cooling section. The corresponding process parameters are as follows: heating section temperature from room temperature to 130℃, heating section pressure 10kg / cm²; constant temperature section temperature 220℃, constant temperature section pressure 25kg / cm², constant temperature section time 90 min; cooling section temperature from 220℃ to room temperature, cooling section pressure 25kg / cm². The entire pressing process is carried out in a vacuum environment.

[0032] In step S2, the first metal layer is etched to obtain a first shunt resistor layer with a first resistance line, and the second metal layer is etched to obtain a second shunt resistor layer with a second resistance line, wherein the width of the second resistance line is greater than the width of the first resistance line.

[0033] The top view of the first shunt resistor layer obtained by etching is as follows: Figure 3 As shown, a top view of the etched second shunt resistor layer is as follows: Figure 4 As shown in 130.

[0034] In step S3, a second insulating layer and a third metal layer are sequentially covered on the side of the first shunt resistor layer away from the second shunt resistor layer, and a third insulating layer and a fourth metal layer are sequentially covered on the side of the second shunt resistor layer away from the first shunt resistor layer, and the first to second shunt resistor layers, the first to third insulating layers, and the third to fourth metal layers are pressed together.

[0035] The pressing tools can include traditional hot presses, vacuum laminators, vacuum fast presses, roller presses, hydraulic presses, and flat vulcanizing machines.

[0036] Preferably, a vacuum laminator is used for lamination. Since the first shunt resistor layer and the second shunt resistor layer have already undergone pattern etching in step S3, and from... Figure 2 The cross-sectional view shows a height difference, so the mold surface in contact with the third and fourth metal layers should be smooth and flat during pressing and curing. The pressing temperature of the press is divided into a heating section, a constant temperature section, and a cooling section, with the corresponding process parameters as follows: heating section temperature from room temperature to 130℃, heating section pressure 10kg / cm²; constant temperature section temperature 220℃, constant temperature section pressure 25kg / cm², constant temperature section time 90 min; cooling section temperature 220℃ to room temperature, cooling section pressure 25kg / cm². The entire pressing process is carried out in a vacuum environment.

[0037] In step S4, holes are drilled at multiple preset positions in the third metal layer to form multiple through holes penetrating the third metal layer, the second insulating layer, the first shunt resistor layer, the first insulating layer, the second shunt resistor layer, the third insulating layer, and the fourth metal layer, and holes are drilled at multiple preset positions in the fourth metal layer to form multiple blind holes ending at the second shunt resistor layer.

[0038] Multiple through holes are formed by mechanical drilling, while multiple blind holes are formed by laser drilling.

[0039] In step S5, multiple through holes are filled with conductive material to obtain multiple conductive channels, and multiple blind holes are filled with conductive material to obtain multiple connection holes.

[0040] The filling process for the conductive material can be solid electroplating or coating with conductive paste, etc., and this application does not impose specific limitations. When using solid electroplating to fill through holes and blind holes, the third and fourth metal layers will be thickened after filling.

[0041] In step S6, the third metal layer is etched to obtain an interconnect layer for chip electrical connection, and the fourth metal layer is etched to obtain a conductive layer with pins.

[0042] The top view of the etched conductive layer is as follows: Figure 4 As shown in 140.

[0043] In step S7, a solder resist layer is formed in the areas on the surfaces of the interconnect layer and the conductive layer where no external connection is required.

[0044] In step S8, nickel-gold treatment is performed on the areas on the surfaces of the interconnect layer and the conductive layer where external connections are required to obtain a nickel-gold layer.

[0045] The nickel-gold treatment can prevent oxidation of the areas on the surface of the interconnect and conductive layers that need to provide external connections, and it also facilitates subsequent soldering.

[0046] This application uses the above-mentioned substrate process to fabricate a substrate-type shunt resistor (i.e., a packaged substrate with integrated shunt resistors). Two shunt resistors with the same temperature coefficient are integrated in the same substrate. By shunting the current through the two resistors, the influence of temperature deviation can be resolved. In addition, the substrate shunt resistor design is flexible. By encapsulating the chip (such as a current detection chip) with the above-mentioned substrate, precise debugging of the product can be achieved at the factory, which improves the current detection accuracy and reduces the difficulty of use.

[0047] Figure 2 To adopt Figure 1 A longitudinal cross-sectional view of the shunt resistor formed by the manufacturing method; Figure 3 A top view of the first shunt resistor layer according to an embodiment of the present invention is shown; Figure 4 A top view of a portion of a shunt resistor according to an embodiment of the present invention is shown. Figure 2 From Figure 4 The cross-sectional view of the section cut by line AA.

[0048] See Figure 2 ,use Figure 1The shunt resistor 100, fabricated using the substrate process shown, includes an interconnect layer 110, a second insulating layer 172, a first shunt resistor layer 120, a first insulating layer 171, a second shunt resistor layer 130, a third insulating layer 173, and a conductive layer 140 with leads, all laminated together. The leads in the conductive layer 140 are used for external circuit connections. The first insulating layer 171 is located between the first shunt resistor layer 120 and the second shunt resistor layer 130. The second insulating layer 172 is located between the first shunt resistor layer 120 and the interconnect layer 110. The third insulating layer 173 is located between the second shunt resistor layer 130 and the conductive layer 140.

[0049] The first shunt resistor layer 120 has a first resistance line 123 for forming a first shunt resistor Rp, and the second shunt resistor layer 130 has a second resistance line for forming a second shunt resistor Rs. The resistance value of the first shunt resistor Rp is much greater than the resistance value of the second shunt resistor Rs.

[0050] In addition, the shunt resistor 100 also includes a nickel-gold layer 190 disposed on the conductive layer 140 and the areas on the surface of the interconnect layer 110 where external connections are required; and a solder mask layer 180 disposed on the interlayer gaps of the interconnect layer 110, the interlayer gaps of the conductive layer 140, and the areas on the surfaces of the interconnect layer 110 and the conductive layer 140 where external connections are not required.

[0051] Interconnect layer 110 is used to interconnect the shunt resistor 100 with a current sensing chip (not shown in the figure), which includes a current sensing operational amplifier. The shunt resistor 110 and the current sensing chip can be interconnected via flip chip, wire bonding, surface mount technology (SMT), or other methods. Multiple terminals of the current sensing chip are connected to the conductive layer 140 via conductive channels 160 for connection to external circuitry.

[0052] The second shunt resistor layer 130 and the conductive layer 140 are connected by a connection hole 150. For example, the connection hole 150 is a blind hole filled with conductive material. Preferably, the connection hole 150 in this application is formed using a solid electroplating process to increase the effective contact area between the second shunt resistor layer 130 and the conductive layer 140, and to reduce the contact resistance between them.

[0053] Furthermore, the first to third insulating layers 171-173 are made of materials with good thermal conductivity to ensure that the shunt resistor 100 has good heat dissipation effect, thereby making the temperature of the first shunt resistor layer 120 and the second shunt resistor layer 130 the same.

[0054] Furthermore, the first shunt resistor layer 120 and the second shunt resistor layer 130 are made of the same material to ensure that the resistors formed by them have the same temperature coefficient. This application does not specifically limit the materials used for the first shunt resistor layer 120 and the second shunt resistor layer 130, such as copper, manganin, constantan, nickel-chromium alloy, iron-chromium-aluminum alloy, etc.

[0055] Preferably, the interconnect layer 110, the first shunt resistor layer 120, the second shunt resistor layer 130, and the conductive layer 140 are all made of copper foil.

[0056] Furthermore, the resistance ratio between the first shunt resistor Rp and the second shunt resistor Rs is greater than or equal to 10000:1 to achieve high current detection. To ensure that the resistance ratio between the first shunt resistor Rp and the second shunt resistor Rs is greater than or equal to 10000:1, the thickness of the second resistance wire needs to be greater than the thickness of the first resistance wire 123, and the width of the second resistance wire needs to be greater than the width of the first resistance wire 123.

[0057] Because the thickness difference between the first resistance wire 123 and the second resistance wire is significant, it increases the risk of warping. Therefore, the first to third insulating layers 171-173 are preferably made of a mixture of materials to balance stress and avoid warping. For example, the insulating materials of the first to third insulating layers 171-173 include prepreg, polyimide, encapsulating molding compound, etc.

[0058] Furthermore, when a single-layer resistor layer cannot meet the resistance value requirements of the first shunt resistor Rp and the second shunt resistor Rs, the first shunt resistor layer 120 and the second shunt resistor layer 130 can be implemented using multiple layers, such as multiple layers of copper foil.

[0059] In addition, since the second shunt resistor layer 130 is relatively thick, its side will be curved during manufacturing, and its influence on the resistance value needs to be controlled during manufacturing.

[0060] See Figure 3 The first shunt resistor layer 120 further includes contact terminals 121 and 122, and a first resistance line 123 connected at both ends to contact terminals 121 and 122 respectively, wherein the first resistance line 123 extends in a zigzag pattern between contact terminals 121 and 122. Contact terminals 121 and 122 are respectively the first and second ends of the first shunt resistor Rp. Furthermore, the first shunt resistor layer 120 also includes a plurality of vias 124 through which conductive channels 160 pass. Contact terminals 121, 122, and the first resistance line 123 can be integrally formed or separately formed, preferably integrally formed. Because the first resistance line 123 is thin and fine, its influence on the resistance value needs to be controlled during circuit fabrication.

[0061] Furthermore, the first resistance line 123 is a multi-S-shaped trace, including multiple first bends 123a and multiple first straight sections 123b. It is understandable that, although... Figure 2 The example given is that the first resistor line 123 is a multi-S-shaped trace. However, in actual applications, the first resistor line 123 can also be a multi-Z-shaped trace, etc. This application does not make any specific limitation.

[0062] For ease of understanding, Figure 4 Only the second shunt resistor layer 130 and the conductive layer 140 are shown, which is a top view from the second shunt resistor layer 130 to the conductive layer 140.

[0063] See Figure 4 The second shunt resistor layer 130 is implemented using a tortuous second resistor line, wherein the second resistor line is a multi-S-shaped trace, and the second resistor line has multiple second bends 131 and multiple second straight sections 132. The extension direction of the first straight section 123b is perpendicular to the extension direction of the second straight section 132.

[0064] Understandably, although Figure 4 The example given is that the second resistor line is a multi-S-shaped trace, but in practical applications, the second resistor line can also be a multi-Z-shaped trace, etc. This application does not make any specific limitation.

[0065] Furthermore, the two outermost second straight sections 132 may also be provided with extension sections 133, which are used to measure the resistance value of the second shunt resistor Rs after the second resistance line is formed.

[0066] The conductive layer 140 includes a plurality of first pins 141, each corresponding to a plurality of second straight sections 132. Each first pin 141 is electrically connected to its corresponding second straight section 132 via a connection hole 150, allowing the current to be measured to flow into the second shunt resistor layer 130. Since the etching shape of the second straight section 132 is relatively controllable, providing the connection hole 150 here can effectively avoid the problem of ineffective interconnection between the second shunt resistor layer 130 and the conductive layer 140 due to the misalignment of the connection hole 150.

[0067] Furthermore, the connecting hole 150 can be of any shape, such as a circle, square, rectangle, polygon, etc. Preferably, the connecting hole 150 is rectangular.

[0068] Furthermore, the multiple first pins 141 connected to the odd number of second straight sections 132 are short-circuited (e.g., short-circuited through the first printed circuit board) and serve as the first end of the second shunt resistor Rs. The multiple first pins 141 connected to the even number of second straight sections 132 are short-circuited (e.g., short-circuited through the second printed circuit board) and serve as the second end of the second shunt resistor Rs. This allows the current to be measured to flow evenly through each section of the resistor, avoiding detection errors caused by uneven current.

[0069] Furthermore, the conductive layer 140 also includes a second pin 142 and a third pin 143. The second pin 142 is connected to a first terminal of the second shunt resistor Rs via at least one first pin 141 for electrical connection to an external circuit. The third pin 143 is connected to a second terminal of the second shunt resistor Rs via at least one first pin 141 for electrical connection to an external circuit. The contact terminal 122 of the first shunt resistor layer 120 is electrically connected to the second pin 142 via a conductive channel 160.

[0070] Furthermore, the conductive layer 140 also includes a fourth pin 144. The contact terminal 121 of the first shunt resistor layer 120 is connected to the fourth pin 144 via a conductive channel 160, and is electrically connected to an external circuit through the fourth pin 144.

[0071] Furthermore, the conductive layer also includes multiple fifth pins 145. The second pin 142, third pin 143, fourth pin 144, and fifth pin 145 can be electrically connected to some terminals in the current sensing chip via the conductive channel 160. For example, the third pin 143 is connected to the negative input terminal of the current sensing operational amplifier, and the fourth pin 144 is connected to the positive input terminal of the current sensing operational amplifier.

[0072] For example, when the number of multiple first pins 141 connected to the first printed circuit board / second printed circuit board is even, the second pin 142 / third pin 143 is connected to the two middle first pins 141 among the multiple first pins 141; when the number of multiple first pins 141 connected to the first printed circuit board / second printed circuit board is odd, the second pin 142 / third pin 143 is connected to the middle first pin 141 among the multiple first pins 141.

[0073] For example, the second resistor wire includes six second bends 131 and seven second straight sections 132. The first pin 141 connected to the first, third, fifth, and seventh second straight sections 132 is short-circuited via a first printed circuit board, and the first pin 141 connected to the second, fourth, and sixth second straight sections 132 is short-circuited via a second printed circuit board. The second pin 142 is connected to the first pin 141 connected to the third and fifth second straight sections 132, and the third pin 143 is connected to the first pin 141 connected to the fourth second straight section 132.

[0074] Furthermore, the connecting lines between the first pin 141 and the second pin 142 and the third pin 143 need to be of equal length and as narrow as possible to reduce the impact on the current sharing of the second shunt resistor layer 130.

[0075] Furthermore, the first pin 141 is narrower near the connection hole 150 than it is far from the connection hole 150, so that the current at the connection hole 150 remains consistent, thereby improving the testing accuracy of the voltage detection line.

[0076] Furthermore, the area of ​​the first pin 141 is larger than the areas of the second pin 142, the third pin 143, the fourth pin 144, and the fifth pin 145.

[0077] The shunt resistor provided in this embodiment of the utility model is manufactured using the same substrate process. When used for current detection, the current to be measured is shunted through the first shunt resistor Rp and the second shunt resistor Rs, which have the same temperature coefficient, thereby reducing the impact of temperature drift on the accuracy of current detection.

[0078] Furthermore, this embodiment of the present invention also provides a detection chip, which includes a current detection chip connected to the interconnect layer 110 of the shunt resistor 100. The current detection chip includes a current detection operational amplifier interconnected with the shunt resistor 100. The shunt resistor 100 and the current detection chip are packaged together. The negative input terminal of the current detection operational amplifier is connected to the second terminal of the second shunt resistor Rs, and the positive input terminal of the current detection operational amplifier is connected to the first terminal of the first shunt resistor Rp. The second terminal of the first shunt resistor Rp is connected to the first terminal of the second shunt resistor Rs.

[0079] For example, the output of a current sensing operational amplifier can be connected to the control terminal of a transistor. The first terminal of the transistor is connected to the positive input terminal of the current sensing operational amplifier, and the second terminal of the transistor can output a sensing current that is proportional to the current on the second shunt resistor Rs.

[0080] By packaging the shunt resistor 100 and the current sensing chip together, the sensing chip can be precisely debugged at the factory, thereby improving the accuracy of current sensing while reducing the difficulty of use.

[0081] The embodiments of this utility model described above are examples of specific examples, and do not exhaustively describe all details, nor do they limit the utility model to only specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to make good use of this utility model and its modifications. The scope of protection of this utility model should be determined by the scope defined by the claims of this utility model and their equivalents.

Claims

1. A shunt resistor, comprising: The interconnect layer, the second insulating layer, the first shunt resistor layer, the second shunt resistor layer, the third insulating layer, and the conductive layer with pins are laminated together, wherein the first insulating layer is located between the first shunt resistor layer and the second shunt resistor layer, the second insulating layer is located between the first shunt resistor layer and the interconnect layer, and the third insulating layer is located between the second shunt resistor layer and the conductive layer. The interconnect layer is used to realize the interconnection between the shunt resistor and the current sensing operational amplifier. The first shunt resistor layer has a first resistor line for forming a first shunt resistor; The second shunt resistor layer has a second resistor line for forming a second shunt resistor; The thickness of the second resistance wire is greater than the thickness of the first resistance wire, and the width of the second resistance wire is greater than the width of the first resistance wire.

2. The shunt resistor according to claim 1, wherein, The first shunt resistor layer further includes a first contact terminal and a second contact terminal. The first resistance line is connected to the first contact terminal and the second contact terminal. The first resistance line extends in a tortuous manner between the first contact terminal and the second contact terminal. The first resistance line includes a plurality of first bends and a plurality of first straight sections. The first contact terminal is the first end of the first shunt resistor, and the second contact terminal is the second end of the first shunt resistor. The second resistance wire includes a plurality of second bends and a plurality of second straight sections, wherein the extension direction of the first straight section is perpendicular to the extension direction of the second straight section.

3. The shunt resistor according to claim 2, wherein, The conductive layer includes a plurality of first pins, as well as second pins, third pins, and fourth pins corresponding to the plurality of second linear portions. Each of the first pins is connected to its corresponding second linear portion via a connecting hole. The second pin is connected to the first end of the second shunt resistor through at least one first pin, and the second contact terminal is electrically connected to the second pin through a conductive channel, and is also electrically connected to an external circuit through the second pin; The third pin is connected to the second terminal of the second shunt resistor through at least one first pin, and the connecting lines between the first pin, the second pin, and the third pin are of equal length; The first contact terminal is electrically connected to the fourth pin via a conductive channel, and is also electrically connected to an external circuit through the fourth pin. Among them, the multiple first pins connected to the odd number of second straight sections can be short-circuited and connected to serve as the first end of the second shunt resistor, and the multiple first pins connected to the even number of second straight sections can be short-circuited and connected to serve as the second end of the second shunt resistor.

4. The shunt resistor according to claim 3, wherein, The first pin is narrower near the connection hole than it is far from the connection hole.

5. The shunt resistor according to claim 1, wherein, The shunt resistor also includes: A solder resist layer is disposed on the surface of the interconnect layer and the conductive layer in areas where no external connection is required. A nickel-gold layer is disposed on the surface of the interconnect layer and the conductive layer in areas where external connectivity is required.

6. The shunt resistor according to claim 1, wherein, The resistance ratio between the first shunt resistor and the second shunt resistor is greater than or equal to 10000:

1.

7. The shunt resistor according to claim 1, wherein, The insulating materials of the first insulating layer, the second insulating layer, and the third insulating layer include prepreg, polyimide, and encapsulation molding compound.

8. The shunt resistor according to claim 1, wherein, Both the first shunt resistor layer and the second shunt resistor layer are made of copper foil.

9. The shunt resistor according to claim 1, wherein, Both the first shunt resistor layer and the second shunt resistor layer are multilayered.

10. A detection chip, comprising: The shunt resistor as described in any one of claims 1-9; as well as A current sensing chip, comprising a current sensing operational amplifier, is electrically connected to the interconnect layer of the shunt resistor. The current sensing chip is packaged together with the shunt resistor. The negative input terminal of the current sensing operational amplifier is connected to the second terminal of the second shunt resistor, the positive input terminal of the current sensing operational amplifier is connected to the first terminal of the first shunt resistor, and the second terminal of the first shunt resistor is connected to the first terminal of the second shunt resistor.

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