Semiconductor laser chip array and laser display device
By designing a semiconductor laser chip array with multiple spaced light-emitting structures, the problems of unclear display effect and insufficient brightness in single laser chip design were solved, achieving high brightness and stable display effect and extending service life.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU GANBRIGHT OPTOELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2025-08-01
- Publication Date
- 2026-07-21
AI Technical Summary
Existing laser display devices suffer from problems such as unclear display effects, insufficient brightness, and low color reproduction due to their use of a single laser chip design.
Design a semiconductor laser chip array comprising multiple spaced light-emitting structures, each capable of emitting laser light, with openings between adjacent structures to provide a good heat dissipation channel, thereby improving brightness and display quality.
By combining multiple light-emitting structures, display quality and brightness are improved, temperature fluctuations are reduced, and lifespan is extended.
Smart Images
Figure CN224537605U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, specifically to a semiconductor laser chip array and a laser display device. Background Technology
[0002] Gallium nitride (GaN) semiconductor lasers possess monochromaticity, high efficiency, high power density, good directionality, low cost, and small size. Their spectral range covers the entire near-infrared, visible, and ultraviolet bands, making them an indispensable new type of high-efficiency semiconductor light source for strategic emerging industries such as laser displays, laser lighting, laser direct writing, laser processing, and visible light communication. With technological advancements, laser display devices have become one of the mainstream high-end display technologies today. Gallium nitride laser display devices offer significant advantages in terms of rich colors, vibrant hues, and clear visual effects.
[0003] However, most laser display devices currently on the market are single-chip designs, using monolithic dot matrix displays. Due to limitations in power density and heat dissipation of the laser devices themselves, they suffer from problems such as unclear display effects, insufficient brightness, and low color reproduction.
[0004] Therefore, in order to further improve the display effect and performance of laser display devices, it is necessary to provide a novel semiconductor laser chip array and its manufacturing method to enhance the overall display quality and user experience. Utility Model Content
[0005] This invention provides a semiconductor laser chip array, comprising: a substrate layer; a plurality of spaced-apart light-emitting structures located on one side of the substrate layer, with an opening between adjacent light-emitting structures; wherein, the light-emitting structure comprises: a first cladding layer; an active layer located on the side of the first cladding layer opposite to the substrate layer; a second cladding layer located on the side of the active layer opposite to the first cladding layer, the second cladding layer including a ridge region, the dimension of the ridge region along the slow axis direction being smaller than the dimension of the active layer along the slow axis direction; and a current injection defining layer located on the side of the ridge region opposite to the active layer, the current injection defining layer having a current injection window; a passivation layer located on the sidewall of the light-emitting structure and the surface of the opening facing the substrate layer; and a front electrode located on the side of the current injection defining layer opposite to the active layer and connected to the ridge region through the current injection window, the front electrodes located on different sides of the ridge region being spaced apart.
[0006] Optionally, the second cladding includes an upper waveguide layer and an upper confinement layer, the upper confinement layer being located on the side of the upper waveguide layer opposite to the active layer; the upper confinement layer, at least a portion of its thickness, constitutes the ridge region.
[0007] Optionally, the upper confinement layer includes a first upper confinement layer and a second upper confinement layer located on the side of the first upper confinement layer opposite to the upper waveguide layer, wherein the second upper confinement layer and the first upper confinement layer having at least a partial thickness constitute the ridge region.
[0008] Optionally, the material of the second upper confining layer includes indium tin oxide.
[0009] Optionally, the size of the second upper confinement layer in the slow axis direction is 100nm~500nm.
[0010] Optionally, the size of the opening in the slow axis direction is 20 micrometers to 50 micrometers.
[0011] Optionally, the semiconductor laser chip array includes 3 to 10 of the light-emitting structures; the luminous power of a single light-emitting structure is 1W to 3W.
[0012] Optionally, the distance between the centers of adjacent light-emitting structures in the slow axis direction is 30 micrometers to 500 micrometers.
[0013] Optionally, the ridge region has a size of 10 micrometers to 100 micrometers in the slow axis direction and a size of 200 nm to 500 nm in the fast axis direction.
[0014] Optionally, the light-emitting structure has a front cavity surface and a rear cavity surface opposite each other in the cavity length direction; the light-emitting area of the front cavity surface of the light-emitting structure is 1um*8um~1um*20um.
[0015] Optionally, the semiconductor laser chip array has a cavity length dimension of 500 micrometers to 1000 micrometers, a slow axis dimension of 800 micrometers to 2000 micrometers, and a fast axis dimension of 75 micrometers to 100 micrometers.
[0016] Optionally, the thickness of the passivation layer is 100nm~500nm.
[0017] This application also provides a laser display device, including the semiconductor laser chip array of this application.
[0018] The technical solution of this utility model has the following advantages:
[0019] The semiconductor laser chip array provided by this utility model has multiple spaced-apart light-emitting structures located on one side of a substrate layer. Each light-emitting structure can emit laser light, and there are openings between adjacent light-emitting structures. These openings provide a good heat dissipation channel for the light-emitting structures, resulting in smaller temperature fluctuations and more stable wavelengths of the emitted laser light. Because the semiconductor laser chip array includes multiple light-emitting structures, the combined brightness of these structures is high, improving display quality. The semiconductor laser chip array also features high quality, high yield, and long lifespan. Attached Figure Description
[0020] To more clearly illustrate the specific embodiments of this utility model or the drawings used in the description of the prior art, it is obvious that the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0021] Figure 1 This is a structural diagram of a semiconductor laser chip array provided in an embodiment of the present invention;
[0022] Figures 2 to 12 A structural diagram illustrating the fabrication process of the semiconductor laser chip array provided by this utility model. Detailed Implementation
[0023] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.
[0024] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0025] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0026] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.
[0027] One embodiment of this utility model provides a semiconductor laser chip array, see reference. Figure 1 ,include:
[0028] Substrate 100;
[0029] A plurality of spaced-apart light-emitting structures are located on one side of the substrate layer 100, with an opening 190 between adjacent light-emitting structures; wherein, the light-emitting structure includes: a first cladding layer W1; an active layer 1301 located on the side of the first cladding layer W1 opposite to the substrate layer 100; a second cladding layer W2 located on the side of the active layer 1301 opposite to the first cladding layer W1, the second cladding layer W2 including a ridge region, the dimension of the ridge region along the slow axis direction being smaller than the dimension of the active layer 1301 along the slow axis direction; and a current injection definition layer 1701 located on the side of the ridge region opposite to the active layer 1301, the current injection definition layer having a current injection window;
[0030] Passivation layer 210 is located on the sidewall of the light-emitting structure and on the surface of the opening 190 facing the substrate layer 100;
[0031] The front electrode 230 is located on the side of the current injection definition layer 1701 opposite to the active layer 1301 and is connected to the ridge region through the current injection window. The front electrodes 230 located on different sides of the ridge region are spaced apart.
[0032] In this embodiment, the semiconductor laser chip array has multiple spaced-apart light-emitting structures located on one side of the substrate layer 100. Each light-emitting structure emits laser light, and adjacent light-emitting structures are separated by an opening 190. The opening 190 provides a good heat dissipation channel for the light-emitting structures, resulting in smaller temperature fluctuations and more stable wavelengths of the emitted laser light. Since the semiconductor laser chip array includes multiple light-emitting structures, the combined brightness of these structures is high, improving display quality. The semiconductor laser chip array exhibits high quality, high yield, and long lifespan.
[0033] The semiconductor laser chip array is a side-emitting semiconductor laser chip array. The semiconductor laser chip array can be a GaN-based semiconductor laser chip array.
[0034] In this embodiment, the first cladding layer includes W1, which includes a lower waveguide layer 1201 and a lower confinement layer 1101, with the lower confinement layer 1101 located between the lower waveguide layer 1201 and the substrate layer 100.
[0035] In this embodiment, the second cladding W2 includes an upper waveguide layer 1401 and an upper confinement layer. The upper confinement layer is located on the side of the upper waveguide layer 1401 opposite to the active layer 1301; the upper confinement layer with at least a partial thickness forms a ridge region. Figure 1 The example used is that the entire upper confining layer forms a ridge region. In other embodiments, the upper confining layer may form a ridge region with a portion of its thickness.
[0036] In one embodiment, the upper confinement layer includes a first upper confinement layer 1501 and a second upper confinement layer 1601 located on the side of the first upper confinement layer 1501 opposite to the upper waveguide layer 1401, wherein the second upper confinement layer 1601 and the first upper confinement layer 1501 with at least a partial thickness constitute the ridge region. Figure 1 The example shown uses the second upper limiting layer 1601 and the entire first upper limiting layer 1501 to form a ridge region. In other embodiments, the ridge region may be formed by the second upper limiting layer 1601 and a portion of the thickness of the first upper limiting layer 1501.
[0037] In one embodiment, the material of the second upper confinement layer 1601 includes indium tin oxide (ITO).
[0038] In one embodiment, the second upper confinement layer 1601 has a size of 100nm~500nm in the slow axis direction.
[0039] In one embodiment, the size of the opening 190 in the slow axis direction is 20 micrometers to 50 micrometers, for example, 20 micrometers, 30 micrometers, 40 micrometers or 50 micrometers.
[0040] In one embodiment, the semiconductor laser chip array includes 3 to 10 light-emitting structures; the light-emitting power of a single light-emitting structure is 1W to 3W.
[0041] In one embodiment, the spacing between the centers of adjacent light-emitting structures in the slow axis direction is 30 micrometers to 500 micrometers, for example, 30 micrometers, 50 micrometers, 100 micrometers, 200 micrometers, 300 micrometers, 400 micrometers or 500 micrometers.
[0042] In one embodiment, the size of the ridge region in the slow axis direction is 10 micrometers to 100 micrometers, for example, 10 micrometers, 50 micrometers or 100 micrometers; the size of the ridge region in the fast axis direction is 200nm to 500nm, for example, 10 micrometers, 50 micrometers or 100 micrometers.
[0043] In one embodiment, the light-emitting structure has a front cavity surface and a rear cavity surface opposite each other in the cavity length direction; the light-emitting area of the light-emitting structure on the front cavity surface is 1um*8um~1um*20um.
[0044] The cavity length direction of the light-emitting structure is perpendicular to both the slow axis and fast axis directions of the light-emitting structure. The slow axis direction of the light-emitting structure is perpendicular to the fast axis direction of the light-emitting structure.
[0045] The semiconductor laser chip array further includes: an antireflective coating located on the front cavity surface; and a reflective coating located on the rear cavity surface.
[0046] In one embodiment, the size of the semiconductor laser chip array in the cavity length direction is 500 micrometers to 1000 micrometers, the size of the semiconductor laser chip array in the slow axis direction is 800 micrometers to 2000 micrometers, and the size of the semiconductor laser chip array in the fast axis direction is 75 micrometers to 100 micrometers.
[0047] In one embodiment, the thickness of the passivation layer 210 is 100nm to 500nm, for example, 100nm, 200nm, 300nm, 400 micrometers or 500nm.
[0048] In one embodiment, the material of the passivation layer 210 includes one or more of SiO2, SiN, Al2O3, and ZrO2.
[0049] In one embodiment, the material of the current injection definition layer 1701 includes silicon oxide.
[0050] In one embodiment, the thickness of the current injection definition layer 1701 is 500nm-1500nm.
[0051] In this embodiment, the semiconductor laser chip array further includes a back electrode 240, located on the side of the substrate layer 100 away from the active layer 1301.
[0052] In one embodiment, the material of the back electrode 240 includes one or any combination of Ni, Ti, Al, Pd, Pt and Au.
[0053] In one embodiment, the thickness of the back electrode 240 is 300 nm to 1 μm.
[0054] In one embodiment, the material of the front electrode 230 includes one or any combination of Ni, Ti, Al, Pd, Pt and Au.
[0055] In one embodiment, the thickness of the front electrode 230 is 800 nm to 3 μm.
[0056] The front electrodes 230 corresponding to the multiple light-emitting structures are independent of each other, while the back electrodes 240 corresponding to the multiple light-emitting structures are connected together. The multiple front electrodes 230 can be controlled independently.
[0057] In one embodiment, the substrate 100 has a dimension of 70-90 micrometers in the fast axis direction.
[0058] Another embodiment of this application provides a method for fabricating a semiconductor laser chip array, comprising: forming a plurality of spaced-apart light-emitting structures on one side of a substrate layer; having an opening between adjacent light-emitting structures; wherein the light-emitting structure comprises: a first cladding layer; an active layer located on the side of the first cladding layer away from the substrate layer; a second cladding layer located on the side of the active layer away from the first cladding layer, the second cladding layer comprising a ridge region, the dimension of the ridge region along the slow axis direction being smaller than the dimension of the active layer along the slow axis direction; and a current injection defining layer located on the side of the ridge region away from the active layer; forming a passivation layer located on the sidewall of the light-emitting structure and the surface of the opening facing the substrate layer, the passivation layer exposing the current injection defining layer; having a current injection window in the current injection defining layer; forming a front electrode located on the side of the current injection defining layer away from the active layer and connected to the ridge region through the current injection window, the front electrodes located on different sides of the ridge regions being spaced apart.
[0059] The following is combined with Figures 2 to 12 This paper details the fabrication method of conductor laser chip arrays.
[0060] refer to Figure 2 A first initial cladding layer W10, an initial active layer 130, a second initial cladding layer W20, and a current injection defining material layer 170 are sequentially formed on one side of the substrate layer 100.
[0061] In one embodiment, forming the first initial cladding W10 includes: sequentially forming an initial lower confinement layer 110 and an initial lower waveguide layer 120 on one side of the substrate layer 100.
[0062] In one embodiment, forming the second initial cladding W20 includes: sequentially forming an initial upper waveguide layer 140 and an initial upper confinement layer on the side of the initial active layer 130 opposite to the first initial cladding W10. For example, the initial upper waveguide layer 140, the first initial upper confinement layer 150, and the second initial upper confinement layer 160 are sequentially formed on the side of the initial active layer 130 opposite to the first initial cladding W10.
[0063] The material of the first initial upper confinement layer 150 is the same as that of the first upper confinement layer in the aforementioned embodiment. The material and thickness of the second initial upper confinement layer 160 are the same as those of the second upper confinement layer in the aforementioned embodiment.
[0064] In one embodiment, the material of the current-injected material layer 170 includes silicon oxide.
[0065] In one embodiment, the current injection defines the thickness of the material layer 170 as 500 nm to 1500 nm.
[0066] refer to Figure 3 and Figure 4 The current injection defining material layer 170, the second initial cladding layer W20, the initial active layer 130 and the first initial cladding layer W10 are etched to form an opening 190 that exposes the substrate layer. The initial active layer 130 between adjacent openings 190 forms an active layer 1301, and the first initial cladding layer W10 between adjacent openings 190 forms a first cladding layer W1.
[0067] refer to Figure 3 A patterned first mask layer 180 is formed on the side of the current injection defined material layer 170 opposite to the second initial cladding layer W20.
[0068] The material of the first mask layer 180 includes photoresist.
[0069] refer to Figure 4 Using the first mask layer 180 as a mask, the current injection defining material layer 170, the second initial cladding layer W20, the initial active layer 130 and the first initial cladding layer W10 are etched to form an opening 190 that exposes the substrate layer.
[0070] Using the first mask layer 180 as a mask, the current injection defining material layer 170, the second initial cladding layer W20, the initial active layer 130 and the first initial cladding layer W10 are etched to form an opening 190 exposing the substrate layer. The process used can be a dry etching process, such as reactive ion etching using inductively coupled plasma.
[0071] The first initial cladding W10 between adjacent openings 190 forms a first cladding W1. Specifically, the initial lower confinement layer 110 between adjacent openings 190 forms a lower confinement layer 1101, and the initial lower waveguide layer 120 between adjacent openings 190 forms a lower waveguide layer 1201. The first cladding W1 includes the lower waveguide layer 1201 and the lower confinement layer 1101.
[0072] An initial upper waveguide layer 140 between adjacent openings 190 forms an upper waveguide layer 1401.
[0073] In one embodiment, the size of the opening 190 in the slow axis direction is 20 micrometers to 50 micrometers, for example, 20 micrometers, 30 micrometers, 40 micrometers or 50 micrometers.
[0074] In one embodiment, the depth of the opening 190 in the fast axis direction is 3 micrometers to 10 micrometers.
[0075] refer to Figure 5 Remove the first mask layer by 180°.
[0076] refer to Figure 6 and Figure 7 The current injection defining material layer 170 between adjacent openings 190 and the second initial cladding layer W20 of a certain thickness are etched to form the second cladding layer W20 to form the second cladding layer W2, and the current injection defining layer 170 to form the current injection defining layer 1701.
[0077] refer to Figure 6 A second mask layer 200 is formed on the side of the current injection defining material layer 170 away from the second initial cladding layer W20, and the second mask layer 200 exposes part of the current injection defining material layer 170.
[0078] The material of the second mask layer 200 includes a photoresist layer.
[0079] refer to Figure 7 Using the second mask layer 200 as a mask, the current injection defining material layer 170 between adjacent openings 190 and the second initial cladding layer W20 of a certain thickness are etched, so that the second initial cladding layer W20 forms the second cladding layer W2, and the current injection defining layer 170 forms the current injection defining layer 1701.
[0080] Using the second mask layer 200 as a mask, the etching process used to etch the current injection defining material layer 170 and the second initial cladding layer W20 of a certain thickness between adjacent openings 190 can be a dry etching process, such as reactive ion etching using inductively coupled plasma.
[0081] The etching of the second initial cladding layer W20, which has a partial thickness between adjacent openings 190, includes etching an initial upper confinement layer with at least a partial thickness between adjacent openings 190, so that the initial upper confinement layer forms an upper confinement layer.
[0082] The etching of the second initial cladding layer W20, which has a partial thickness between adjacent openings 190, includes etching the second initial upper confinement layer 160 and the first initial upper confinement layer 150, which has a minimum thickness between adjacent openings 190, such that the second initial upper confinement layer 160 forms a second upper confinement layer 1601 and the first initial upper confinement layer 150 forms a first upper confinement layer 1501; the second upper confinement layer 1601 and the first upper confinement layer 1501, which has a minimum thickness, constitute the ridge region.
[0083] The dimensions of the ridge region are described with reference to the description in the foregoing embodiments.
[0084] The size of the ridge region in the slow axis direction is smaller than that of the active layer 1301 in the slow axis direction.
[0085] refer to Figure 8 Remove the second mask layer 200.
[0086] refer to Figure 9 A passivation layer 210 is formed, which is located on the sidewall of the light-emitting structure and on the surface of the opening 190 facing the substrate layer 100. The passivation layer 210 exposes the current injection definition layer 1701.
[0087] In one embodiment, forming the passivation layer 210 includes: forming an initial passivation layer on the sidewall of the light-emitting structure, the surface of the opening 190 facing the substrate layer 100, and the side of the current injection definition layer 1701 away from the upper confinement layer; removing the initial passivation layer on the side of the current injection definition layer 1701 away from the upper confinement layer, and the remaining initial passivation layer forming the passivation layer 210.
[0088] The thickness and material of the passivation layer 210 are as described in the foregoing embodiments.
[0089] refer to Figure 10 The current injection definition layer 1701 has a current injection window 220.
[0090] refer to Figure 11 A front electrode 230 is formed. The front electrode 230 is located on the side of the current injection definition layer 1701 away from the active layer 1301 and is connected to the ridge region through the current injection window 220. The front electrodes 230 located on different sides of the ridge region are spaced apart.
[0091] The material and thickness of the front electrode 230 are as described in the foregoing embodiments.
[0092] refer to Figure 12 A back electrode 240 is formed on the side of the substrate layer 100 opposite to the active layer 1301.
[0093] The material and thickness of the back electrode 240 are as described in the foregoing embodiments.
[0094] In one embodiment, the substrate layer 100 is thinned before forming the back electrode 240.
[0095] Another embodiment of this application provides a laser display device, including: a semiconductor laser chip array of the above embodiments of this application.
[0096] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the protection scope of this invention.
Claims
1. A semiconductor laser chip array, characterized in that, include: Substrate layer; A plurality of spaced-apart light-emitting structures are located on one side of the substrate layer, with openings between adjacent light-emitting structures; wherein, the light-emitting structure includes: a first cladding layer; an active layer located on the side of the first cladding layer opposite to the substrate layer; a second cladding layer located on the side of the active layer opposite to the first cladding layer, the second cladding layer including a ridge region, the dimension of the ridge region along the slow axis direction being smaller than the dimension of the active layer along the slow axis direction; and a current injection definition layer located on the side of the ridge region opposite to the active layer, the current injection definition layer having a current injection window; A passivation layer is located on the sidewall of the light-emitting structure and on the surface of the opening facing the substrate layer; The front electrode is located on the side of the current injection definition layer away from the active layer and is connected to the ridge region through the current injection window. The front electrode is located on the side of the different ridge regions.
2. The semiconductor laser chip array according to claim 1, characterized in that, The second cladding includes an upper waveguide layer and an upper confinement layer, the upper confinement layer being located on the side of the upper waveguide layer opposite to the active layer; the upper confinement layer, at least a portion of its thickness, constitutes the ridge region.
3. The semiconductor laser chip array according to claim 2, characterized in that, The upper confinement layer includes a first upper confinement layer and a second upper confinement layer located on the side of the first upper confinement layer opposite to the upper waveguide layer, wherein the second upper confinement layer and the first upper confinement layer having at least a partial thickness constitute the ridge region.
4. The semiconductor laser chip array according to claim 3, characterized in that, The material of the second upper confinement layer includes indium tin oxide.
5. The semiconductor laser chip array according to claim 3, characterized in that, The second upper confinement layer has a size of 100nm~500nm in the slow axis direction.
6. The semiconductor laser chip array according to claim 1, characterized in that, The size of the opening in the slow axis direction is 20 micrometers to 50 micrometers.
7. The semiconductor laser chip array according to claim 1, characterized in that, The semiconductor laser chip array includes 3 to 10 light-emitting structures; the light-emitting power of a single light-emitting structure is 1W to 3W.
8. The semiconductor laser chip array according to claim 1, characterized in that, The distance between the centers of adjacent light-emitting structures in the slow axis direction is 30 micrometers to 500 micrometers.
9. The semiconductor laser chip array according to claim 1, characterized in that, The ridge region has a size of 10 micrometers to 100 micrometers in the slow axis direction and a size of 200 nm to 500 nm in the fast axis direction.
10. The semiconductor laser chip array according to claim 1, characterized in that, The light-emitting structure has a front cavity surface and a rear cavity surface opposite each other in the cavity length direction; The light-emitting structure has a light-emitting area of 1um*8um to 1um*20um on the front cavity surface.
11. The semiconductor laser chip array according to claim 1, characterized in that, The semiconductor laser chip array has a cavity length dimension of 500 micrometers to 1000 micrometers, a slow axis dimension of 800 micrometers to 2000 micrometers, and a fast axis dimension of 75 micrometers to 100 micrometers.
12. The semiconductor laser chip array according to claim 1, characterized in that, The thickness of the passivation layer is 100nm~500nm.
13. A laser display device, characterized in that, include: The semiconductor laser chip array according to any one of claims 1 to 12.