A front stage protection circuit of a vehicle-mounted direct current electrical system

Abstract

The application provides a front-stage protection circuit of a vehicle-mounted direct-current electrical system, comprising a spike suppression unit, an input end of the spike suppression unit being connected with an input power supply, an output end being connected with a surge voltage suppression unit, a surge current suppression unit and a voltage boosting unit in sequence, and an output end of the voltage boosting unit being connected with a load; the spike suppression unit is used for clamping an input spike pulse voltage, the surge voltage suppression unit is used for suppressing and clamping an input voltage surge, the surge current suppression unit is used for suppressing a surge current at a power-on moment, and the voltage boosting unit is used for maintaining an output voltage of a rear stage unchanged under a front-stage voltage moment drop. The application can clamp a spike pulse voltage and a surge voltage of an input voltage generated by external interference factors, suppress a surge current generated at a power-on moment, and maintain the rear-stage voltage unchanged when an initial engagement surge voltage drops from a steady-state voltage in a disturbance process.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, specifically to a front-end protection circuit for an on-board DC electrical system. Background Technology

[0002] The use of a vehicle-mounted 28V DC electrical system must meet the requirements for surge voltage, spike pulse voltage, and initial engagement surge voltage in the power supply system as specified in GJB298-87 "Characteristics of 28V DC Electrical Systems for Vehicles". GJB298-87 stipulates that under single-fault conditions, the input spike pulse voltage is ±250V with a maximum energy of 15mJ; the surge impulse voltage is 100V / 50ms; and the initial engagement surge voltage will drop from the steady-state voltage to 6V during disturbance. Currently, a common method for suppressing surge voltage is to connect a TVS diode in parallel with the power supply stage. However, the allowable operating time for the TVS diode's pulse peak power is only 1ms, making it highly susceptible to damage under surge voltage impacts lasting up to 50ms.

[0003] Existing technologies cannot effectively protect against both surge current and surge voltage simultaneously. Therefore, this application aims to provide a front-end protection circuit that can take into account both surge current and surge voltage. Summary of the Invention

[0004] In order to overcome the shortcomings of existing technologies that cannot effectively protect against both surge current and surge voltage simultaneously, this utility model provides a front-end protection circuit for a vehicle-mounted DC electrical system.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] A front-end protection circuit for an on-board DC electrical system includes a spike suppression unit. The input terminal of the spike suppression unit is connected to an input power supply, and the output terminal is sequentially connected to a surge voltage suppression unit, a surge current suppression unit, and a boost unit. The output terminal of the boost unit is connected to a load.

[0007] The spike suppression unit is used to clamp the input spike pulse voltage, the surge voltage suppression unit is used to suppress and clamp the input voltage surge, the surge current suppression unit is used to suppress the surge current at the moment of power-on, and the boost unit is used to maintain the output voltage of the subsequent stage unchanged in the event of a momentary drop in the voltage of the preceding stage.

[0008] Furthermore, the spike suppression unit includes a bidirectional TVS diode with a preset voltage threshold, which is connected in parallel across the input power supply.

[0009] Furthermore, the surge voltage suppression unit includes a high-voltage surge suppression chip U1. The FB pin of the high-voltage surge suppression chip U1 is electrically connected to one end of resistor R11 and one end of resistor R12, respectively. The other end of resistor R11 is electrically connected to the OUT pin of the high-voltage surge suppression chip U1, and the other end of resistor R12 is grounded.

[0010] The OUT pin of the high-voltage surge suppression chip U1 is connected to the input terminal of the surge current suppression unit. At the same time, the OUT pin of the high-voltage surge suppression chip U1 is grounded through capacitors C3 and C4, which are connected in parallel and grounded.

[0011] The SENSE pin of the high-voltage surge suppression chip U1 is electrically connected to the source of the MOS transistor Q1 and one end of the resistor R8, and the other end of the resistor R8 is electrically connected to the OUT pin of the high-voltage surge suppression chip U1.

[0012] The GATE pin of the high-voltage surge suppression chip U1 is electrically connected to the gate of the MOS transistor Q1 through resistor R7, and the drain of the MOS transistor Q1 is connected to the positive terminal of the input power supply.

[0013] The VCC pin of the high-voltage surge suppression chip U1 is electrically connected to one end of resistor R6, one end of resistor R5, one end of capacitor C1, and the cathode of the Zener diode. The other end of resistor R6 is electrically connected to the SHDN pin of the high-voltage surge suppression chip U1. The other end of resistor R5 is connected to the positive terminal of the input power supply. The other end of capacitor C1 is connected to ground. The anode of the Zener diode is connected to ground.

[0014] The OV pin of the high voltage surge suppression chip U1 is electrically connected to one end of resistor R3 and one end of resistor R4, respectively. The other end of resistor R3 is connected to the positive terminal of the input power supply, and the other end of resistor R4 is grounded.

[0015] The UV pins of the high voltage surge suppression chip U1 are electrically connected to one end of resistor R1 and one end of resistor R2, respectively. The other end of resistor R1 is connected to the positive terminal of the input power supply, and the other end of resistor R2 is grounded.

[0016] The GND and EP pins of the high-voltage surge suppression chip U1 are both grounded. The TMR pin of the high-voltage surge suppression chip U1 is grounded after being connected in series with capacitor C2. The FLT pin of the high-voltage surge suppression chip U1 is connected to ground through resistor R10. The ENOUT pin of the high-voltage surge suppression chip U1 is connected to ground through resistor R9.

[0017] Furthermore, the high-voltage surge suppression chip U1 uses the CSV24363 chip.

[0018] Furthermore, the surge current suppression unit includes a MOSFET Q2, resistors R13, R14, and R15, capacitors C5 and C6, and a Zener diode Z1.

[0019] The gate pin of the MOSFET Q2 is electrically connected to one end of resistor R14, one end of resistor R13, one end of capacitor C5, and the cathode of Zener diode Z2, respectively. The other end of resistor R13 is electrically connected to the output terminal of the surge voltage suppression unit. The other end of resistor R14, capacitor C5, and Zener diode Z2 is electrically connected to the source of MOSFET Q2.

[0020] The drain of the MOS transistor Q2 is connected to one end of the capacitor C6 and grounded together. The other end of the capacitor C6 is electrically connected to the output of the surge voltage suppression unit. The resistor R15 is connected in parallel across the drain and source of the MOS transistor Q2.

[0021] Furthermore, the boost unit employs a boost circuit.

[0022] The beneficial effects of this utility model are:

[0023] This application provides a front-end protection circuit for an on-board DC electrical system, including a spike suppression unit. The input terminal of the spike suppression unit is connected to an input power supply, and the output terminal is sequentially connected to a surge voltage suppression unit, a surge current suppression unit, and a boost unit. The output terminal of the boost unit is connected to a load. The spike suppression unit is used to clamp the input spike pulse voltage. The surge voltage suppression unit is used to suppress and clamp the input voltage surge. The surge current suppression unit is used to suppress the surge current at the moment of power-on. The boost unit is used to maintain the output voltage of the subsequent stage unchanged when the voltage of the front-end stage drops instantaneously. The front-end protection circuit provided by this application can clamp the spike pulse voltage and surge voltage generated by external interference factors on the input voltage; suppress the surge current generated at the moment of power-on; and maintain the voltage of the subsequent stage unchanged when the initial engagement surge voltage drops from the steady-state voltage during disturbance. Attached Figure Description

[0024] Figure 1 A schematic diagram of a front-end protection circuit for an on-board DC electrical system according to an embodiment of the present disclosure is shown;

[0025] Figure 2 A schematic diagram of a spike suppression unit according to an embodiment of the present disclosure is shown;

[0026] Figure 3 A schematic diagram of a surge voltage suppression unit according to an embodiment of the present disclosure is shown;

[0027] Figure 4A schematic diagram of a surge current suppression unit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0028] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0029] This embodiment provides a 28V vehicle-mounted front-end protection circuit that can clamp the input voltage spikes and surges caused by external interference; suppress the surge current generated at power-on; and keep the subsequent voltage unchanged when the initial engagement surge voltage drops from the steady-state voltage during disturbance.

[0030] Figure 1 A schematic diagram of a front-end protection circuit for an on-board DC electrical system according to an embodiment of this disclosure is shown, such as... Figure 1 As shown, it includes a spike suppression unit, the input terminal of which is connected to the input power supply, and the output terminal is sequentially connected to a surge voltage suppression unit, a surge current suppression unit, and a boost unit. The output terminal of the boost unit is connected to the load.

[0031] The spike suppression unit is used to clamp the input spike pulse voltage, the surge voltage suppression unit is used to suppress and clamp the input voltage surge, the surge current suppression unit is used to suppress the surge current at the moment of power-on, and the boost unit is used to maintain the output voltage of the subsequent stage unchanged in the event of a momentary drop in the voltage of the preceding stage.

[0032] Figure 2 A schematic diagram of a spike suppression unit according to an embodiment of the present disclosure is shown, as follows: Figure 2 As shown, the spike suppression unit includes a bidirectional preset voltage threshold TVS diode DR1, which is connected in parallel across the input power supply. Specifically, the bidirectional preset voltage threshold is 100V. When the input is a normal 28V voltage, the TVS diode is not conducting. When a spike pulse exceeding 100V occurs at the 28V input, the TVS diode DR1 conducts, diverting the voltage spike pulse to ground and protecting the subsequent circuitry from its influence.

[0033] Figure 3 A schematic diagram of a surge voltage suppression unit according to an embodiment of the present disclosure is shown, as follows: Figure 3 As shown, the surge voltage suppression unit includes a high-voltage surge suppression chip U1. The FB pin of the high-voltage surge suppression chip U1 is electrically connected to one end of resistor R11 and one end of resistor R12, respectively. The other end of resistor R11 is electrically connected to the OUT pin of the high-voltage surge suppression chip U1, and the other end of resistor R12 is grounded.

[0034] The OUT pin of the high voltage surge suppression chip U1 is connected to the input terminal of the surge current suppression unit. At the same time, the OUT pin of the high voltage surge suppression chip U1 is grounded through capacitors C3 and C4, which are connected in parallel and then grounded.

[0035] The SENSE pin of the high-voltage surge suppression chip U1 is electrically connected to the source of the MOS transistor Q1 and one end of the resistor R8, and the other end of the resistor R8 is electrically connected to the OUT pin of the high-voltage surge suppression chip U1.

[0036] The GATE pin of the high-voltage surge suppression chip U1 is electrically connected to the gate of the MOS transistor Q1 through resistor R7, and the drain of the MOS transistor Q1 is connected to the positive terminal of the input power supply.

[0037] The VCC pin of the high-voltage surge suppression chip U1 is electrically connected to one end of resistor R6, one end of resistor R5, one end of capacitor C1, and the cathode of the Zener diode. The other end of resistor R6 is electrically connected to the SHDN pin of the high-voltage surge suppression chip U1. The other end of resistor R5 is connected to the positive terminal of the 28V input power supply. The other end of capacitor C1 is connected to ground. The anode of the Zener diode is connected to ground.

[0038] The OV pin of the high voltage surge suppression chip U1 is electrically connected to one end of resistor R3 and one end of resistor R4, respectively. The other end of resistor R3 is connected to the positive terminal of the input power supply, and the other end of resistor R4 is grounded.

[0039] The UV pins of the high voltage surge suppression chip U1 are electrically connected to one end of resistor R1 and one end of resistor R2, respectively. The other end of resistor R1 is connected to the positive terminal of the input power supply, and the other end of resistor R2 is grounded.

[0040] The GND and EP pins of the high-voltage surge suppression chip U1 are both grounded. The TMR pin of the high-voltage surge suppression chip U1 is grounded after being connected in series with capacitor C2. The FLT pin of the high-voltage surge suppression chip U1 is connected to ground through resistor R10. The ENOUT pin of the high-voltage surge suppression chip U1 is connected to ground through resistor R9.

[0041] Specifically, the high-voltage surge suppression chip U1 uses the CSV24363 chip.

[0042] Specifically, when a normal 28V input is received, the MOSFET Q1 of the surge voltage suppression unit conducts normally, and the subsequent power supply is normal. When a 100V surge voltage of 50ms exists in the circuit, the high-voltage surge suppression chip U1 can limit the voltage on the OUT pin under overvoltage conditions. The voltage amplifier inside the high-voltage surge suppression chip U1 is responsible for regulating the voltage of the GATE pin to maintain a voltage of 1.25V on the FB pin. During this period, the MOSFET Q1 operates in the linear region, is in the conducting state, and supplies current to the load. This enables uninterrupted operation during brief overvoltage transients. If the voltage regulation loop is in the operating state for a longer period than the timeout period set by the timer capacitor, an overvoltage fault is detected. The GATE pin voltage is pulled down to the SNS pin by a 140mA current, thereby turning off the MOSFET Q1, which can prevent the MOSFET Q1 from being damaged during prolonged overvoltage. After the fault condition has disappeared and a cooling cycle has been completed, the GATE pin is pulled high again.

[0043] Figure 4 A schematic diagram of a surge current suppression unit according to an embodiment of the present disclosure is shown, as follows: Figure 4 As shown, the surge current suppression unit includes a MOSFET Q2, resistors R13, R14, and R15, capacitors C5 and C6, and a Zener diode Z1.

[0044] The gate pin of the MOSFET Q2 is electrically connected to one end of resistor R14, one end of resistor R13, one end of capacitor C5, and the cathode of Zener diode Z2, respectively. The other end of resistor R13 is electrically connected to the output terminal of the surge voltage suppression unit. The other end of resistor R14, capacitor C5, and Zener diode Z2 is electrically connected to the source of MOSFET Q2.

[0045] The drain of the MOS transistor Q2 is connected to one end of the capacitor C6 and grounded together. The other end of the capacitor C6 is electrically connected to the output of the surge voltage suppression unit. The resistor R15 is connected in parallel across the drain and source of the MOS transistor Q2.

[0046] Specifically, at the instant of power-on, due to the presence of capacitor C5, there is no voltage difference across the gate and source (GS) terminals of the MOSFET, causing the MOSFET to turn off. Current can only flow through resistor R15, and the current in the circuit is I = U / R15. When capacitor C5 is fully charged, a voltage difference exists between the gate and source terminals of the MOSFET, causing the MOSFET to turn on and short-circuit resistor R15. Current then flows only through MOSFET Q2 to the next stage. Therefore, adjusting the value of resistor R15 can change the magnitude of the inrush current at the instant of power-on.

[0047] The boost unit employs a boost circuit, which is a common DC-DC converter used to convert low-voltage DC input into higher-voltage DC input.

[0048] This embodiment provides a 28V vehicle-mounted pre-stage protection circuit that conforms to the requirements for surge voltage, spike voltage, and initial engagement surge voltage in the power supply system as specified in GJB298-87 "Characteristics of 28V DC Electrical Systems for Vehicles". GJB298-87 specifies the limit values ​​and steady-state voltage range of the transient characteristics of the 28V DC power supply system for military vehicles. Its purpose is to ensure compatibility between the vehicle power supply and the electrical equipment by limiting the power supply performance within a defined range and restricting the power requirements of the electrical equipment.

Claims

1. A front-end protection circuit for an on-board DC electrical system, characterized in that, It includes a spike suppression unit, the input of which is connected to an input power supply, and the output of which is sequentially connected to a surge voltage suppression unit, a surge current suppression unit, and a boost unit. The output of the boost unit is connected to a load. The spike suppression unit is used to clamp the input spike pulse voltage, the surge voltage suppression unit is used to suppress and clamp the input voltage surge, the surge current suppression unit is used to suppress the surge current at the moment of power-on, and the boost unit is used to maintain the output voltage of the subsequent stage unchanged in the event of a momentary drop in the voltage of the preceding stage.

2. The front-end protection circuit of the vehicle-mounted DC electrical system according to claim 1, characterized in that, The spike suppression unit includes a bidirectional TVS diode with a preset voltage threshold, which is connected in parallel across the input power supply.

3. The front-end protection circuit of the vehicle-mounted DC electrical system according to claim 1, characterized in that, The surge voltage suppression unit includes a high voltage surge suppression chip U1. The FB pin of the high voltage surge suppression chip U1 is electrically connected to one end of resistor R11 and one end of resistor R12, respectively. The other end of resistor R11 is electrically connected to the OUT pin of the high voltage surge suppression chip U1, and the other end of resistor R12 is grounded. The OUT pin of the high voltage surge suppression chip U1 is connected to the input terminal of the surge current suppression unit. At the same time, the OUT pin of the high voltage surge suppression chip U1 is grounded through capacitors C3 and C4, which are connected in parallel and then grounded. The SENSE pin of the high-voltage surge suppression chip U1 is electrically connected to the source of the MOS transistor Q1 and one end of the resistor R8, and the other end of the resistor R8 is electrically connected to the OUT pin of the high-voltage surge suppression chip U1. The GATE pin of the high-voltage surge suppression chip U1 is electrically connected to the gate of the MOS transistor Q1 through resistor R7, and the drain of the MOS transistor Q1 is connected to the positive terminal of the input power supply. The VCC pin of the high-voltage surge suppression chip U1 is electrically connected to one end of resistor R6, one end of resistor R5, one end of capacitor C1, and the cathode of the Zener diode. The other end of resistor R6 is electrically connected to the SHDN pin of the high-voltage surge suppression chip U1. The other end of resistor R5 is connected to the positive terminal of the input power supply. The other end of capacitor C1 is connected to ground. The anode of the Zener diode is connected to ground. The OV pin of the high voltage surge suppression chip U1 is electrically connected to one end of resistor R3 and one end of resistor R4, respectively. The other end of resistor R3 is connected to the positive terminal of the input power supply, and the other end of resistor R4 is grounded. The UV pins of the high voltage surge suppression chip U1 are electrically connected to one end of resistor R1 and one end of resistor R2, respectively. The other end of resistor R1 is connected to the positive terminal of the input power supply, and the other end of resistor R2 is grounded. The GND and EP pins of the high-voltage surge suppression chip U1 are both grounded. The TMR pin of the high-voltage surge suppression chip U1 is grounded after being connected in series with capacitor C2. The FLT pin of the high-voltage surge suppression chip U1 is connected to ground through resistor R10. The ENOUT pin of the high-voltage surge suppression chip U1 is connected to ground through resistor R9.

4. The front-end protection circuit of the vehicle-mounted DC electrical system according to claim 3, characterized in that, The high-voltage surge suppression chip U1 uses the CSV24363 chip.

5. The front-end protection circuit of the vehicle-mounted DC electrical system according to claim 1, characterized in that, The surge current suppression unit includes a MOSFET Q2, resistors R13, R14, and R15, capacitors C5 and C6, and a Zener diode Z1. The gate pin of the MOSFET Q2 is electrically connected to one end of resistor R14, one end of resistor R13, one end of capacitor C5, and the cathode of Zener diode Z2, respectively. The other end of resistor R13 is electrically connected to the output terminal of the surge voltage suppression unit. The other end of resistor R14, capacitor C5, and Zener diode Z2 is electrically connected to the source of MOSFET Q2. The drain of the MOS transistor Q2 is connected to one end of the capacitor C6 and grounded together. The other end of the capacitor C6 is electrically connected to the output of the surge voltage suppression unit. The resistor R15 is connected in parallel across the drain and source of the MOS transistor Q2.

6. The front-end protection circuit of the vehicle-mounted DC electrical system according to claim 1, characterized in that, The boost unit uses a boost circuit.

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