Buffering and absorbing circuit applied to heric circuit and heric circuit

Abstract

The application provides a buffer absorption circuit applied to a Heric circuit and the Heric circuit, and relates to the technical field of voltage peak clamping and absorption. The Heric circuit comprises a first freewheeling power switch tube. The buffer absorption circuit comprises a first absorption circuit and a second absorption circuit. A first end of the first absorption circuit is connected with a DC bus for receiving a DC bus voltage, a second end of the first absorption circuit is connected with a first end of the first freewheeling power switch tube, and a third end of the first absorption circuit is connected with a power reference ground. A first end of the second absorption circuit is connected with a second end of the first freewheeling power switch tube, and a second end of the second absorption circuit is connected with the power reference ground. The buffer absorption circuit can clamp the voltage of the first end and the second end of the first freewheeling power switch tube in a controllable voltage range by using a fixed level, so that the loss of the buffer absorption circuit of the first freewheeling power switch tube is greatly reduced, and a better and stable absorption effect is achieved.

Description

Technical Field

[0001] This utility model relates to the field of voltage spike clamping absorption technology, and in particular to a buffer absorption circuit and a Heric circuit for use in Heric circuits. Background Technology

[0002] In modern power electronic systems, the rapid switching action of power switching devices (such as IGBTs and MOSFETs) generates voltage spikes and electromagnetic interference (EMI). These phenomena not only reduce system reliability but can also cause equipment damage. To effectively suppress these voltage spikes and EMI, absorption circuits are widely used in circuits containing power switching devices. Among them, RCD...

[0003] Resistor-Capacitor-Diode (RCD) absorption circuits are widely used due to their simple and effective design. However, existing RCD absorption circuits have some significant limitations in practical applications, which restricts their further application in high-efficiency, high-frequency power electronic systems.

[0004] Please see Figure 1 The diagram illustrates an existing RCD snubber circuit for a power switching device. The RCD snubber circuit is connected in parallel across the power switching device and includes a buffer capacitor C01, a resistor R01, and a diode D01. The first terminal of the buffer capacitor C01 is connected to the first terminal of the power switching device. The second terminal of the buffer capacitor C01 is connected to both the first terminal of the resistor R01 and the anode of the diode D01. The resistor R01 is connected to both the cathode of the diode D01 and the second terminal of the power switching device. The power switching device can be a controllable switch such as an IGBT or a MOSFET. The first terminal of the power switching device is the collector of the IGBT or the drain of the MOSFET, and the second terminal is the emitter of the IGBT or the source of the MOSFET. When the power switching device is turned off, the buffer capacitor C01 absorbs the sudden voltage change at the first terminal of the power switching device, thereby suppressing voltage spikes. Subsequently, the energy stored in the buffer capacitor C01 is dissipated through the resistor R01. This RCD snubber circuit is directly connected in parallel across the power switching device. Therefore, the voltage change on the buffer capacitor C01 is the same as the voltage change on the power switching device, and the voltage change period on the buffer capacitor C01 is also the same as the voltage change period on the power switching device.

[0005] While existing RCD snubber circuits are effective in suppressing voltage spikes, they suffer from two main problems in practical applications. First, they introduce significant additional losses. The buffer capacitor C01 charges and discharges with each switching action of the power switch, resulting in energy loss; diode D01 incurs conduction losses during conduction and recovery; and resistor R01 consumes all the energy absorbed by the buffer capacitor C01. These losses increase dramatically with the operating voltage and switching frequency of the power switch. Second, the value of the buffer capacitor C01 in traditional RCD snubber circuits is directly proportional to the spike absorption capability. Increasing the capacitance of C01 increases the losses in the RCD snubber circuit, creating a trade-off between better absorption capability and lower losses. The increased losses and the limited power capacity of resistor R01, in turn, restrict the value of the buffer capacitor C01, weakening its ability to absorb voltage spikes or other voltage fluctuations.

[0006] In order to effectively absorb voltage spikes and reduce electromagnetic interference while significantly reducing the loss of the buffer absorption circuit, the industry urgently needs to develop a new type of buffer absorption circuit that can simultaneously meet the requirements of low loss and high absorption capability for Heric circuits. Utility Model Content

[0007] This addresses the issue mentioned above that existing RCD absorption circuits cannot simultaneously satisfy both low loss and high absorption capacity.

[0008] This application proposes a snubber circuit for use in a Heric circuit, the Heric circuit including a first freewheeling power switch; the snubber circuit includes:

[0009] A first absorption circuit includes a first terminal, a second terminal, and a third terminal. The first terminal is connected to the DC bus for receiving the DC bus voltage. The second terminal is connected to the first terminal of the first freewheeling power switch. The third terminal is connected to the power reference ground.

[0010] The second absorption circuit includes a first terminal and a second terminal, the first terminal being connected to the second terminal of the first freewheeling power switch, and the second terminal being connected to the power reference ground.

[0011] Optionally, the first absorption circuit includes a first diode, a first absorption resistor, and a first absorption capacitor;

[0012] The anode of the first diode is connected to the first terminal of the first freewheeling power switch, and the cathode of the first diode is connected to the first terminal of the first absorption resistor and the first terminal of the first absorption capacitor, respectively.

[0013] The second end of the first absorption resistor is coupled to the DC bus;

[0014] The second terminal of the first absorption capacitor is connected to the power reference ground.

[0015] Optionally, when the voltage at the first terminal of the first freewheeling power switch is higher than the DC bus voltage, the first diode is turned on, and the first absorption capacitor absorbs the energy of the voltage spike higher than the DC bus voltage and clamps the voltage at the first terminal of the first freewheeling power switch to the DC bus voltage.

[0016] Optionally, the energy of the voltage spike stored in the first absorption capacitor is discharged to the DC bus through the first absorption resistor.

[0017] Optionally, the second absorption circuit includes a second diode, a second absorption resistor, and a second absorption capacitor;

[0018] The cathode of the second diode is connected to the second terminal of the first freewheeling power switch, and the anode of the second diode is connected to the first terminal of the second absorption resistor and the first terminal of the second absorption capacitor, respectively.

[0019] The second terminal of the second absorption resistor and the second terminal of the second absorption capacitor are both connected to the power reference ground.

[0020] Optionally, when the voltage at the second terminal of the first freewheeling power switch is lower than the level of the power reference ground, the second diode is turned on, and the second absorption capacitor absorbs the energy of the negative voltage spike that is lower than the level of the power reference ground and clamps the voltage at the second terminal of the first freewheeling power switch to the level of the power reference ground.

[0021] Optionally, the energy of the negative voltage spike stored in the second absorption capacitor is dissipated through the second absorption resistor.

[0022] Optionally, the Heric circuit further includes a first power switch, a second power switch, a third power switch, a fourth power switch, and a second freewheeling power switch;

[0023] The first end of the first power switch and the first end of the third power switch are both connected to the DC bus. The first end of the second power switch is connected to the second end of the first power switch. The first end of the fourth power switch is connected to the second end of the third power switch. The second ends of the second power switch and the second ends of the fourth power switch are both connected to the power reference ground. The second ends of the first power switch and the second ends of the third power switch are connected to the power grid.

[0024] The first end of the second freewheeling power switch is connected to the first end of the first freewheeling power switch, and the second end of the second freewheeling power switch is connected to the second end of the first power switch.

[0025] The buffer absorption circuit further includes a third absorption circuit, the first end of which is connected to the second end of the second freewheeling power switch, and the second end of which is connected to the power reference ground.

[0026] Optionally, the third absorption circuit includes a third diode, a third absorption resistor, and a third absorption capacitor;

[0027] The cathode of the third diode is connected to the second terminal of the second freewheeling power switch, and the anode of the third diode is connected to the first terminal of the third absorption resistor and the first terminal of the third absorption capacitor, respectively.

[0028] The second terminal of the third absorption resistor and the second terminal of the third absorption capacitor are both connected to the power reference ground.

[0029] Optionally, when the voltage at the second terminal of the second freewheeling power switch is lower than the level of the power reference ground, the third diode is turned on, and the third absorption capacitor absorbs the energy of the negative voltage spike that is lower than the level of the power reference ground and clamps the voltage at the second terminal of the second freewheeling power switch to the level of the power reference ground.

[0030] This application also proposes a Heric circuit, comprising:

[0031] A first power switch transistor, the first end of which is connected to the DC bus;

[0032] A second power switch, the first end of which is connected to the second end of the first power switch and the first end of the power grid, and the second end of which is connected to the power reference ground;

[0033] The third power switch is connected to the DC bus at its first end.

[0034] A fourth power switch, the first end of which is connected to the second end of the third power switch and the second end of the power grid, and the second end of the fourth power switch is connected to the power reference ground;

[0035] A first freewheeling power switch, the second end of which is connected to the second end of the third power switch;

[0036] The second freewheeling power switch is connected to the second terminal of the first power switch, and the first terminal of the second freewheeling power switch is connected to the first terminal of the first freewheeling power switch.

[0037] A first absorption circuit, wherein a first terminal of the first absorption circuit is connected to the DC bus, a second terminal of the first absorption circuit is connected to the first terminal of the first freewheeling power switch, and a third terminal of the first absorption circuit is connected to the power reference ground; and

[0038] A second absorption circuit is provided, with its first terminal connected to the second terminal of the first freewheeling power switch and its second terminal connected to the power reference ground.

[0039] Optionally, the Heric circuit further includes a third absorption circuit;

[0040] The first terminal of the third absorption circuit is connected to the second terminal of the second freewheeling power switch, and the second terminal of the third absorption circuit is connected to the power reference ground.

[0041] Optionally, the first absorption circuit includes a first diode, a first absorption resistor, and a first absorption capacitor;

[0042] The anode of the first diode is connected to the first terminal of the first freewheeling power switch, and the cathode of the first diode is connected to the first terminal of the first absorption resistor and the first terminal of the first absorption capacitor, respectively.

[0043] The second end of the first absorption resistor is coupled to the DC bus;

[0044] The second terminal of the first absorption capacitor is connected to the power reference ground;

[0045] The second absorption circuit includes a second diode, a second absorption resistor, and a second absorption capacitor;

[0046] The cathode of the second diode is connected to the second terminal of the first freewheeling power switch, and the anode of the second diode is connected to the first terminal of the second absorption resistor and the first terminal of the second absorption capacitor, respectively.

[0047] The second terminal of the second absorption resistor and the second terminal of the second absorption capacitor are both connected to the power reference ground;

[0048] The third absorption circuit includes a third diode, a third absorption resistor, and a third absorption capacitor;

[0049] The cathode of the third diode is connected to the second terminal of the second freewheeling power switch, and the anode of the third diode is connected to the first terminal of the third absorption resistor and the first terminal of the third absorption capacitor, respectively.

[0050] The second terminal of the third absorption resistor and the second terminal of the third absorption capacitor are both connected to the power reference ground.

[0051] Optionally, the Heric circuit operates in either forward inverter mode or reverse rectification mode.

[0052] The beneficial effects of this application include at least the following:

[0053] The buffer absorption circuit of this embodiment includes a first absorption circuit and a second absorption circuit. The first terminal of the first absorption circuit is connected to the DC bus to receive the DC bus voltage. The second terminal of the first absorption circuit is connected to the first terminal of the first freewheeling power switch in the Heric circuit. The third terminal of the first absorption circuit is grounded. The first terminal of the second absorption circuit is connected to the second terminal of the first freewheeling power switch. The second terminal of the second absorption circuit is grounded. Under operating conditions where the voltage levels at both the first and second terminals of the first freewheeling power switch are constantly changing, a fixed voltage level is used for clamping, and the clamping voltage range is controllable. This buffer absorption circuit clamps voltage spikes higher than the DC bus voltage or negative voltage spikes lower than the power reference ground level. Voltage changes within the stress range have no effect, and there is no additional discharge circuit. This buffer absorption circuit significantly reduces losses caused by its operation. It only absorbs voltage spikes higher than the DC bus voltage or negative voltage spikes lower than the power reference ground level. These spikes are short in duration, low in energy, and have minimal losses. Clamping the first freewheeling power switch with the DC bus voltage allows the energy of the voltage spikes absorbed by the first absorption capacitor to be released back to the DC bus through the first absorption resistor, further improving energy utilization and reducing losses. This buffer absorption circuit can select either a large-capacitance first or second absorption capacitor for absorption. When absorbing voltage or negative voltage spikes, the voltage on either capacitor will not surge rapidly, effectively clamping the spikes throughout their formation and achieving better and more stable absorption.

[0054] The features and technical advantages of this application have been broadly outlined above to facilitate a better understanding of the following detailed description. Additional features and advantages of this application, which form the subject matter of the claims, will be described below. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily utilized as the basis for modifying or designing other structures or processes to achieve the same purpose as this application. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this application as set forth in the appended claims. Attached Figure Description

[0055] To gain a more comprehensive understanding of this application and its advantages, the following description is now taken in conjunction with the accompanying drawings, in which:

[0056] Figure 1 A schematic diagram of the RCD snubber circuit of an existing power switching device is shown.

[0057] Figure 2 A schematic diagram of the Heric circuit according to an embodiment of this application is shown;

[0058] Figure 3 A schematic diagram of the buffer absorption circuit according to an embodiment of this application is shown;

[0059] Figure 4 A schematic diagram of the structure of a buffer absorption circuit applied to a Heric circuit according to an embodiment of this application is shown.

[0060] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The accompanying drawings are provided to clearly illustrate relevant aspects of various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0061] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0062] The term "exemplary" as used herein means "serving as an example, embodiment, or illustration." Any embodiment illustrated herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments. The terms "first," "second," "third," etc. (if present) in the specification, claims, and drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence.

[0063] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "coupled," "connected," and "linked" should be interpreted broadly. For example, they can refer to electrical connection or mutual communication, direct connection or indirect connection through an intermediate medium, or the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0064] Furthermore, to better illustrate this utility model, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this utility model can be implemented even without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail, in order to highlight the main points of this utility model.

[0065] The Heric (Highly Efficient Reliable Inverter Concept) circuit is a high-efficiency, high-reliability inverter topology widely used in photovoltaic power generation, energy storage systems, and electric vehicle charging. Please refer to... Figure 2 This diagram illustrates the structure of a Heric circuit according to an embodiment of this application. The Heric circuit includes a first power switch Q1, a second power switch Q2, a third power switch Q3, a fourth power switch Q4, a first freewheeling power switch Q6, a second freewheeling power switch Q5, a bus capacitor Cdc, and an inductor. The first terminal of the bus capacitor Cdc, the first terminal of the first power switch Q1, and the first terminal of the third power switch Q3 are all connected to the positive terminal of the Heric circuit's input. The positive terminal of the Heric circuit's input is connected to the DC bus BUS+. The first terminal of the second power switch Q2 is connected to the second terminal of the first power switch Q1 and the first terminal of the power grid Grid. The first terminal of the fourth power switch Q4 is connected to the second terminal of the third power switch Q3 and the second terminal of the power grid Grid. The second terminal of the bus capacitor Cdc, the second terminal of the second power switch Q2, and the first terminal of the fourth power switch Q4 are connected to the second terminal of the third power switch Q3 and the second terminal of the power grid Grid. Both ends are connected to the negative terminal of the input terminal of the Heric circuit. The negative terminal of the input terminal of the Heric circuit is connected to the power reference ground PGND. The inductor is connected between the first terminal of the grid and the second terminal of the first power switch Q1 and / or between the second terminal of the grid and the second terminal of the third power switch Q3. The second terminal of the second freewheeling power switch Q5 is connected to the second terminal of the first power switch Q1. The first terminal of the second freewheeling power switch Q5 is connected to the first terminal of the first freewheeling power switch Q6. The second terminal of the first freewheeling power switch Q6 is connected to the second terminal of the third power switch Q3.

[0066] In this embodiment, the first power switch Q1, the second power switch Q2, the third power switch Q3, the fourth power switch Q4, the first freewheeling power switch Q6, and the second freewheeling power switch Q5 can be controllable switches, such as IGBTs and MOSFETs.

[0067] In this embodiment, the inductor includes a first inductor L1 and a second inductor L2. The first inductor L1 is connected between the first end of the power grid and the second end of the first power switch Q1, and the second inductor L2 is connected between the second end of the power grid and the second end of the third power switch Q3.

[0068] The Heric circuit of this application can operate in forward inverter mode, that is, the DC bus voltage VBUS provided by the bus capacitor Cdc is inverted into AC voltage by the first power switch Q1, the second power switch Q2, the third power switch Q3, the fourth power switch Q4, the first freewheeling power switch Q6, and the second freewheeling power switch Q5, and fed back to the grid. The Heric circuit can also operate in reverse rectification mode, that is, the AC voltage provided by the grid is rectified into DC voltage by the first power switch Q1, the second power switch Q2, the third power switch Q3, the fourth power switch Q4, the first freewheeling power switch Q6, and the second freewheeling power switch Q5 and supplied to the bus capacitor Cdc.

[0069] The Heric circuit operates in forward inverter mode. When the grid voltage is in the positive half-cycle, the second freewheeling power switch Q5 remains on. Specifically, when the first power switch Q1 and the fourth power switch Q4 are on, the bus capacitor Cdc, the first power switch Q1, the first inductor L1, the grid, the second inductor L2, and the fourth power switch Q4 form a current loop. The first terminal of the grid is positive, and the second terminal is negative. At this time, the voltages across the first power switch Q1, the fourth power switch Q4, and the second freewheeling power switch Q5 are all close to 0V. The second power switch Q2 and the third power switch... The voltage across transistor Q3 and the first freewheeling power switch Q6 is the DC bus voltage VBUS. When the first power switch Q1 and the fourth power switch Q4 are turned off, the anti-parallel diode of the first freewheeling power switch Q6, the second freewheeling power switch Q5, the first inductor L1, the grid, and the second inductor L2 form a freewheeling circuit. At this time, the voltage across the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 is half of the DC bus voltage VBUS, i.e., 1 / 2VBUS. The voltage across the first freewheeling power switch Q6 and the second freewheeling power switch Q5 is close to 0V.

[0070] The Heric circuit operates in forward inverter mode. When the grid voltage is in the negative half-cycle, the first freewheeling power switch Q6 remains on. When the second and third power switches Q2 and Q3 are on, the bus capacitor Cdc, the third power switch Q3, the second inductor L2, the grid, the first inductor L1, and the second power switch Q2 form a current loop. The second terminal of the grid is positive, and the first terminal is negative. At this time, the voltage across the second power switch Q2, the third power switch Q3, and the first freewheeling power switch Q6 is close to 0V. The first power switch Q1 and the fourth power switch... The voltage across transistor Q4 and the second freewheeling power switch Q5 is the DC bus voltage VBUS. When the second power switch Q2 and the third power switch Q3 are turned off, the anti-parallel diode of the second freewheeling power switch Q5, the first freewheeling power switch Q6, the second inductor L2, the grid, and the first inductor L1 form a freewheeling circuit. At this time, the voltage across the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 is half of the DC bus voltage VBUS, i.e., 1 / 2VBUS. The voltage across the first freewheeling power switch Q6 and the second freewheeling power switch Q5 is close to 0V.

[0071] The Heric circuit operates in reverse rectification mode. When the grid voltage is in the positive half-cycle, the first freewheeling power switch Q6 is turned on. The grid, the first inductor L1, the anti-parallel diode of the second freewheeling power switch Q5, the first freewheeling power switch Q6, and the second inductor L2 form a current loop. The first terminal of the grid is positive, and the second terminal is negative. At this time, the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 all experience half of the DC bus voltage. The line voltage VBUS, or 1 / 2VBUS, is close to 0V for both the first freewheeling power switch Q6 and the second freewheeling power switch Q5. When the first freewheeling power switch Q6 is turned off, the grid, the first inductor L1, the anti-parallel diode of the first power switch Q1, the bus capacitor Cdc, the anti-parallel diode of the fourth power switch Q4, and the second inductor L2 form a current loop. At this time, the voltages across the second power switch Q2, the third power switch Q3, and the first freewheeling power switch Q6 are all the DC bus voltage VBUS.

[0072] The Heric circuit operates in reverse rectification mode. When the voltage of the grid is in the negative half-cycle, the second freewheeling power switch Q5 is turned on. The grid, the second inductor L2, the anti-parallel diode of the first freewheeling power switch Q6, the second freewheeling power switch Q5, and the first inductor L1 form a current loop. The second terminal of the grid is positive, and the first terminal is negative. At this time, the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 all experience half of the DC bus voltage. The line voltage VBUS, or 1 / 2VBUS, is close to 0V for both the first freewheeling power switch Q6 and the second freewheeling power switch Q5. When the second freewheeling power switch Q5 is turned off, the grid, the second inductor L2, the anti-parallel diode of the third power switch Q3, the bus capacitor Cdc, the anti-parallel diode of the second power switch Q2, and the first inductor L1 form a current loop. At this time, the voltages across the first power switch Q1, the fourth power switch Q4, and the second freewheeling power switch Q5 are all the DC bus voltage VBUS.

[0073] As can be seen, in the Heric circuit, the first freewheeling power switch Q6 and the second freewheeling power switch Q5 are connected between the second and first terminals of the power grid. The voltage levels at both terminals of the first and second freewheeling power switch Q6 and Q5 are floating. The voltage across both terminals of the first and second freewheeling power switch Q6 and Q5 changes continuously according to the period of the power frequency voltage. The voltage variations are very large; that is, the voltage fluctuations at the first and second terminals of both the first and second freewheeling power switches Q6 and Q5 are directly proportional to the DC bus voltage.

[0074] The voltage stress in the Heric circuit is concentrated on the first freewheeling power switch Q6 and the second freewheeling power switch Q5. The conventional RCD snubber circuit is connected between the first and second terminals of the second freewheeling power switch Q5 or the first and second terminals of the first freewheeling power switch Q6. As the switching action of the second freewheeling power switch Q5 or the first freewheeling power switch Q6 changes, the snubber capacitor in the conventional RCD snubber circuit is continuously charged and discharged, and the charging and discharging frequency is the same as the operating frequency of the second freewheeling power switch Q5 or the first freewheeling power switch Q6. Therefore, as the frequency increases, the loss of the conventional RCD snubber circuit will increase sharply, which also limits the upper limit of the switching frequency of the second freewheeling power switch Q5 or the first freewheeling power switch Q6. Furthermore, the energy consumed by the absorption capacitor on the absorption resistor each time the second freewheeling power switch Q5 or the first freewheeling power switch Q6 operates is directly related to the size of the absorption capacitor. In fast-switching systems, in order to reduce the loss of the absorption circuit or to match the power of the absorption resistor R, the absorption capacitor can only be in the pF range. As a result, the absorption circuit's absorption effect on the voltage spikes across the first freewheeling power switch Q6 or the second freewheeling power switch Q5 is often not ideal.

[0075] The Heric circuit provided in this embodiment changes the operating mode of the absorption capacitor. It uses a fixed voltage clamp instead of a parallel capacitor for buffer absorption. The DC bus voltage VBUS or the power reference ground level (e.g., zero level) is used to clamp the first or second terminal of the first freewheeling power switch Q6 or the first and second terminals of the second freewheeling power switch Q5, and absorbs the energy of voltage spikes higher than the DC bus voltage VBUS or the energy of negative voltage spikes lower than the power reference ground PGND level.

[0076] Please refer to details. Figure 3A schematic diagram of a buffer absorption circuit according to an embodiment of this application is shown. The Heric circuit includes a first freewheeling power switch Q6, and the buffer absorption circuit includes a first absorption circuit and a second absorption circuit. The first terminal of the first absorption circuit is connected to the DC bus BUS+ to receive the DC bus voltage VBUS. The second terminal of the first absorption circuit is connected to the first terminal of the first freewheeling power switch Q6, and the third terminal of the first absorption circuit is connected to the power reference ground PGND. The first terminal of the second absorption circuit is connected to the second terminal of the first freewheeling power switch Q6, and the second terminal of the second absorption circuit is connected to the power reference ground PGND. The first absorption circuit absorbs voltage spikes at the first terminal of the first freewheeling power switch Q6 and clamps the voltage at the DC bus voltage VBUS, wherein the voltage spike is higher than the DC bus voltage. The second absorption circuit absorbs negative voltage spikes at the second terminal of the first freewheeling power switch Q6 and clamps the voltage at the power reference ground level, such as zero level, wherein the negative voltage spike is lower than the power reference ground level.

[0077] Furthermore, the first absorption circuit includes a first diode Ds1, a first absorption resistor Rs1, and a first absorption capacitor Cs1. The anode of the first diode Ds1 is connected to the first terminal of the first freewheeling power switch Q6, and the cathode of the first diode Ds1 is connected to the first terminal of the first absorption resistor Rs1 and the first terminal of the first absorption capacitor Cs1. The second terminal of the first absorption resistor Rs1 is connected to the DC bus BUS+ to receive the DC bus voltage VBUS. The second terminal of the first absorption capacitor Cs1 is connected to the power reference ground PGND. The first terminal of the first freewheeling power switch Q6 is connected to the power reference ground PGND via the first diode Ds1 and the first absorption capacitor Cs1 to establish an energy absorption loop. The cathode of the first diode Ds1 is connected in series with the DC bus BUS+ via the first absorption resistor Rs1. Before the first diode Ds1 is turned on, the DC bus voltage VBUS charges the first absorption capacitor Cs1 through the first absorption resistor Rs1, so that the voltage across the first absorption capacitor Cs1 relative to the power reference ground PGND remains constant at the DC bus voltage VBUS.

[0078] Furthermore, when the voltage at the first terminal of the first freewheeling power switch Q6 is higher than the DC bus voltage VBUS, the first diode Ds1 is turned on, and the first absorption capacitor Cs1 absorbs the energy of the voltage spike higher than the DC bus voltage VBUS and clamps the voltage at the first terminal of the first freewheeling power switch Q6 to the DC bus voltage VBUS. Specifically, after the first freewheeling power switch Q6 is turned off, there will be a voltage spike at the first terminal of the first freewheeling power switch Q6. When the voltage at the first terminal of the first freewheeling power switch Q6 is higher than the DC bus voltage VBUS, the first diode Ds1 is turned on and the first absorption capacitor Cs1 absorbs the energy of the voltage spike at the first terminal of the first freewheeling power switch Q6. Since this voltage spike is higher than the DC bus voltage VBUS, the switching action of the power switch does not interfere with the voltage on the first absorption capacitor Cs1. The first absorption capacitor Cs1 can accurately clamp the voltage at the first terminal of the first freewheeling power switch Q6 and limit it below the DC bus voltage VBUS. The unidirectional conduction characteristic of the first diode Ds1 effectively prevents the energy on the first absorption capacitor Cs1 from flowing to the first terminal of the first freewheeling power switch Q6.

[0079] As can be seen, this first absorption circuit only clamps voltage spikes higher than the DC bus voltage VBUS, and the level changes within the DC bus voltage range are not affected. The energy of the voltage spike is provided only by the energy stored in the stray inductance within the loop. The spike duration is very short and the energy is low, so the loss caused by absorbing only voltage spikes is small.

[0080] Furthermore, the capacitance value of the first absorption capacitor Cs1 in the first absorption circuit can be selected to be relatively large, such as nF or uF. When absorbing voltage spikes, the voltage on the first absorption capacitor Cs1 will not be rapidly charged by the energy of the absorbed voltage spike, and it can effectively clamp the voltage spike throughout the entire process of its generation, achieving a better and more stable absorption and clamping effect.

[0081] Furthermore, the energy of the voltage spike stored in the first absorption capacitor Cs1 is discharged to the DC bus BUS+ through the first absorption resistor Rs1, further improving energy utilization and reducing the additional losses caused by the first absorption circuit.

[0082] Furthermore, the second absorption circuit includes a second diode Ds2, a second absorption resistor Rs2, and a second absorption capacitor Cs2; the cathode of the second diode Ds2 is connected to the second terminal of the first freewheeling power switch Q6, and the anode of the second diode Ds2 is connected to the first terminal of the second absorption resistor Ds2 and the first terminal of the second absorption capacitor Cs2, respectively; the second terminal of the second absorption resistor Rs2 and the second terminal of the second absorption capacitor Cs2 are both connected to the power reference ground PGND.

[0083] Furthermore, when the voltage at the second terminal of the first freewheeling power switch Q6 is lower than the level of the power reference ground PGND, the second diode Ds2 conducts, and the second absorption capacitor Cs2 absorbs the energy of the negative voltage spike below the level of the power reference ground PGND, clamping the voltage at the second terminal of the first freewheeling power switch Q6 to the level of the power reference ground PGND. The second diode Ds2 conducts when a negative voltage appears below the level of the power reference ground PGND at the second terminal of the first freewheeling power switch Q6, and the second absorption capacitor Cs2 absorbs the energy of the negative voltage spike below the level of the power reference ground PGND, clamping the voltage at the second terminal of the first freewheeling power switch Q6 to the level of the power reference ground, for example, zero level.

[0084] As can be seen, the second absorption circuit only absorbs negative voltage spikes that are below the power reference ground PGND, and has no effect on the switching operation of the first freewheeling power switch Q6, nor on voltage changes at the second terminal of the first freewheeling power switch Q6 that are above the power reference ground PGND. It only targets the absorption range of negative voltage spikes and also reduces the losses of the second absorption circuit.

[0085] Furthermore, the energy of the negative voltage spike stored in the second absorption capacitor Cs2 is consumed by the second absorption resistor Rs2, so that the voltage on the second absorption capacitor Cs2 is equal to the level of the power reference ground PGND before the end of each switching cycle.

[0086] Please see Figure 4 A schematic diagram of the buffer absorption circuit of the Heric circuit according to an embodiment of this application is shown. The buffer absorption circuit further includes a third absorption circuit. The first terminal of the third absorption circuit is connected to the second terminal of the second freewheeling power switch Q5, and the second terminal of the third absorption circuit is connected to the power reference ground PGND.

[0087] Furthermore, the third absorption circuit includes a third diode Ds3, a third absorption resistor Rs3, and a third absorption capacitor Cs3; the cathode of the third diode Ds3 is connected to the second terminal of the second freewheeling power switch Q5, and the anode of the third diode Ds3 is connected to the first terminal of the third absorption resistor Rs3 and the first terminal of the third absorption capacitor Cs3, respectively; the second terminals of the third absorption resistor Rs3 and the second terminals of the third absorption capacitor Cs3 are both connected to the power reference ground PGND.

[0088] Furthermore, when the voltage at the second terminal of the second freewheeling power switch is lower than the level of the power reference ground PGND, the third diode conducts, and the third absorption capacitor Cs3 absorbs the energy of the negative voltage spike below the level of the power reference ground PGND and clamps the voltage at the second terminal of the second freewheeling power switch Q5 to the level of the power reference ground PGND. The third diode Ds3 conducts when a negative voltage appears at the second terminal of the second freewheeling power switch Q5 below the level of the power reference ground PGND, and the third absorption capacitor Cs3 absorbs the energy of the negative voltage spike below the level of the power reference ground PGND and clamps the voltage at the second terminal of the second freewheeling power switch Q5 to the level of the power reference ground PGND, for example, zero level.

[0089] As can be seen, the third absorption circuit only clamps negative voltage spikes that are below the power reference ground PGND, and has no effect on the switching action of the second freewheeling power switch Q5, nor on voltage changes at the second terminal of the second freewheeling power switch Q5 that are above the power reference ground PGND; the absorption range that only targets negative voltage spikes also reduces the losses of the third absorption circuit.

[0090] Furthermore, the energy of the negative voltage spike stored in the third absorption capacitor Cs3 is consumed by the third absorption resistor Rs3, so that the voltage on the third absorption capacitor Cs3 is equal to the level of the power reference ground PGND before the end of each switching cycle.

[0091] The buffer absorption circuit of the Heric circuit in this embodiment is suitable for operating conditions where the voltage levels across the freewheeling power switch are constantly changing. It uses fixed voltage levels, such as the DC bus voltage or zero voltage, to clamp the freewheeling power switch, and the clamping voltage range is controllable. The buffer absorption circuit can absorb and clamp voltage spikes higher than the DC bus voltage or negative voltage spikes lower than zero voltage, without affecting voltage changes outside the clamping voltage range or requiring an additional discharge circuit.

[0092] Since the energy of the voltage spike is provided only by the energy stored in the stray inductance within the loop, the spike duration is short and the energy is low. The buffer absorption circuit absorbs only the spike, resulting in less additional loss in the loop. In addition, the energy of the spike stored in the first absorption capacitor is discharged to the DC bus through the first absorption resistor, which helps to improve energy utilization and reduce losses.

[0093] The buffer absorption circuit uses a large-capacitance absorption capacitor. When absorbing a spike, the voltage on the absorption capacitor will not be rapidly increased by the energy of the spike. It can effectively clamp the spike throughout the entire process of its generation, achieving a better and more stable absorption effect.

[0094] Please see Figure 4 This illustration shows a schematic diagram of the buffer absorption circuit of the Heric circuit according to an embodiment of this application. The present invention also provides a Heric circuit, including a first power switch Q1, a second power switch Q2, a third power switch Q3, a fourth power switch Q4, a bus capacitor Cd, a first inductor L1, a second inductor L2, a first freewheeling power switch Q6, and a second freewheeling power switch Q5. The first terminal of the first power switch Q1 is connected to the DC bus BUS+. The first terminal of the second power switch Q2 is connected to the second terminal of the first power switch Q1 and the first terminal of the power grid Grid, and the second terminal of the second power switch Q2 is connected to the power reference ground PGND. The first terminal of the third power switch Q3 is connected to the DC bus BUS+. The first terminal of the fourth power switch Q4 is connected to the second terminal of the third power switch Q3 and the second terminal of the power grid Grid, and the second terminal of the fourth power switch Q4 is connected to the power reference ground PGND. The first terminal of the bus capacitor Cdc is connected to the DC bus BUS+, and the second terminal of the bus capacitor Cdc is connected to the power reference ground PGND. The second terminal of the first freewheeling power switch Q6 is connected to the second terminal of the third power switch Q3. The second terminal of the second freewheeling power switch Q5 is connected to the second terminal of the first power switch Q1, and the first terminal of the second freewheeling power switch Q5 is connected to the first terminal of the first freewheeling power switch Q6. A first inductor L1 is connected between the first power switch Q1 and the first terminal of the power grid, and a second inductor L2 is connected between the second terminal of the third power switch Q3 and the second terminal of the power grid.

[0095] The first terminal of the first absorption circuit is connected to the DC bus BUS+, the second terminal of the first absorption circuit is connected to the first terminal of the first freewheeling power switch Q6, and the third terminal of the first absorption circuit is connected to the power reference ground PGND.

[0096] The first terminal of the second absorption circuit is connected to the second terminal of the first freewheeling power switch Q6, and the second terminal of the second absorption circuit is connected to the power reference ground PGND.

[0097] Furthermore, the first absorption circuit includes a first diode Ds1, a first absorption resistor Rs1, and a first absorption capacitor Cs1. The anode of the first diode Ds1 is connected to the first terminal of the first freewheeling power switch Q6, and the cathode of the first diode Ds1 is connected to the first terminal of the first absorption resistor Rs1 and the first terminal of the first absorption capacitor Cs1. The second terminal of the first absorption resistor Rs1 is connected to the DC bus BUS+. The second terminal of the first absorption capacitor Cs1 is connected to the power reference ground PGND. The first terminal of the first freewheeling power switch Q6 is connected to the power reference ground PGND via the first diode Ds1 and the first absorption capacitor Cs1 to establish an energy absorption loop. The cathode of the first diode Ds1 is connected in series with the DC bus BUS+ via the first absorption resistor Rs1. Before the first diode Ds1 is turned on, the DC bus voltage VBUS charges the first absorption capacitor Cs1 through the first absorption resistor Rs1, so that the voltage across the first absorption capacitor Cs1 relative to the power reference ground PGND remains constant at the DC bus voltage VBUS.

[0098] When the power switch is turned off, a voltage spike higher than the DC bus voltage VBUS will appear at the first terminal of the first freewheeling power switch Q6. When the voltage at the first terminal of the first freewheeling power switch Q6 is higher than the DC bus voltage VBUS, the first diode Ds1 conducts and uses the first absorption capacitor Cs1 to absorb the energy of the voltage spike higher than the DC bus voltage VBUS at the first terminal of the first freewheeling power switch Q6. The switching action of the power switch does not interfere with the voltage on the first absorption capacitor Cs1. The first absorption capacitor Cs1 can accurately clamp the voltage at the first terminal of the first freewheeling power switch Q6 and limit it below the DC bus voltage VBUS. The unidirectional conduction characteristic of the first diode Ds1 effectively prevents the energy on the first absorption capacitor Cs1 from flowing to the first terminal of the first freewheeling power switch Q6.

[0099] As can be seen, this first absorption circuit only clamps voltage spikes above the DC bus voltage VBUS, while level changes below the DC bus voltage VBUS remain unaffected. The energy of the voltage spike is provided solely by the energy stored in the loop stray inductance. The spike duration is short, the energy is low, and the loss caused by absorbing only voltage spikes is minimal.

[0100] Furthermore, the first absorption capacitor Cs1 discharges the energy of the stored voltage spike to the DC bus BUS+ through the first absorption resistor Rs1, thereby further improving energy utilization and reducing losses.

[0101] Furthermore, the second absorption circuit includes a second diode Ds2, a second absorption resistor Rs2, and a second absorption capacitor Cs2; the cathode of the second diode Ds2 is connected to the second terminal of the first freewheeling power switch Q6, and the anode of the second diode Ds2 is connected to the first terminal of the second absorption resistor Ds2 and the first terminal of the second absorption capacitor Cs2, respectively; the second terminal of the second absorption resistor Rs2 and the second terminal of the second absorption capacitor Cs2 are both connected to the power reference ground PGND.

[0102] The second diode Ds2 turns on when a negative voltage lower than the power reference ground PGND appears at the second terminal of the first freewheeling power switch Q6. The second absorption capacitor Cs2 absorbs the energy of the negative voltage spike lower than the power reference ground PGND and clamps the voltage at the second terminal of the first freewheeling power switch Q6 to the level of the power reference ground PGND, for example, zero level.

[0103] As can be seen, the second absorption circuit only clamps negative voltage spikes that are below the power reference ground PGND, and has no effect on the switching action of the first freewheeling power switch Q6, nor on voltage changes at the second terminal of the first freewheeling power switch Q6 that are above the power reference ground PGND; the absorption range that only targets negative voltage spikes also reduces the losses of the second absorption circuit.

[0104] Furthermore, the Heric circuit also includes a third absorption circuit; the first terminal of the third absorption circuit is connected to the second terminal of the second freewheeling power switch Q5, and the second terminal of the third absorption circuit is connected to the power reference ground PGND.

[0105] Furthermore, the third absorption circuit includes a third diode Ds3, a third absorption resistor Rs3, and a third absorption capacitor Cs3; the cathode of the third diode Ds3 is connected to the second terminal of the second freewheeling power switch Q5, and the anode of the third diode Ds3 is connected to the first terminal of the third absorption resistor Rs3 and the first terminal of the third absorption capacitor Cs3, respectively; the second terminals of the third absorption resistor Rs3 and the second terminals of the third absorption capacitor Cs3 are both connected to the power reference ground PGND.

[0106] Furthermore, when the voltage at the second terminal of the second freewheeling power switch is lower than the level of the power reference ground PGND, the third diode turns on, and the third absorption capacitor Cs3 absorbs the energy of the negative voltage spike below the level of the power reference ground PGND and clamps the voltage at the second terminal of the second freewheeling power switch Q5 to the level of the power reference ground PGND. The third diode Ds3 turns on when a negative voltage appears at the second terminal of the second freewheeling power switch Q5 below the level of the power reference ground, and the third absorption capacitor Cs3 absorbs the energy of the negative voltage spike below the level of the power reference ground PGND and clamps the voltage at the level of the second freewheeling power switch Q5 at the level of the power reference ground, for example, zero level.

[0107] As can be seen, the third absorption circuit only clamps negative voltage spikes that are below the power reference ground level, and has no effect on the switching operation of the second freewheeling power switch Q5, nor on voltage changes at the second terminal of the second freewheeling power switch Q5 that are above the power reference ground PGND; the absorption range targeting only negative voltage spikes also reduces the losses of the third absorption circuit.

[0108] The first, second, and third absorption circuits in the Heric circuit of this embodiment are suitable for operating conditions where the voltage levels across the freewheeling power switch are constantly changing. They clamp the freewheeling power switch using fixed voltage levels, such as the DC bus voltage or zero voltage, with a controllable clamping voltage range. By utilizing these circuits, voltage spikes above the DC bus voltage or negative voltage spikes below zero voltage can be absorbed and clamped only, without affecting voltage changes outside the clamping voltage range or requiring additional discharge circuits.

[0109] Since the peak duration is very short and the energy is low, and the first absorption circuit, the second absorption circuit and the third absorption circuit only absorb the peak, the additional loss caused by the absorption circuit is small, and it has the advantages of low loss and high absorption capacity. In addition, the energy of the peak stored in the first absorption capacitor is discharged to the DC bus through the first absorption resistor, which helps to improve energy utilization and reduce loss.

[0110] The first, second, and third absorption circuits use absorption capacitors with large capacitance values. When absorbing spikes, the voltage on the absorption capacitors will not be rapidly increased by the energy of the spikes, and they can effectively clamp the spikes throughout the entire process of their generation, achieving a better and more stable absorption effect.

[0111] Although embodiments of the present application and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the present application as defined by the appended claims.

[0112] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, methods, and steps described herein. Those skilled in the art will readily understand from the disclosure of this application that, according to this application, currently existing or to be developed processes, machines, manufactures, compositions of matter, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein can be utilized. Therefore, it is intended that the appended claims encompass such processes, machines, manufactures, compositions of matter, methods, or steps within their scope.

Claims

1. A buffer absorption circuit applied to a Heric circuit, the Heric circuit including a first freewheeling power switch; characterized in that, The buffer absorption circuit includes: A first absorption circuit includes a first terminal, a second terminal, and a third terminal. The first terminal is connected to the DC bus for receiving the DC bus voltage. The second terminal is connected to the first terminal of the first freewheeling power switch. The third terminal is connected to the power reference ground. The second absorption circuit includes a first terminal and a second terminal, the first terminal being connected to the second terminal of the first freewheeling power switch, and the second terminal being connected to the power reference ground.

2. The buffer absorption circuit applied to Heric circuits according to claim 1, characterized in that, The first absorption circuit includes a first diode, a first absorption resistor, and a first absorption capacitor; The anode of the first diode is connected to the first terminal of the first freewheeling power switch, and the cathode of the first diode is connected to the first terminal of the first absorption resistor and the first terminal of the first absorption capacitor, respectively. The second end of the first absorption resistor is connected to the DC bus; The second terminal of the first absorption capacitor is connected to the power reference ground.

3. The buffer absorption circuit applied to Heric circuits according to claim 2, characterized in that, When the voltage at the first terminal of the first freewheeling power switch is higher than the DC bus voltage, the first diode is turned on, and the first absorption capacitor absorbs the energy of the voltage spike that is higher than the DC bus voltage and clamps the voltage at the first terminal of the first freewheeling power switch to the DC bus voltage.

4. The buffer absorption circuit applied to Heric circuits according to claim 3, characterized in that, The energy of the voltage spike stored in the first absorption capacitor is discharged to the DC bus through the first absorption resistor.

5. The buffer absorption circuit applied to Heric circuits according to claim 1, characterized in that, The second absorption circuit includes a second diode, a second absorption resistor, and a second absorption capacitor; The cathode of the second diode is connected to the second terminal of the first freewheeling power switch, and the anode of the second diode is connected to the first terminal of the second absorption resistor and the first terminal of the second absorption capacitor, respectively. The second terminal of the second absorption resistor and the second terminal of the second absorption capacitor are both connected to the power reference ground.

6. The buffer absorption circuit applied to Heric circuits according to claim 5, characterized in that, When the voltage at the second terminal of the first freewheeling power switch is lower than the level of the power reference ground, the second diode is turned on, and the second absorption capacitor absorbs the energy of the negative voltage spike that is lower than the level of the power reference ground and clamps the voltage at the second terminal of the first freewheeling power switch to the level of the power reference ground.

7. The buffer absorption circuit applied to Heric circuits according to claim 6, characterized in that, The energy of the negative voltage spike stored in the second absorption capacitor is consumed by the second absorption resistor.

8. The buffer absorption circuit applied to Heric circuits according to claim 1, characterized in that, The Heric circuit also includes a first power switch, a second power switch, a third power switch, a fourth power switch, and a second freewheeling power switch. The first end of the first power switch and the first end of the third power switch are both connected to the DC bus. The first end of the second power switch is connected to the second end of the first power switch. The first end of the fourth power switch is connected to the second end of the third power switch. The second ends of the second power switch and the second ends of the fourth power switch are both connected to the power reference ground. The second ends of the first power switch and the second ends of the third power switch are connected to the power grid. The first end of the second freewheeling power switch is connected to the first end of the first freewheeling power switch, and the second end of the second freewheeling power switch is connected to the second end of the first power switch. The buffer absorption circuit further includes a third absorption circuit, the first end of which is connected to the second end of the second freewheeling power switch, and the second end of which is connected to the power reference ground.

9. The buffer absorption circuit applied to Heric circuits according to claim 8, characterized in that, The third absorption circuit includes a third diode, a third absorption resistor, and a third absorption capacitor; The cathode of the third diode is connected to the second terminal of the second freewheeling power switch, and the anode of the third diode is connected to the first terminal of the third absorption resistor and the first terminal of the third absorption capacitor, respectively. The second terminal of the third absorption resistor and the second terminal of the third absorption capacitor are both connected to the power reference ground.

10. The buffer absorption circuit applied to Heric circuits according to claim 9, characterized in that, When the voltage at the second terminal of the second freewheeling power switch is lower than the level of the power reference ground, the third diode turns on, and the third absorption capacitor absorbs the energy of the negative voltage spike that is lower than the level of the power reference ground and clamps the voltage at the second terminal of the second freewheeling power switch to the level of the power reference ground.

11. A Heric circuit, characterized in that, include: A first power switch transistor, the first end of which is connected to the DC bus; A second power switch, the first end of which is connected to the second end of the first power switch and the first end of the power grid, and the second end of which is connected to the power reference ground; The third power switch is connected to the DC bus at its first end. A fourth power switch, the first end of which is connected to the second end of the third power switch and the second end of the power grid, and the second end of the fourth power switch is connected to the power reference ground; A first freewheeling power switch, the second end of which is connected to the second end of the third power switch; The second freewheeling power switch is connected to the second terminal of the first power switch, and the first terminal of the second freewheeling power switch is connected to the first terminal of the first freewheeling power switch. A first absorption circuit, wherein a first terminal of the first absorption circuit is connected to the DC bus, a second terminal of the first absorption circuit is connected to the first terminal of the first freewheeling power switch, and a third terminal of the first absorption circuit is connected to the power reference ground. as well as A second absorption circuit is provided, with its first terminal connected to the second terminal of the first freewheeling power switch and its second terminal connected to the power reference ground.

12. The Heric circuit according to claim 11, characterized in that, The Heric circuit also includes a third absorption circuit; The first terminal of the third absorption circuit is connected to the second terminal of the second freewheeling power switch, and the second terminal of the third absorption circuit is connected to the power reference ground.

13. The Heric circuit according to claim 12, characterized in that, The first absorption circuit includes a first diode, a first absorption resistor, and a first absorption capacitor; The anode of the first diode is connected to the first terminal of the first freewheeling power switch, and the cathode of the first diode is connected to the first terminal of the first absorption resistor and the first terminal of the first absorption capacitor, respectively. The second end of the first absorption resistor is coupled to the DC bus; The second terminal of the first absorption capacitor is connected to the power reference ground; The second absorption circuit includes a second diode, a second absorption resistor, and a second absorption capacitor; The cathode of the second diode is connected to the second terminal of the first freewheeling power switch, and the anode of the second diode is connected to the first terminal of the second absorption resistor and the first terminal of the second absorption capacitor, respectively. The second terminal of the second absorption resistor and the second terminal of the second absorption capacitor are both connected to the power reference ground; The third absorption circuit includes a third diode, a third absorption resistor, and a third absorption capacitor; The cathode of the third diode is connected to the second terminal of the second freewheeling power switch, and the anode of the third diode is connected to the first terminal of the third absorption resistor and the first terminal of the third absorption capacitor, respectively. The second terminal of the third absorption resistor and the second terminal of the third absorption capacitor are both connected to the power reference ground.

14. The Heric circuit according to claim 11, characterized in that, The Heric circuit operates in either forward inverter mode or reverse rectification mode.

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