Wi-fi optical terminal 5g radio frequency front-end power timing control circuit and system

Abstract

The utility model relates to chip power supply time sequence control technical field, concretely to a kind of Wi-Fi optical terminal 5G radio frequency front-end power supply time sequence control circuit and system.Control method's steps include: through the initial low level signal output of GPIO39 pin of SOC main chip, control N-MOS tube Q2 and Q5 are in cut-off state, ensure that the EN pin of BUCK chip P4U1 maintains low level, cut off 5G radio frequency front-end and the 5V0_FEM power output of USB interface, to initialize enable signal control.After DC12V0_IN input power, the 2.5V power of DDR4, SOC core 1.2V / 0.9V power and 1V8_BUCK reference voltage are started preferentially, after the SOC core 1.2V / 0.9V power is stable and voltage fluctuation is less than 5% continuously 2ms, trigger GPIO39 pin output high level enable signal, to preferentially start core power time sequence.The utility model's Wi-Fi optical terminal 5G radio frequency front-end power supply time sequence control method, effectively solve the problem that existing technology in impact current is too large and energy storage capacitor energy utilization efficiency is low.

Description

Technical Field

[0001] This utility model relates to the field of chip power supply timing control technology, specifically a power supply timing control circuit and system for a 5G radio frequency front-end of a Wi-Fi optical terminal. Background Technology

[0002] In the power management design of wireless communication terminal equipment, the power timing control of the RF front-end and peripheral interfaces restricts the reliability and energy efficiency of the equipment. In existing solutions, for optical terminal products supporting high-speed wireless communication, the 5G RF front-end and USB interface are typically powered directly by the same buck converter circuit, which starts up synchronously with the core logic circuit upon power-up. While this design meets basic power supply requirements, it has significant drawbacks:

[0003] On the one hand, since the RF front-end and USB interface do not need to work immediately during the initial system startup, the instantaneous connection of their loads will cause a large inrush current on the power input side, posing a challenge to the stability of the power adapter and circuit.

[0004] On the other hand, during power-down, the continuous operation of the buck converter circuit consumes a significant amount of energy from the energy storage capacitor, resulting in insufficient energy reserves for critical information feedback and affecting the effective duration of the feedback signal. Especially in scenarios involving input voltage drops, balancing the timing of power cut-off for non-core loads with the energy distribution to the core circuitry has become a pressing technical challenge in existing designs. Utility Model Content

[0005] This disclosure proposes a 5G RF front-end power supply timing control circuit and system for Wi-Fi optical terminals, aiming to overcome at least one defect in the prior art.

[0006] To achieve the above objectives, the technical solution disclosed in this utility model is as follows:

[0007] According to one aspect of this disclosure, a power supply timing control circuit for a 5G radio frequency front-end of a Wi-Fi optical terminal is provided, the control circuit comprising:

[0008] The SOC interface module includes a GPIO39 pin and a PFI_DYING_GASP pin. The GPIO39 pin is connected to the gate of the N-MOS transistor Q2 through a resistor P4R8, and the PFI_DYING_GASP pin is connected to the nodes of voltage divider resistors PR1 and PR2.

[0009] A two-stage signal amplification circuit is provided, in which the sources of N-MOS transistors Q2 and Q5 are both grounded, and the drain of N-MOS transistor Q5 is connected to the EN pin of BUCK chip P4U1 to realize two-stage amplification and driving of GPIO39 signal.

[0010] The voltage divider feedback network consists of a voltage divider resistor PR1 connected to DC12V0_IN at one end and PR2 connected to ground at the other end. The node voltages are input to the EN pin of the BUCK chip P4U1 and the PFI_DYING_GASP pin of the SOC, respectively. The parallel capacitors P4C1 and P4C5 filter the voltage divider signal.

[0011] The BUCK power conversion circuit has the VIN pin of the BUCK chip P4U1 connected to DC12V0_IN, the SW pin connected to the output terminal 5V0_FEM through the inductor P4L1, and the FB pin grounded through resistors P4R2 and P4R5, and the resistor P4R4 connected to the 5V0_FEM output terminal to form a feedback regulation network.

[0012] The output filtering unit has capacitors P4C4, P4C6, P4C7, P4C8, P4C9, and P4C10 connected in parallel at the 5V0_FEM output terminal. Together with inductor P4L1, they form an LC filter circuit to suppress output ripple.

[0013] The energy storage buffer circuit has capacitors P4C2 and P4C3 connected in parallel at the DC12V0_IN input terminal to store transient energy and stabilize the input voltage.

[0014] Furthermore, the gate of the N-MOS transistor Q2 is connected to GPIO39 through resistor P4R8, and the drain is connected to the gate of the N-MOS transistor Q5. The gate of the N-MOS transistor Q5 is pulled up through resistor P4R9.

[0015] Furthermore, one end of resistor P4R2 is connected to the 5V0_FEM output terminal, and the other end is connected to the FB pin of the BUCK chip P4U1 through resistors P4R4 and P4R7. A capacitor P4C11 is connected in parallel across the two ends of resistor P4R4, and the other end of resistor P4R2 is grounded through resistor P4R5 to achieve feedback regulation of the output voltage.

[0016] According to another aspect of this disclosure, a 5G RF front-end power supply timing control system for a Wi-Fi optical terminal is provided, the control system comprising:

[0017] The power input module is connected to a DC12V±10% power supply. The output terminal of the power input module is connected to the DC12V0_IN interface of the control circuit and has a built-in surge protection device.

[0018] The timing control module integrates the control circuit described above. It communicates with the SOC main chip through GPIO39 and PFI_DYING_GASP pins and is used for enable control and voltage detection of the 5G RF front-end power supply of the Wi-Fi optical terminal.

[0019] The load drive module has its input terminal connected to the 5V0_FEM output terminal of the control circuit, which is used to power the 5G FEM chip and the USB interface, and the load drive module has a built-in overcurrent protection fuse.

[0020] The energy storage and filtering module includes capacitors P4C2 and P4C3 at the input end and capacitors P4C4, P4C6-P4C10 at the output end, which are used to maintain the stability of the power signal and transient response.

[0021] According to another aspect of this disclosure, a storage medium is provided that stores a computer program, which, when executed by a processor, implements the power supply timing control method for a 5G radio frequency front-end of a Wi-Fi optical terminal as described above.

[0022] The beneficial effects of this utility model are:

[0023] This invention provides a power supply timing control method for the 5G RF front-end of a Wi-Fi optical terminal, effectively solving the problems of excessive inrush current and low energy utilization efficiency of energy storage capacitors in existing technologies. Specifically, by using the GPIO pins of the SOC main chip to hierarchically control the enable signal of the buck converter circuit, delayed startup of the 5G RF front-end and USB interface power supply is achieved. This significantly reduces the load surge at power-on, effectively suppresses the inrush current, thereby improving the stability of the power input side and reducing the requirements for power adapter specifications.

[0024] Furthermore, the enable signal detection mechanism based on a precise voltage divider network design can promptly cut off the power supply to non-core loads at the initial power-down stage, reducing their energy consumption on the energy storage capacitor. This allows more energy to be used to maintain the operation of the core circuit and critical signal feedback, extending the effective feedback time. Through optimized hardware circuit design, this solution achieves intelligent control of power timing without complex software intervention. This improves the reliability of the device under voltage fluctuation scenarios and reduces hardware costs by decreasing the energy storage capacitor capacity requirement, providing an efficient and economical solution for power management of high-speed wireless communication terminals.

[0025] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, the preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0026] Figure 1 This is a flowchart of a power supply timing control method for a 5G radio frequency front-end of a Wi-Fi optical terminal in one embodiment of the present invention;

[0027] Figure 2This is a circuit diagram of the power supply timing control circuit for the 5G radio frequency front-end of a Wi-Fi optical terminal in one embodiment of this utility model;

[0028] Figure 3 This is a schematic diagram of the power tree structure of a Wi-Fi PON gateway in one embodiment of the present invention;

[0029] Figure 4 This is a power-on timing diagram of the SOC in one embodiment of the present invention;

[0030] Figure 5 This is a power-on timing diagram of DDR4 in one embodiment of the present invention;

[0031] Figure 6 This is a Wi-Fi power-on timing diagram in one embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0033] In the embodiments of this utility model, the words "exemplary" or "for example" and the descriptions within parentheses are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this utility model should not be construed as being more preferred or advantageous than other embodiments or designs.

[0034] refer to Figures 1 to 6 As shown, the present invention provides the following preferred embodiments:

[0035] Example 1

[0036] To address the issues of excessive inrush current during power-on and low energy utilization efficiency of energy storage capacitors during power-off in existing wireless communication terminal devices, this embodiment provides a power timing control method for the 5G RF front-end of a Wi-Fi optical terminal. It further optimizes the specific implementation of power timing control by controlling the signals of the GPIO pins of the SOC main chip and designing a voltage divider network to achieve precise timing management of the 5G RF front-end and USB interface power. Figure 1 As shown, the flow of the power supply timing control method is as follows:

[0037] S100: Outputs an initial low-level signal through the GPIO39 pin of the SOC main chip to control N-MOS transistors Q2 and Q5 to be in the off state, ensuring that the EN pin of the BUCK chip P4U1 remains at a low level, cutting off the 5V0_FEM power output of the 5G RF front-end and USB interface to initialize the enable signal control.

[0038] S200: After power-on at DC12V0_IN input, the DDR4 2.5V power supply, the SOC core 1.2V / 0.9V power supply and the 1V8_BUCK reference voltage are enabled first. After the SOC core 1.2V / 0.9V power supply stabilizes and the voltage fluctuation is less than 5% for 2ms, the GPIO39 pin is triggered to output a high-level enable signal to enable the core power timing first.

[0039] S300: The DC12V0_IN voltage is divided by voltage divider resistors PR1 and PR2 to generate an enable signal input to the EN pin of P4U1. When the divided voltage value reaches the power-on threshold of P4U1 (1.3V±2%), P4U1 is activated to start outputting 5V0_FEM power to detect the threshold of the voltage divider network enable signal.

[0040] S400: When the DC12V0_IN voltage drops to below the P4U1 power-down threshold of 1.2V±2%, the N-MOS transistors Q2 and Q5 are automatically turned off, the EN pin enable signal of P4U1 is cut off, and the 5V0_FEM power supply output is stopped to protect against input voltage drops.

[0041] S500: Reduces the energy consumption of the 5V0_FEM load on the energy storage capacitors P4C2 and P4C3, and utilizes energy storage to maintain the SOC core circuit to complete data preservation during the power-down transition phase, thereby optimizing the energy distribution of the energy storage capacitors.

[0042] Specifically, in the initial state, the GPIO39 pin of the SOC main chip outputs an initial low-level signal by default. This signal controls the gate voltages of N-MOS transistors Q2 and Q5, keeping them in the off state. It's important to understand that when an N-MOS transistor is off, the conductive path between its drain and source is broken, ensuring that the EN pin of the BUCK chip P4U1 cannot receive an enable voltage and remains in a low-level state. At this time, the power input from DC12V0_IN cannot be converted to 5V0_FEM power by P4U1, thus cutting off power to the 5G RF front-end and USB interface. The purpose of this operation is to prevent non-core loads from being connected during the initial system startup, suppressing the sudden load increase at power-on and reducing the impact on the power input side.

[0043] Furthermore, upon power-up of the DC12V0_IN input, the power system enters the core power priority startup phase. During this process, the 2.5V power supply for DDR4, the 1.2V / 0.9V power supply for the SOC core, and the 1V8_BUCK reference voltage are preferentially activated. These core power supplies provide stable operating voltages for critical components such as the SOC main chip and memory, forming the basis for system initialization and logic processing. Once the SOC core 1.2V / 0.9V power supply stabilizes and voltage fluctuations are less than 5% for 2ms, the system determines that the core circuit has entered a reliable operating state. At this point, the GPIO39 pin is triggered to switch from a low level to a high level enable signal. This high-level signal, through the gate control circuit of the N-MOS transistors, turns on N-MOS transistors Q2 and Q5, allowing the enable signal generated by the voltage divider network to be transmitted to the EN pin of P4U1, providing conditions for the subsequent startup of non-core load power supplies.

[0044] Furthermore, the DC12V0_IN voltage is divided by voltage divider resistors PR1 and PR2, and the generated voltage signal serves as the input to the EN pin of P4U1. When the DC12V0_IN voltage is within the normal operating range, the voltage division value changes with the input voltage. When this value reaches the P4U1's power-on threshold of 1.3V±2%, the EN pin is activated, and P4U1 begins normal operation and outputs a 5V0_FEM power supply. It should be noted that the resistance ratio of the voltage divider resistors needs to be designed according to the enable voltage range of P4U1 and the input voltage fluctuation range to ensure that when the input voltage is within 12V±10%, the voltage division value can accurately fall within the enable threshold range, thus avoiding both false triggering and startup lag.

[0045] Furthermore, in the scenario of input voltage drop, when the DC12V0_IN voltage drops to below the P4U1 power-down threshold of 1.2V±2%, the signal generated by the voltage divider network cannot maintain the effective level of the EN pin. At this time, N-MOS transistors Q2 and Q5 automatically turn off, cutting off the enable signal of the EN pin. P4U1 stops working due to the loss of effective enable, the 5V0_FEM power output is cut off, and the load on the 5G RF front-end and USB interface is removed, thus preventing them from continuing to consume the energy of the energy storage capacitor. The purpose of this mechanism is to preemptively cut off non-core loads before the input voltage drops to a level that affects the core circuitry, reserving limited energy storage for the core circuitry.

[0046] Through the above control process, the energy consumption of the 5V0_FEM load on the energy storage capacitors P4C2 and P4C3 is significantly reduced. During the power-down transition phase, the energy stored in the energy storage capacitors can maintain the operation of the SOC core circuit for a longer period of time, providing sufficient time to complete critical data saving and DYING GASP information feedback. Understandably, the timely disconnection of non-core loads reduces energy shunting, allowing the core circuit to maintain a stable operating state even when the voltage drops, thus improving the reliability of the equipment under abnormal power outage scenarios.

[0047] The advantage of this embodiment lies in its ability to achieve delayed startup and early shutdown of non-core load power supplies through the coordinated control of GPIO pin signals and a voltage divider network, effectively solving the problems of excessive power-on inrush current and wasted energy storage after power-off. This solution, through optimized hardware circuit design, achieves intelligent power timing control without complex software intervention. This improves the stability of the device under voltage fluctuation scenarios and extends the operating time of the core circuit through reasonable energy allocation, providing an efficient solution for power management of high-speed wireless communication terminals. The entire control process, based on real-time voltage signal detection and automatic hardware logic response, ensures the coordinated operation of various functional modules under different power states, meeting the reliability requirements of telecommunications standards for FTTR equipment.

[0048] Example 2

[0049] To address the issue of matching the driving capability of GPIO pins with the gate driving requirements of power MOSFETs, this embodiment further refines the signal amplification logic of N-MOS transistors. Through hierarchical control of hardware circuits, reliable signal transmission and logic conversion are achieved, ensuring precise control of power devices by the enable signal under different level states.

[0050] In the initial logic state, the GPIO39 pin of the SOC main chip is grounded by default using a built-in pull-down resistor. This pull-down resistor ensures that the pin outputs a stable low level when the system is not initialized, avoiding false triggering caused by floating states. At this time, the gate of N-MOS transistor Q2 is in the off state due to being connected to a low level, and its high impedance between its drain and source cuts off the signal path of subsequent circuits. Further, the gate of N-MOS transistor Q5 is connected to the DC12V0_IN input voltage through a pull-up resistor P4R9. When Q2 is off, the gate of Q5 is pulled up to a high voltage level. Since the gate-source voltage difference of an N-MOS transistor needs to exceed a threshold voltage to conduct, the gate-source voltage of Q5 is close to 12V, theoretically it should conduct. However, it should be understood that in this circuit design, the source of Q5 is not directly grounded, but connected to the output of a voltage divider network. Therefore, the actual gate-source voltage needs to be determined based on the circuit node potentials. When GPIO39 outputs a low level, Q2 is turned off, causing the gate of Q5 to be pulled up by P4R9. However, its source potential is affected by the voltage divider network and is at a low level when the EN pin is not activated. The gate-source voltage difference is insufficient to turn on Q5, thus ensuring that the EN pin of P4U1 remains at a low level.

[0051] Once the SOC core power supply stabilizes, the GPIO39 pin switches to a high-level output. At this point, the gate potential of Q2 rises, exceeding its threshold voltage and turning on. The conduction of Q2 pulls the gate voltage of Q5 down to near ground, ensuring the gate-source voltage difference of Q5 meets the conduction condition, and Q5 turns on. The function of Q5 is to transmit the enable signal generated by the voltage divider network to the EN pin of P4U1. At this point, the voltage on the EN pin is no longer controlled by the pull-up resistor, but is determined by the voltage division value of DC12V0_IN by voltage divider resistors PR1 and PR2. It should be noted that Q2, as a signal amplification stage, converts the low-drive-capacity signal of the GPIO pin into a high-current signal sufficient to drive Q5, avoiding insufficient voltage drop or response delay issues caused by GPIO directly driving Q5. This two-stage amplification structure, through level conversion and impedance matching, ensures that the enable signal can still quickly and accurately control the start and stop of P4U1 in scenarios with long traces or high capacitive loads.

[0052] In the signal transmission path, the value of the pull-up resistor P4R9 needs to balance power consumption and response speed. An excessively large value may cause gate charging delay for Q5, while an excessively small value will increase static power consumption. The combination of the built-in pull-down resistor and the external pull-up resistor forms a reliable high / low level clamping mechanism, avoiding signal oscillations caused by electromagnetic interference or power fluctuations. This design is particularly important in high-temperature or voltage-fluctuation environments, ensuring that the switching state of the N-MOS transistor is controlled solely by the GPIO signal, eliminating the influence of external noise.

[0053] The advantage of this embodiment lies in the fact that a reliable level transmission link is constructed through signal amplification and logic conversion using two stages of N-MOS transistors, solving the matching problem between the driving capability of the microcontroller pins and the driving requirements of the power conversion chip's enable terminal. It not only achieves effective low-level cutoff and reliable high-level conduction of the enable signal, but also ensures signal stability under different power supply states through the cooperation of a voltage divider network and pull-up / pull-down resistors. This provides a reliable front-end control circuit for the subsequent threshold detection of the voltage divider network, improving the anti-interference capability and logic response accuracy of the entire power timing control system.

[0054] Example 3

[0055] To address the issue of insufficient accuracy in enabling signal threshold detection, this embodiment further clarifies the parameter design method of the voltage divider network. By establishing a mathematical mapping relationship between the input voltage and the enabling signal, it ensures that P4U1 achieves accurate power-on startup and power-off protection within the input voltage fluctuation range, thus avoiding power supply malfunctions caused by threshold drift.

[0056] The core function of the voltage divider network is to convert the high voltage of DC12V0_IN into a low voltage signal suitable for the EN pin of P4U1 to recognize. Its working principle is based on the voltage divider principle of Ohm's law. Specifically, voltage divider resistors PR1 and PR2 are connected in series between DC12V0_IN and ground, and the EN pin is connected to the node of the two resistors. Therefore, the voltage VEN at the EN pin satisfies the voltage divider formula:

[0057] Among them, V EN V is the voltage at the EN pin of P4U1. IN The input voltage is DC12V0_IN, and PR1 and PR2 are the resistance values ​​of the voltage divider resistors. In practice, it is necessary to ensure that when VIN is at the rated input voltage of 12V, VEN falls within the power-on threshold range of P4U1, which is 1.3V ± 2%, i.e., 1.274V to 1.326V. By adjusting the resistance ratio of PR1 and PR2, for example, selecting PR1 as a high-precision thin-film resistor and PR2 as a temperature-coefficient matched surface-mount resistor, the voltage divider error can be controlled within ±1%, meeting the chip's threshold requirements.

[0058] In input voltage drop detection scenarios, the calculation of the power-down threshold requires reverse derivation of the input voltage protection point. Based on the power-down threshold of P4U1 (1.2V ± 2%, i.e., 1.176V to 1.224V), the protection threshold of DC12V0_IN can be obtained using the voltage divider formula:

[0059] Among them, V TH_DOWNThis is the power-down threshold voltage. This calculation process needs to consider the resistance tolerance range. By selecting resistors with an accuracy of ±1%, it is ensured that the actual protection threshold remains within the design range after temperature changes or prolonged operation. For example, when PR1 = 100kΩ and PR2 = 10kΩ, the input voltage range corresponding to the power-up threshold is 11.74V to 12.26V, and the input voltage range corresponding to the power-down threshold is 10.92V to 11.34V, forming a hysteresis voltage of 0.82V. This prevents frequent start-up and shutdown of the EN pin caused by fluctuations in the input voltage near the threshold.

[0060] It's important to understand that the PCB layout of the voltage divider network is equally crucial for detection accuracy. Short traces and low parasitic capacitance routing should be used to reduce the impact of high-frequency noise on voltage sampling. Simultaneously, connecting a high-frequency filter capacitor in parallel across the voltage divider resistors can suppress transient fluctuations in the input voltage, ensuring the stability of the VEN signal. This hardware-level threshold detection scheme eliminates the need for real-time software calculations, achieving real-time voltage signal mapping through a fixed resistor network, reducing system resource consumption and improving response speed.

[0061] The advantage of this embodiment lies in the fact that, through precise voltage divider resistor ratios and threshold calculation formulas, a voltage detection mechanism with hysteresis characteristics is constructed, ensuring that P4U1 operates stably under normal input voltage fluctuations and shuts down promptly in case of abnormal voltage drops. This solution achieves precise threshold control through hardware circuitry, avoiding the delay issues of software detection. Simultaneously, it utilizes the physical characteristics of resistors to ensure the long-term stability of the threshold, providing a reliable voltage reference for power supply timing control and improving the system's adaptability and reliability under wide voltage input scenarios.

[0062] Example 4

[0063] To address the timing synchronization issue between the core power supply and non-core load power supplies, this embodiment further clarifies the method for determining the startup delay time of the SOC core power supply and the power-on interlock detection mechanism. Through hardware signal monitoring and software logic coordination, it ensures that the 5G RF front-end power supply only starts after the core system is fully ready, avoiding functional abnormalities caused by incomplete initialization.

[0064] In the core power-on process, the 1V8_BUCK reference voltage serves as a reference signal for system initialization, and its stability is a crucial factor in determining whether the core circuitry can function properly. Once the 1V8_BUCK voltage stabilizes, the system enters a delay waiting phase. The delay time T is designed to be no less than the sum of 1ms and the software response time Δt. Here, 1ms is a hardware stabilization margin used to compensate for power converter startup overshoot and oscillation; Δt is the time required for the SOC main chip to complete register initialization and configure GPIO pin states, determined by a combination of typical values ​​from the chip datasheet and actual measured values ​​after program optimization. The purpose of this delay mechanism is to ensure that the SOC main chip has completed internal logic initialization, preventing the GPIO39 pin from outputting an invalid signal before configuration is complete, which could lead to a false start-up of the P4U1.

[0065] In the power-on interlock detection phase, the system monitors the VEN signal output by the voltage divider network in real time via the PFI_DYING_GASP pin. P4U1 is only triggered to start working when the DC12V0_IN voltage is ≥10.64V (corresponding to VEN ≥1.326V, i.e., 102% of the upper limit of the power-on threshold) and the high level on the GPIO39 pin lasts for 1ms. This condition setting includes two layers of interlock logic: first, voltage amplitude detection, ensuring that the input voltage not only reaches the power-on threshold but also has a 2% safety margin to avoid unstable startup under critical voltage; second, signal duration detection, using a 1ms high-level holding time to filter out transient interference signals and prevent false triggering.

[0066] During timing control, the SOC main chip uses an internal timer to precisely control the delay time, while simultaneously monitoring the VEN signal using a hardware interrupt pin to avoid resource consumption caused by software polling. This hardware and software collaborative interlocking mechanism establishes a dual confirmation process between core power supply stabilization and non-core load startup, ensuring that high-power modules such as the 5G RF front-end are only connected when the system has full operational capability. This reduces power surges during startup and improves the collaborative reliability of various functional modules.

[0067] The advantage of this embodiment lies in the fact that, through the quantitative design of delay time and multiple constraints on power-on interlock conditions, a rigorous timing startup process is constructed, ensuring that the startup of non-core load power supplies is completely synchronized with the initialization progress of the core system. This solution not only avoids functional abnormalities caused by startup timing disorder, but also improves the system's anti-interference capability in complex electromagnetic environments through dual detection of voltage amplitude and duration, providing reliable power protection for the stable operation of high-speed wireless communication modules and meeting the stringent timing control requirements of communication equipment.

[0068] Example 5

[0069] To address the issue of insufficient energy supply to the core circuit during the power-down transition phase, this embodiment further optimizes the configuration method of the energy storage capacitors. By connecting energy storage capacitors P4C2 and P4C3 in parallel at the input power supply terminal, a local energy storage unit is constructed to effectively suppress the transient current of the 5V0_FEM load and prioritize the allocation of energy to the core circuit.

[0070] The principle of energy storage capacitor configuration is to form a low-impedance energy storage node at the DC12V0_IN input terminal. By increasing the capacitive energy storage capacity of this node, transient fluctuations in the input voltage are absorbed, reducing the impact on the main power supply during the startup of the 5V0_FEM power supply. Specifically, P4C2 and P4C3 use a combination of electrolytic capacitors and ceramic capacitors connected in parallel. The electrolytic capacitors provide a large capacity of energy storage to meet the continuous power supply requirements of the core circuit when power is off; the ceramic capacitors suppress high-frequency noise and improve the transient response characteristics of the power supply. The voltage rating of the capacitors must be higher than the peak input voltage, such as 16V. The capacitance is calculated based on the power consumption of the core circuit when power is off, ensuring that after disconnecting non-core loads, the remaining energy can sustain the SOC core circuit for at least 5ms to complete the data saving operation.

[0071] In terms of circuit layout, the energy storage capacitor should be placed as close as possible to the DC12V0_IN input interface and the BUCK chip P4U1 to shorten the current path, reduce line impedance, and improve energy storage efficiency. When the 5V0_FEM power supply starts up, its transient peak current is first provided by the energy storage capacitor, reducing the instantaneous load on the input power supply, thereby reducing voltage fluctuations in the main power supply and avoiding affecting the stability of the core circuit. During the power-down phase, when the input voltage is detected to drop below the power-down threshold, the 5G RF front-end load is disconnected. The energy stored in the energy storage capacitor is no longer released to non-core loads, but is used entirely to maintain the 1.2V / 0.9V power supply of the SOC core and the 2.5V power supply of DDR4, ensuring that the processor has enough time to execute the power-down protection program.

[0072] It is important to understand that the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the energy storage capacitor have a significant impact on energy release efficiency. Choosing tantalum capacitors or polymer electrolytic capacitors with low ESR can reduce energy loss and extend discharge time. Furthermore, by assigning P4C2 and P4C3 as the main energy storage capacitor and high-frequency filter capacitor respectively, addressing energy demands at different time scales, a hierarchical energy storage structure is formed. This not only meets the requirements of high-current discharge but also suppresses high-frequency noise interference to the core circuit.

[0073] The advantage of this embodiment lies in the fact that, through the rational configuration of the input-side energy storage capacitors, a local energy storage system independent of the load power supply is constructed, effectively reducing the transient impact of the 5V0_FEM load on the main power supply, while simultaneously achieving directional energy distribution during power-down. This solution, through hardware-level energy storage optimization, eliminates the need for complex energy management chips; simply through capacitor selection and layout design, it significantly improves the operational stability of the core circuit during power-down transitions, providing physical-layer protection for the reliable storage of critical data and enhancing the device's fault tolerance in abnormal power-down scenarios.

[0074] Example 6

[0075] To address the optimization requirements of existing power supply timing control circuits in terms of driving capability and signal stability, this embodiment provides a 5G RF front-end power supply timing control circuit for a Wi-Fi optical terminal, further refining the hardware connections and functional module collaboration mechanisms of the control circuit. The control circuit is built on the PON gateway hardware platform of the Wi-Fi solution and is specifically designed for 5G RF front-end power supply timing control.

[0076] Specifically, the SOC interface module, acting as the interaction hub between the control circuit and the main chip, uses a 1.8V standard for its GPIO39 pin. By default, it is grounded via a built-in pull-down resistor to ensure the BUCK circuit is initially disabled, preventing power-on surges. The GPIO39 pin is connected to the gate of the N-MOS transistor Q2 via resistor P4R8, which serves both current limiting and signal matching functions, preventing damage to the MOS transistor from sudden gate voltage changes. The PFI_DYING_GASP pin is connected to the series connection of voltage divider resistors PR1 and PR2, used to monitor the trigger signal when the input voltage drops in real time, providing a voltage reference for system feedback.

[0077] Furthermore, the two-stage signal amplification circuit is composed of N-MOS transistors Q2 and Q5, both with their sources directly grounded, forming a common-source amplification structure. The drain of Q2 is connected to the gate of Q5, realizing step-by-step signal amplification: when GPIO39 outputs a high level, Q2 is turned on, pulling down the gate-to-ground impedance of Q5, causing Q5 to turn on, and its drain outputs a high level to the EN pin of the BUCK chip P4U1, completing the enable drive; conversely, when GPIO39 is low, Q2 is turned off, and the gate of Q5 remains in the off state through default grounding, with no drive signal on the EN pin. This two-stage amplification design effectively improves the driving capability of the GPIO signal, ensuring reliable control of the BUCK circuit even in long traces or high capacitive load scenarios.

[0078] Furthermore, the voltage divider feedback network consists of voltage divider resistors PR1 and PR2 and filter capacitors P4C1 and P4C5. One end of PR1 is connected to the input power supply DC12V0_IN, and one end of PR2 is grounded. The node voltage is simultaneously input to the EN pin of P4U1 and the PFI_DYING_GASP pin of the SOC. It's important to understand that this network has a dual function: for the BUCK circuit, the node voltage is used to determine whether the input voltage meets the enable threshold; for the system, the PFI_DYING_GASP pin feeds back the voltage drop status to the main chip, triggering the corresponding protection mechanism. The parallel capacitors filter out high-frequency noise, ensuring the stability of the voltage detection signal.

[0079] Furthermore, the BUCK power conversion circuit uses the P4U1 chip as its core. The VIN pin is connected to DC12V0_IN, and the SW pin is connected to the output terminal 5V0_FEM through inductor P4L1, forming a typical buck converter topology. The FB pin is grounded through resistors P4R2 and P4R5 and connected to the output terminal through P4R4, forming a closed-loop feedback network to adjust the duty cycle of the switching transistor in real time to stabilize the output voltage. The output filter unit consists of multiple capacitors of different capacitance values ​​connected in parallel, which, together with inductor P4L1, form an LC filter circuit to effectively suppress switching ripple and meet the stringent power supply noise requirements of the 5G FEM chip. The energy storage buffer circuit connects capacitors P4C2 and P4C3 in parallel on the input side to store transient energy, mitigating the impact of input voltage fluctuations on the downstream circuits, especially maintaining short-term power supply during power switching or load changes, thus improving system robustness.

[0080] Furthermore, the signal flow between modules follows timing control logic: In the initial stage of power-on, GPIO39 is at a low level by default, the two-stage amplifier circuit is cut off, and the BUCK circuit does not work, to avoid premature power consumption of the 5G FEM and USB interface; when the system initialization is completed, the main chip outputs a high level through GPIO39, which enables the BUCK circuit through two-stage amplification, gradually loading the load and suppressing inrush current; when power-off, the voltage divider network detects the input voltage drop and shuts down the BUCK circuit in advance to reduce energy storage capacitor consumption and extend the DYING GASP feedback time.

[0081] The advantages of this embodiment are that the modular design clarifies the electrical connection and coordination mechanism of each functional unit, the two-stage amplification circuit enhances the reliability of signal driving, the voltage divider feedback network realizes the deep integration of voltage detection and timing control, and the output and energy storage filter circuit ensures power quality and transient response capability. This embodiment provides a complete implementation path for power timing control at the hardware level, meeting the stringent reliability and energy efficiency requirements of telecommunications FTTR equipment.

[0082] Example 7

[0083] To address the issues of gate signal stability and drive capability optimization in a two-stage signal amplifier circuit, this embodiment further refines the gate bias structure of the N-MOS transistor. By setting a pull-up resistor P4R9 at the gate of the N-MOS transistor Q5, a reliable static bias network is constructed to ensure the accuracy of signal transmission and anti-interference capability.

[0084] Based on the two-stage signal amplification circuit of the aforementioned embodiment, this embodiment explicitly connects the drain of N-MOS transistor Q2 directly to the gate of Q5, forming the front-stage drive path. Simultaneously, the gate of Q5 is connected to the stable voltage node after the DC12V0_IN voltage divider via resistor P4R9, forming a pull-up bias structure. It should be understood that this pull-up resistor is designed to provide a default high-level bias for the gate of Q5, ensuring that the gate potential of Q5 remains stable above the effective enable threshold when there is no drive signal input, thus avoiding state uncertainty issues caused by a floating signal link.

[0085] The specific circuit connection is as follows: The GPIO39 pin of the SOC interface module is connected to the gate of Q2 through resistor P4R8. This resistor serves both current limiting and level matching functions to prevent excessive GPIO output current from damaging the device. The source of Q2 is grounded, and the drain is connected to the gate of Q5, forming the first stage of the common-source amplifier structure. The source of Q5 is also grounded, and the drain is connected to the EN pin of the BUCK chip P4U1. In addition to receiving the drain signal of Q2, its gate is pulled up to the reference voltage after the DC12V0_IN voltage divider through P4R9 to ensure that Q5 maintains a certain level state in the initial state or during signal transmission gaps.

[0086] The working principle of this embodiment is as follows: When GPIO39 outputs a low level (default state or system standby), the gate voltage of Q2 is lower than the conduction threshold of the N-MOS transistor, so Q2 is turned off. At this time, the gate of Q5 is pulled up to a voltage higher than its conduction threshold (e.g., 3.3V) through P4R9, Q5 turns on, and the drain voltage approaches the source potential (ground level), thereby pulling the EN pin low and turning off the BUCK power conversion circuit. When GPIO39 outputs a high level (power enabled after system initialization), Q2 turns on, the drain voltage drops to near ground level, the gate of Q5 is pulled down to a level lower than the conduction threshold, Q5 is turned off, and the EN pin is pulled up to the enable voltage (e.g., 2.5V) through the voltage divider feedback network (composed of PR1 and PR2), triggering the BUCK chip to work and outputting a 5V0_FEM power supply. This negative logic control mechanism ensures that Q5 is reliably turned on when Q2 is turned off through the pull-up resistor P4R9, avoiding false turn-off caused by a floating gate, thereby ensuring the stable shutdown of the BUCK circuit in standby mode.

[0087] It's important to understand that the values ​​of resistors P4R8 and P4R9 must meet the circuit's driving requirements: P4R8's value needs to be determined based on the output capability of GPIO39 and the gate capacitance of Q2, typically ranging from 10kΩ to 50kΩ, to limit transient current and suppress ringing effects; the value of P4R9 must ensure that the gate voltage after pull-up is higher than the threshold voltage of Q5, while also considering power consumption optimization, with typical values ​​ranging from 4.7kΩ to 10kΩ. The combination of these two resistors allows Q2 to effectively pull down the gate potential of Q5 when it is on, and maintains a high gate level for Q5 when it is off through P4R9, forming a clear switching logic boundary.

[0088] Furthermore, the introduction of pull-up resistors improves the circuit's anti-interference performance. In high-frequency electromagnetic environments, unterminated gate pins are susceptible to noise, leading to gate voltage fluctuations and causing Q5 to malfunction. By fixing the gate to a stable potential using P4R9, the effects of common-mode and differential-mode noise are effectively suppressed, ensuring the purity of signal transmission. Simultaneously, the two-stage amplification structure, through the current amplification of Q2, converts the small drive current of GPIO39 into the gate control signal for Q5, solving the problem of insufficient pin drive capability in the SOC main chip. This is particularly suitable for scenarios with long-distance control signal traces in PCB layouts, avoiding drive failure due to signal attenuation.

[0089] The advantage of this embodiment is that by setting a pull-up resistor P4R9 on the gate of Q5, a stable static bias mechanism is constructed, eliminating the state uncertainty caused by gate floating and ensuring reliable operation of the two-stage amplifier circuit when the timing control signal switches. This design optimizes the anti-interference capability of signal transmission, enhances the accuracy of BUCK circuit enable control, and provides a more stable hardware foundation for the power timing control of the 5G RF front-end of Wi-Fi optical terminals, meeting the requirements for long-term reliable operation of communication equipment in complex electromagnetic environments.

[0090] Example 8

[0091] To address the output voltage stability issue of the BUCK power conversion circuit, this embodiment further refines the resistor and capacitor configuration of the feedback regulation network. By optimizing the voltage division ratio and frequency response of the feedback path, precise control of the 5V0_FEM output voltage is achieved.

[0092] The feedback regulation network uses the FB pin of the BUCK chip P4U1 as its core, constructing a voltage negative feedback closed loop. One end of resistor P4R2 is connected to the 5V0_FEM output terminal, and the other end is connected to the FB pin through resistors P4R4 and P4R7 in series. Simultaneously, capacitor P4C11 is connected in parallel across P4R4 to form an RC filter, suppressing high-frequency noise interference with the feedback signal. The other end of P4R2 is also grounded through resistor P4R5, forming a voltage divider circuit with P4R4 and P4R7. This circuit proportionally converts the output voltage into the feedback voltage of the FB pin, compares it with the chip's internal reference voltage, and adjusts the duty cycle of the switching transistor.

[0093] It's important to understand that the resistance ratio of the feedback resistors directly determines the output voltage setting. Based on the reference voltage of the P4U1 chip, in this embodiment, P4R2 and P4R5 form a pull-down resistor, and P4R4 and P4R7 form a pull-up resistor. The actual ratio must meet the 5V output requirement. The function of capacitor P4C11 is to compensate for the phase margin of the feedback loop, avoid high-frequency oscillation, and improve loop stability. Its capacitance value needs to be selected in conjunction with the inductance value of inductor P4L1 and the ESR characteristics of the output capacitor, and the optimal compensation point should be determined through Bode plot analysis.

[0094] The feedback regulation process is as follows: When the 5V0_FEM output voltage increases, the FB pin voltage also increases. The internal controller of the chip reduces the duty cycle and decreases the output pulse width of the SW pin, thereby lowering the output voltage. Conversely, when the output voltage decreases, the duty cycle increases, increasing the output voltage, thus forming a dynamic balance. The introduction of resistor P4R7 increases the adjustable parameters of the feedback loop, allowing fine-tuning of the voltage division ratio under different load conditions to ensure that the voltage regulation rate meets the specifications under light and heavy loads.

[0095] Furthermore, the multiple capacitors (P4C4, P4C6-P4C10) in the output filter unit employ different capacitance combinations to balance low-frequency filtering and high-frequency decoupling: large-capacity electrolytic capacitors suppress low-frequency ripple, while small-capacity ceramic capacitors handle high-frequency noise. Together with inductor P4L1, they form a multi-stage filter network, controlling the output ripple below 50mV to meet the stringent power supply noise requirements of 5G RF chips. The coordinated design of the feedback network and filter circuit effectively reduces voltage overshoot and sag during load transient response, improving the dynamic performance of the power supply system.

[0096] The advantage of this embodiment is that by precisely designing the resistor ratio and RC compensation parameters of the feedback regulation network, high-precision stability of the BUCK circuit output voltage is achieved. Combined with the multi-stage filtering structure, the power quality is significantly improved, providing a clean and stable power supply environment for the 5G RF front end. At the same time, the adaptability of the power system in a wide load range is enhanced, ensuring reliable operation of the equipment under different working conditions.

[0097] Example 9

[0098] To address the integration and reliability issues of power timing control systems, this embodiment proposes a 5G RF front-end power timing control system for Wi-Fi optical terminals. It constructs a complete hardware architecture that includes power input, timing control, load driving, and energy storage filtering. The modules work together to achieve full-link control of the 5G RF front-end power supply.

[0099] Specifically, the power input module connects to a DC 12V ± 10% power supply (10.8V~13.2V). Its output terminal, DC 12V 0_IN, incorporates surge protection devices, such as TVS diodes or varistors, to suppress transient interference from the power grid and protect downstream circuitry from high-voltage surges. The module employs a reverse connection protection design, using Schottky diodes or MOSFETs for polarity protection to prevent damage to components caused by reverse power connection.

[0100] Furthermore, the timing control module integrates a power supply timing control circuit for the 5G RF front-end of the Wi-Fi optical terminal. It communicates with the SOC main chip via GPIO39 and the PFI_DYING_GASP pin: GPIO39 receives the enable control signal from the main chip, which drives the BUCK chip through a two-stage amplification circuit; the PFI_DYING_GASP pin provides real-time feedback on the input voltage drop status, triggering the main chip to execute the DYING GASP information reporting process. The module employs a multi-layer PCB layout to isolate the high-frequency switching circuit from the low-frequency control circuit, reducing electromagnetic coupling interference and ensuring signal integrity.

[0101] Furthermore, the load drive module's input is connected to the 5V0_FEM output to power the 5G FEM chip and the USB interface. It integrates an overcurrent protection fuse that quickly blows when the load current exceeds the rated value (e.g., 3A), cutting off the power path and preventing device burnout or PCB trace damage due to overcurrent. This module employs a distributed power supply design, with the 5G FEM and USB interface connected to the output via independent traces, reducing noise coupling between them and ensuring the purity of the RF signal.

[0102] Furthermore, the energy storage and filtering module includes electrolytic capacitors P4C2 and P4C3 on the input side to store transient energy and maintain short-term power supply during power input fluctuations, meeting the energy requirements during DYING GASP feedback. Multiple ceramic capacitors (P4C4, P4C6-P4C10) on the output side form a high-frequency decoupling network, which, together with inductor P4L1, suppresses switching ripple and ensures low-noise characteristics of the output voltage. The layout of the input and output capacitors follows the principle of "close to power supply, close to load," shortening the high-frequency current loop and reducing the impact of parasitic inductance.

[0103] The workflow of this embodiment is as follows: Upon power-up, the power input module filters surge signals, the energy storage capacitor charges, the timing control module waits for the main chip to complete initialization, enables the BUCK circuit through GPIO39, and the load drive module gradually loads the power supply to the 5GFEM and USB interface; Upon power-down, the voltage divider feedback network detects that the input voltage is lower than 9.43V, triggers the PFI_DYING_GASP signal, the main chip startup information is reported, and at the same time, the timing control module closes the BUCK circuit, cuts off the load power supply, reduces energy storage capacitor consumption, and extends the feedback time.

[0104] Furthermore, the electrical isolation and grounding design between modules follows EMC specifications. Power ground and signal ground are connected through a single-point grounding connection to avoid ground loop noise and ensure stable operation of the system in complex electromagnetic environments. The overcurrent protection threshold and fuse specifications of the load drive module are set according to the maximum operating current of the 5G FEM chip, balancing protection sensitivity and normal operating margin.

[0105] The advantages of this embodiment are that, through modular integrated design, a complete control link from power input to load drive is constructed, surge protection and overcurrent protection mechanisms improve system safety, energy storage filtering and electromagnetic compatibility design ensure power quality and reliability, and the collaborative work of timing control module and main chip realizes precise timing management of 5G RF front-end power supply.

[0106] Although the present invention has been specifically described above with reference to preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above. Rather, various modifications and variations can be made by those skilled in the art without departing from the essence of the present invention, and such modifications and variations should fall within the scope defined by the appended claims and their equivalents.

Claims

1. A power supply timing control circuit for a 5G radio frequency front-end of a Wi-Fi optical terminal, characterized in that, The control circuit includes: The SOC interface module includes a GPIO39 pin and a PFI_DYING_GASP pin. The GPIO39 pin is connected to the gate of the N-MOS transistor Q2 through a resistor P4R8, and the PFI_DYING_GASP pin is connected to the nodes of voltage divider resistors PR1 and PR2. A two-stage signal amplification circuit is provided, in which the sources of N-MOS transistors Q2 and Q5 are both grounded, and the drain of N-MOS transistor Q5 is connected to the EN pin of BUCK chip P4U1 to realize two-stage amplification and driving of GPIO39 signal. The voltage divider feedback network consists of a voltage divider resistor PR1 connected to DC12V0_IN at one end and PR2 connected to ground at the other end. The node voltages are input to the EN pin of the BUCK chip P4U1 and the PFI_DYING_GASP pin of the SOC, respectively. The parallel capacitors P4C1 and P4C5 filter the voltage divider signal. The BUCK power conversion circuit has the VIN pin of the BUCK chip P4U1 connected to DC12V0_IN, the SW pin connected to the output terminal 5V0_FEM through the inductor P4L1, and the FB pin grounded through resistors P4R2 and P4R5, and the resistor P4R4 connected to the 5V0_FEM output terminal to form a feedback regulation network. The output filtering unit has capacitors P4C4, P4C6, P4C7, P4C8, P4C9, and P4C10 connected in parallel at the 5V0_FEM output terminal. Together with inductor P4L1, they form an LC filter circuit to suppress output ripple. The energy storage buffer circuit has capacitors P4C2 and P4C3 connected in parallel at the DC12V0_IN input terminal to store transient energy and stabilize the input voltage.

2. The Wi-Fi optical terminal 5G RF front-end power supply timing control circuit as described in claim 1, characterized in that, The gate of the N-MOS transistor Q2 is connected to GPIO39 through resistor P4R8, and the drain is connected to the gate of the N-MOS transistor Q5. The gate of the N-MOS transistor Q5 is pulled up through resistor P4R9.

3. The Wi-Fi optical terminal 5G RF front-end power supply timing control circuit as described in claim 1, characterized in that, One end of resistor P4R2 is connected to the 5V0_FEM output terminal, and the other end is connected to the FB pin of the BUCK chip P4U1 through resistors P4R4 and P4R7. A capacitor P4C11 is connected in parallel across the two ends of resistor P4R4, and the other end of resistor P4R2 is grounded through resistor P4R5 to achieve feedback regulation of the output voltage.

4. A 5G RF front-end power supply timing control system for a Wi-Fi optical terminal, characterized in that, The control system includes: The power input module is connected to a DC12V±10% power supply. The output terminal of the power input module is connected to the DC12V0_IN interface of the control circuit and has a built-in surge protection device. The timing control module integrates the control circuit as described in any one of claims 1-3, and communicates with the SOC main chip through GPIO39 and PFI_DYING_GASP pins for enable control and voltage detection of the 5G RF front-end power supply of the Wi-Fi optical terminal. The load drive module has its input terminal connected to the 5V0_FEM output terminal of the control circuit, which is used to power the 5G FEM chip and the USB interface, and the load drive module has a built-in overcurrent protection fuse. The energy storage and filtering module includes capacitors P4C2 and P4C3 at the input end and capacitors P4C4, P4C6-P4C10 at the output end, which are used to maintain the stability of the power signal and transient response.

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