Delay circuit and drive circuit
By introducing a bias current generation unit and a delay unit into the drive circuit, and utilizing a design where current and voltage are proportional, the problem of uncontrollable delay time in traditional drive circuits is solved, achieving accuracy and controllability of delay time.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CRM ICBG (WUXI) CO LTD
- Filing Date
- 2025-07-22
- Publication Date
- 2026-07-21
AI Technical Summary
The delay time of traditional drive circuits is uncontrollable or inaccurate because the resistance varies with process parameters, temperature and power supply voltage fluctuations.
By employing a bias current generation unit and a delay unit, and controlling the charging and discharging process of the capacitor, and utilizing a design where current and voltage are proportional, the delay duration is ensured to be independent of the voltage at the voltage source terminal, thereby achieving accuracy and controllability of the delay duration.
It effectively offsets the impact of voltage source deviation on delay duration, improves the accuracy and controllability of delay circuit, and ensures the stability of charging and discharging delay duration.
Smart Images
Figure CN224538173U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of driving circuit technology, and in particular to a delay circuit and a driving circuit. Background Technology
[0002] In related technologies, traditional drive circuits typically generate delays using RC circuits, with the delay duration usually determined by an RC structure. However, because the resistance fluctuates significantly with process parameters, temperature, and power supply voltage, changes in these factors lead to substantial variations in the charging and discharging currents of the delay circuit. This results in changes to the delay duration, making it uncontrollable or inaccurate. Utility Model Content
[0003] This application provides an improved delay circuit and driving circuit to solve at least one problem in the prior art.
[0004] This application provides a delay circuit, including:
[0005] A bias current generating unit includes a voltage source terminal, a ground terminal, a first current output terminal, and a second current output terminal. The first current output terminal is used to output a first current, and the second current output terminal is used to output a second current. Both the first current and the second current are proportional to the voltage of the voltage source terminal.
[0006] The delay unit includes a control terminal, a selection switch, a capacitor, and a first inverter. The control terminal is connected to the selection switch, which is also connected to the capacitor, the voltage source terminal, and the ground terminal. A first current output terminal is connected between the voltage source terminal and the selection switch, and a second current output terminal is connected between the selection switch and the ground terminal. The selection switch, controlled by the control terminal, selectively connects the capacitor and the voltage source terminal to charge the capacitor with the first current, or connects the capacitor and the ground terminal to discharge the capacitor with the second current. The capacitor is connected to the first inverter, and the switching threshold voltage of the first inverter is proportional to the voltage of the voltage source terminal.
[0007] Optionally, the bias current generating unit includes a reference current generating module, a first current mirror, and a second current mirror. The reference current generating module generates a reference current that is proportional to the voltage at the voltage source terminal. The first current mirror is connected to both the reference current generating module and the first current output terminal, and is used to generate the first current based on the mirror image of the reference current. The second current mirror is connected to both the reference current generating module and the second current output terminal, and is used to generate the second current based on the mirror image of the reference current.
[0008] Optionally, the reference current generating module includes a resistor and a first transistor, the resistor and the first transistor being connected in series between the voltage source terminal and the ground terminal, and the ratio of the voltage at the voltage source terminal to the PN junction voltage drop of the first transistor being greater than a set ratio.
[0009] Optionally, the reference current generation module further includes a second transistor, which forms a third current mirror with the first transistor.
[0010] Optionally, the reference current generating module further includes a first adjustable resistor and a second adjustable resistor, wherein the first adjustable resistor is connected between the first transistor and the ground terminal, and the second adjustable resistor is connected between the second transistor and the ground terminal.
[0011] Optionally, both the first adjustable resistor and the second adjustable resistor include a fuse adjustment component, which includes multiple fuses. By blowing at least one of the multiple fuses, the magnitude of the corresponding first adjustable resistor and the second adjustable resistor is adjusted.
[0012] Optionally, the selection switch includes a first switch and a second switch. The control terminal is connected to both the first switch and the second switch. The first switch is connected between the voltage source and the capacitor, and the second switch is connected between the capacitor and the ground terminal. When the first switch is controlled to be turned on by the control terminal and the second switch is controlled to be turned off by the control terminal, the first switch connects the capacitor and the voltage source. When the second switch is controlled to be turned on by the control terminal and the first switch is controlled to be turned off by the control terminal, the second switch connects the capacitor and the ground terminal.
[0013] Optionally, the first switching transistor is a p-type MOSFET, the second switching transistor is an n-type MOSFET, the gates of both the first and second switching transistors are connected to the control terminal, the source of the first switching transistor is connected to the voltage source terminal, the drain of the first switching transistor is connected to the drain of the second switching transistor, and both are connected to one end of the capacitor, and the source of the second switching transistor and the other end of the capacitor are connected to the ground terminal.
[0014] Optionally, the first inverter is a Schmitt inverter.
[0015] Optionally, the delay circuit includes a second inverter and two delay units, the two delay units being a first delay unit and a second delay unit, the second inverter being connected between the first delay unit and the second delay unit; the bias current generating unit further includes a third current output terminal and a fourth current output terminal, the bias current generating unit being used to generate a third current and a fourth current, both of which are proportional to the voltage at the voltage source terminal;
[0016] The first current output terminal and the second current output terminal are connected to the first delay unit, and the first current and the second current are the charging current and the discharging current of the first delay unit, respectively; the third current output terminal and the fourth current output terminal are connected to the second delay unit, and the third current and the fourth current are the charging current and the discharging current of the second delay unit, respectively.
[0017] Optionally, the first inverters of the first delay unit and the second delay unit have the same flip-flop threshold; the ratio of the first current to the fourth current and the ratio of the second current to the third current are the same as the ratio of the capacitor in the first delay unit to the capacitor in the second delay unit.
[0018] This application also provides a driving circuit, including: a delay circuit as described in any of the above embodiments.
[0019] The delay circuit and driving circuit of this application embodiment generate a first current and a second current through a bias current generating unit. A first current output terminal outputs the first current, and a second current output terminal outputs the second current. Both the first and second currents are proportional to the voltage at the voltage source terminal. A delay unit is included, comprising a control terminal, a selection switch, a capacitor, and a first inverter. The selection switch, controlled by the control terminal, selectively connects the capacitor and the voltage source terminal to charge the capacitor using the first current, or connects the capacitor and the ground terminal to discharge the capacitor using the second current. The capacitor is connected to the first inverter, and the switching threshold voltage of the first inverter is proportional to the voltage at the voltage source terminal.
[0020] Because the capacitor is connected to the first inverter, when the selector switch is controlled to selectively connect the capacitor and the voltage source, the voltage source charges the capacitor with a first current until the capacitor's voltage exceeds the first inverter's switching threshold voltage, at which point the first inverter flips. The time interval from the start of charging to the first inverter flipping is the charging delay duration. When the selector switch is controlled to selectively connect the capacitor and the ground terminal, the capacitor discharges with a second current. When the capacitor's voltage drops from the voltage source to the first inverter's switching threshold voltage, the first inverter flips. The time interval from the start of discharging to the first inverter flipping is the discharging delay duration.
[0021] With the switching threshold voltage remaining constant, a larger initial current results in a shorter time required to charge the capacitor until its voltage reaches the switching threshold voltage; the charging delay is inversely proportional to the initial current. Conversely, with the initial current remaining constant, a larger switching threshold voltage results in a longer time required to charge the capacitor until its voltage reaches the switching threshold voltage; the charging delay is directly proportional to the switching threshold voltage. Furthermore, because both the initial current and the switching threshold voltage are proportional to the voltage at the voltage source, the influence of the voltage at the voltage source on the charging delay can be offset.
[0022] With the threshold voltage remaining constant, a larger second current results in a shorter time for the capacitor voltage to drop from the voltage source to the threshold voltage, thus the discharge delay is inversely proportional to the second current. Conversely, with the second current remaining constant, a larger threshold voltage results in a longer time for the capacitor voltage to drop from the voltage source to the threshold voltage, thus the discharge delay is directly proportional to the threshold voltage. Furthermore, since both the second current and the threshold voltage are proportional to the voltage source, the influence of the voltage source on the discharge delay can be offset. Therefore, both the charging and discharging delays are independent of the voltage source, preventing inaccuracies in the charging and discharging delays caused by voltage source deviations, and improving the accuracy and controllability of the delay circuit. Attached Figure Description
[0023] Figure 1 The diagram shown is a schematic block diagram of one embodiment of the delay circuit of this application;
[0024] Figure 2 The diagram shown is a schematic block diagram of another embodiment of the delay circuit of this application;
[0025] Figure 3 As shown Figure 2 The circuit diagram of the delay circuit;
[0026] Figure 4 The diagram shown is a schematic block diagram of another embodiment of the delay circuit of this application;
[0027] Figure 5 As shown Figure 4 The circuit diagram of the delay circuit.
[0028] Figure label:
[0029] Delay circuit 1, bias current generating unit 10, voltage source terminal 11, ground terminal 12, first current output terminal 13, second current output terminal 14, third current output terminal 131, fourth current output terminal 141, reference current generating module 101, first current mirror 102, second current mirror 103, resistor 15, first transistor 16, second transistor 17, first adjustable resistor 18, second adjustable resistor 19, delay unit 20, control terminal 21, selection switch 22, capacitor 23, first inverter 24, first switching transistor 221, second switching transistor 222, second inverter 30, first delay unit 201, second delay unit 202. Detailed Implementation
[0030] The delay circuit 1 and the driving circuit of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.
[0031] Please refer to Figure 1 , Figure 1 The diagram shown is a schematic block diagram of one embodiment of the delay circuit 1 of this application. Figure 1 As shown, the delay circuit 1 in this embodiment is used to delay the output of the input signal. Specifically, the delay circuit 1 includes a bias current generating unit 10 and a delay unit 20. The bias current generating unit 10 includes a voltage source terminal 11, a ground terminal 12, a first current output terminal 13, and a second current output terminal 14. The bias current generating unit 10 is used to generate a first current I1 and a second current I2. The first current output terminal 13 is used to output the first current I1, and the second current output terminal 14 is used to output the second current I2. Both the first current I1 and the second current I2 are proportional to the voltage of the voltage source terminal 11.
[0032] The delay unit 20 includes a control terminal 21, a selection switch 22, a capacitor 23, and a first inverter 24. The control terminal 21 is connected to the selection switch 22, which is also connected to the capacitor 23, the voltage source terminal 11, and the ground terminal 12. A first current output terminal 13 is connected between the voltage source terminal 11 and the selection switch 22, and a second current output terminal 14 is connected between the selection switch 22 and the ground terminal 12. The selection switch 22, controlled by the control terminal 21, selectively connects the capacitor 23 and the voltage source terminal 11 to charge the capacitor 23 with a first current I1, or connects the capacitor 23 and the ground terminal 12 to discharge the capacitor 23 with a second current I2. The first current I1 is the charging current of the capacitor 23, and the second current I2 is the discharging current of the capacitor 23. The capacitor 23 is connected to the first inverter 24, and the switching threshold voltage of the first inverter 24 is proportional to the voltage of the voltage source terminal 11.
[0033] In this patent application, both the first current I1 and the second current I2 are proportional to the voltage at voltage source terminal 11, and the switching threshold voltage of the first inverter 24 is proportional to the voltage at voltage source terminal 11. Alternatively, the first current I1 and the second current I2 may be precisely proportional to the voltage at voltage source terminal 11, and the switching threshold voltage of the first inverter 24 may also be approximately proportional to the voltage at voltage source terminal 11.
[0034] The delay circuit 1 and driving circuit of this application embodiment generate a first current I1 and a second current I2 by setting a bias current generating unit 10. The first current output terminal 13 is used to output the first current I1, and the second current output terminal 14 is used to output the second current I2. Both the first current I1 and the second current I2 are proportional to the voltage of the voltage source terminal 11. By setting a delay unit 20, the delay unit 20 includes a control terminal 21, a selection switch 22, a capacitor 23, and a first inverter 24. The selection switch 22 is controlled by the control terminal 21 to selectively connect the capacitor 23 and the voltage source terminal 11 to charge the capacitor 23 with the first current I1, or to connect the capacitor 23 and the ground terminal 12 to discharge the capacitor 23 with the second current I2. The first current I1 is the charging current of the capacitor 23, and the second current I2 is the discharging current of the capacitor 23. The capacitor 23 is connected to the first inverter 24, and the flip threshold voltage of the first inverter 24 is proportional to the voltage of the voltage source terminal 11.
[0035] In this embodiment, the control terminal 21 uses a high or low level to control the selection switch 22 to connect capacitor 23 and voltage source terminal 11, or capacitor 23 and ground terminal 12. When the control terminal 21 is at either a high or low level, the selection switch 22 connects capacitor 23 and voltage source terminal 11. When the control terminal 21 is at either a high or low level, the selection switch 22 connects capacitor 23 and ground terminal 12. Thus, by controlling the potential of the control terminal 21, the selection switch 22 can be controlled to connect capacitor 23 and voltage source terminal 11, or capacitor 23 and ground terminal 12, making the control method simple and efficient.
[0036] When charging capacitor 23, the time it takes for the voltage across capacitor 23 to rise from zero to the switching threshold voltage of the first inverter 24 is the charging delay duration of the delay unit 20. When the switching threshold voltage of the first inverter 24 is the same, the larger the first current I1, the smaller the charging delay duration; the charging delay duration is inversely proportional to the first current I1. With the first current I1 constant, the larger the switching threshold voltage of the first inverter 24, the longer it takes to charge capacitor 23 until its voltage reaches the switching threshold voltage; the charging delay duration is directly proportional to the switching threshold voltage. Furthermore, because the first current I1 is proportional to the voltage at voltage source terminal 11, and the switching threshold voltage is proportional to the voltage at voltage source terminal 11, the influence of the voltage at voltage source terminal 11 on the charging delay duration can be offset.
[0037] When discharging capacitor 23, the time it takes for the voltage across capacitor 23 to drop from the voltage at voltage source 11 to the switching threshold voltage of the first inverter 24 is the discharge delay duration of delay unit 20. With the switching threshold voltage constant, the larger the second current I2, the shorter the time required for the voltage across capacitor 23 to drop from the voltage at voltage source 11 to the switching threshold voltage; the discharge delay duration is inversely proportional to the second current I2. With the second current I2 constant, the larger the switching threshold voltage, the longer the time required for the voltage across capacitor 23 to drop from the voltage at voltage source 11 to the switching threshold voltage; the discharge delay duration is directly proportional to the switching threshold voltage. Furthermore, because the first current I1 is proportional to the voltage at voltage source 11, and the switching threshold voltage is also proportional to the voltage at voltage source 11, the influence of the voltage at voltage source 11 on the charging delay duration can be offset.
[0038] To illustrate more specifically how the technical solution of this embodiment can eliminate the influence of the voltage at voltage source terminal 11 on the charging delay time and discharging delay time, an example is given. Assume the voltage at voltage source terminal 11 is VCC, the capacitance of capacitor 23 is C, the first current I1 is proportional to the voltage at voltage source terminal 11, and the magnitude of the first current I1 is aVCC; the second current I2 is proportional to the voltage at voltage source terminal 11, and the magnitude of the second current I2 is bVCC; the switching threshold voltage of the first inverter 24 is proportional to the voltage at voltage source terminal 11, and the switching threshold Vth of the first inverter 24 is kVCC, where a, b, and k are proportionality coefficients, and k is greater than 0 and not greater than 1.
[0039] When capacitor 23 is charged, the time it takes for the voltage across capacitor 23 to rise from zero to the switching threshold voltage Vth of the first inverter 24 is the charging delay time of the delay unit 20. The charging delay time is the ratio of the switching threshold voltage multiplied by the capacitance C of capacitor 23 to the first current I1. Since the switching threshold voltage is kVCC and the first current I1 is aVCC, the charging delay time is kC / a, which cancels the influence of the voltage VCC at the voltage source terminal 11 on the charging delay time.
[0040] When capacitor 23 is discharged, the time it takes for the voltage across capacitor 23 to drop from the voltage at voltage source terminal 11 to the switching threshold voltage of the first inverter 24 is the discharge delay duration of delay unit 20. The discharge delay duration is the ratio of the difference between the voltage at voltage source terminal 11 and the switching threshold voltage of the first inverter 24 multiplied by the capacitance C of capacitor 23 to the second current I2. Since the switching threshold voltage is kVCC, the difference between the voltage at voltage source terminal 11 and the switching threshold voltage of the first inverter 24 is (1-k)VCC, the second current I2 is bVCC, and the discharge delay duration is (1-k)C / b, which cancels out the influence of the voltage VCC at voltage source terminal 11 on the discharge delay duration.
[0041] Thus, both the charging delay and the discharging delay are independent of the voltage at voltage source terminal 11. The delay circuit in this application is insensitive to voltage changes at voltage source terminal 11, whether it's a rise delay or a fall delay. Using the technical solution provided in this embodiment, the charging delay and discharging delay can maintain the same parameter value even when the power supply voltage at voltage source terminal 11 is different. This avoids inaccuracies in the charging and discharging delay caused by voltage deviations at voltage source terminal 11, improving the accuracy and controllability of the delay circuit 1.
[0042] Please refer to Figure 2 , Figure 2 The diagram shown is a schematic block diagram of another embodiment of the delay circuit 1 of this application; Figure 2 The illustrated embodiments and Figure 1The illustrated embodiments are essentially the same. The difference lies in that... Figure 2 In the illustrated embodiment, the bias current generating unit 10 includes a reference current generating module 101, a first current mirror 102, and a second current mirror 103. The reference current generating module 101 generates a reference current that is proportional to the voltage at the voltage source terminal 11. The first current mirror 102 is connected to both the reference current generating module 101 and the first current output terminal 13, and is used to generate a first current I1 based on the mirrored reference current. The second current mirror 103 is connected to both the reference current generating module 101 and the second current output terminal 14, and is used to generate a second current I2 based on the mirrored reference current. Thus, the reference current generating module 101 only needs to generate a reference current proportional to the voltage at the voltage source terminal 11. The first current I1 can be obtained by mirroring the reference current through the first current mirror 102, and the second current I2 can be obtained by mirroring the reference current through the second current mirror 103.
[0043] Understandably, the current mirror can not only replicate the current but also scale it proportionally. Thus, by adjusting the first current mirror 102, the ratio of the first current I1 to the reference current can be adjusted, thereby adjusting the magnitude of the first current I1. Similarly, by adjusting the second current mirror 103, the ratio of the second current I2 to the reference current can be adjusted, thereby adjusting the magnitude of the second current I2. By adjusting the magnitudes of the first current I1 and the second current I2, the set charging delay time and the set discharging delay time can be adjusted. In this way, the first current mirror 102 and the second current mirror 103 generate the first current I1 and the second current I2 respectively based on the reference current, resulting in a simple structure that is easy to implement and highly accurate.
[0044] exist Figure 3 In the illustrated embodiment, switch MP11 and switch MP22 form a first current mirror 102, which can mirror a reference current to generate a first current I1. Switch MP11 and switch MP12 also form a current mirror to mirror a reference current for use by the second current mirror 103. Switch MN21 and switch MN23 form a second current mirror 103, which can mirror the current reflected by the current mirror formed by switch MP11 and switch MP12 to generate a second current I2.
[0045] Please refer to Figure 3 , Figure 3 for Figure 2 The circuit diagram of delay circuit 1. Figure 3In the illustrated embodiment, the reference current generation module 101 includes a resistor 15 and a first transistor 16. The resistor 15 and the first transistor 16 are connected in series between the voltage source terminal 11 and the ground terminal 12. The ratio of the voltage at the voltage source terminal 11 to the PN junction voltage drop of the first transistor 16 is greater than a set ratio. Thus, the magnitude of the reference current is equal to the ratio of the difference between the voltage at the voltage source terminal 11 and the PN junction voltage drop of the first transistor 16 to the resistor 15. By ensuring that the ratio of the voltage at the voltage source terminal 11 to the PN junction voltage drop of the first transistor 16 is greater than a set ratio, the reference current can be made approximately proportional to the voltage of the voltage source. Generally, the voltage at the voltage source terminal 11 of the delay circuit 1 in the driving circuit is typically 15V, and the PN junction voltage drop of the first transistor 16 is typically around 0.7V, with the ratio of the voltage at the voltage source terminal 11 to the PN junction voltage drop of the first transistor 16 being greater than a set ratio.
[0046] exist Figure 3 In the illustrated embodiment, the reference current is the ratio of the voltage VCC at voltage source terminal 11 to the resistance R of resistor 15, and the reference current is proportional to the voltage at voltage source terminal 11. The reference current is mirrored by the first current mirror 102 to become a first current I1, which is also proportional to the voltage at voltage source terminal 11. The first current I1 is aVCC, where a is the ratio of the first current proportionality coefficient to the resistance of resistor 15. The reference current is mirrored by the second current mirror 103 to become a second current I2, which is also proportional to the voltage at voltage source terminal 11. The second current I2 is bVCC, where b is the ratio of the second current proportionality coefficient to the resistance of resistor 15.
[0047] exist Figure 3 In the embodiment shown, resistor 15 is a low-temperature drift resistor, which reduces the impact of temperature changes on the charging and discharging delay times of the delay circuit 1, thereby reducing the influence of temperature changes on the charging and discharging delay times.
[0048] exist Figure 3In the illustrated embodiment, the reference current generation module 101 further includes a second transistor 17, which forms a third current mirror with the first transistor 16. In some embodiments, the aspect ratio of the second transistor 17 is different from that of the first transistor 16. By forming a third current mirror with the second transistor 17 and the first transistor 16, and by making the aspect ratio of the second transistor 17 different from that of the first transistor 16, the third current mirror can scale the current formed between the voltage source terminal 11 and the ground terminal 12 formed by the resistor 15 and the first transistor 16 connected in series, thereby achieving the purpose of adjusting the reference current. Furthermore, since the first current I1 and the second current I2 are obtained by mirroring the reference current with the first current mirror 102 and the second current mirror 103, respectively, when the reference current is adjusted, the first current I1 and the second current I2 are also adjusted, thereby allowing adjustment of the charging delay time and the discharging delay time. Thus, by changing the relationship between the width-to-length ratio of the second transistor 17 and the width-to-length ratio of the first transistor 16, the adjustment factor of the third current mirror on the reference current can be adjusted to obtain the adjusted reference current. Since the first current I1 is obtained by mirroring the adjusted reference current of the first current mirror 102 and the second current I2 is obtained by mirroring the adjusted reference current of the second current mirror 103, the magnitudes of the first current I1 and the second current I2 can be changed to obtain the desired charging delay time and discharging delay time.
[0049] In another embodiment, the aspect ratio of the second transistor 17 is the same as that of the first transistor 16. By forming a third current mirror with the first transistor 16, the second transistor 17, having the same aspect ratio as the first transistor 16, can replicate the reference current formed by the resistor 15 and the first transistor 16 connected in series between the voltage source terminal 11 and the ground terminal 12. This facilitates the mirroring of the reference current by the first current mirror 102 and the second current mirror 103 to form the first current I1 and the second current I2.
[0050] exist Figure 3In the illustrated embodiment, the reference current generating module 101 further includes a first adjustable resistor 18 and a second adjustable resistor 19. The first adjustable resistor 18 is connected between the first transistor 16 and the ground terminal 12, with one end connected to the ground terminal 12 and the other end connected to the emitter of the first transistor 16. The second adjustable resistor 19 is connected between the second transistor 17 and the ground terminal 12, with one end connected to the ground terminal 12 and the other end connected to the emitter of the second transistor 17. Exemplarily, both the first adjustable resistor 18 and the second adjustable resistor 19 include a fuse adjustment element, which includes multiple fuses. By blowing at least one of the multiple fuses, the value of the corresponding first adjustable resistor 18 and second adjustable resistor 19 is adjusted. This facilitates precise adjustment of the values of the first adjustable resistor 18 and the second adjustable resistor 19. Thus, by changing the resistance values of the first adjustable resistor 18 and the second adjustable resistor 19, the magnitude of the reference current can be finely adjusted, thereby adjusting the charging delay time and the discharging delay time, so that the actual generated charging delay time and discharging delay time are closer to the expected charging delay time and discharging delay time, thus improving the accuracy of the delay circuit 1.
[0051] exist Figure 3 In the illustrated embodiment, the selector switch 22 includes a first switch 221 and a second switch 222. The control terminal 21 is connected to both the first and second switches 221. The first switch 221 is connected between the voltage source terminal 11 and the capacitor 23, and the second switch 222 is connected between the capacitor 23 and the ground terminal 12. When the first switch 221 is turned on by the control terminal 21 and the second switch 222 is turned off by the control terminal 21, the first switch 221 connects the capacitor 23 and the voltage source terminal 11. When the second switch 222 is turned on by the control terminal 21 and the first switch 221 is turned off by the control terminal 21, the second switch 222 connects the capacitor 23 and the ground terminal.
[0052] It is understandable that control terminal 21 controls one of the first switch transistor 221 and the second switch transistor 222 to be turned on and the other to be turned off. When the first switch transistor 221 is turned on and the second switch transistor 222 is turned off, capacitor 23 is connected to voltage source terminal 11, and is charged by the first current I1. When the second switch transistor 222 is turned on and the first switch transistor 221 is turned off, capacitor 23 is connected to ground terminal 12, and is discharged by the second current I2. This allows for control of the charging and discharging processes of capacitor 23, generating charging and discharging delay times.
[0053] In this embodiment, the first switch 221 is a p-type MOSFET, and the second switch 222 is an n-type MOSFET. The gates of both switches 221 and 222 are connected to the control terminal 21. The source of the first switch 221 is connected to the voltage source terminal 11, and the drains of both switches 221 and 222 are connected to one end of the capacitor 23. The source of the second switch 222 and the other end of the capacitor 23 are connected to the ground terminal 12. Thus, when the control terminal 21 is low, the first switch 221 is turned on and the second switch 222 is turned off. The first switch 221 connects the capacitor 23 and the voltage source terminal 11, charging the capacitor 23 through a first current I1. When the control terminal 21 is high, the second switch 222 is turned on and the first switch 221 is turned off. The second switch 222 connects the capacitor 23 and the ground terminal, discharging the capacitor 23 through a second current I2.
[0054] In some embodiments, the first inverter 24 is a CMOS inverter. A CMOS inverter generally includes a p-type MOS transistor and an n-type MOS transistor. The gates of both the p-type and n-type MOS transistors are connected to the input terminal of the CMOS inverter, that is, the gates of the p-type and n-type MOS transistors are connected to capacitor 23. The source of the p-type MOS transistor is connected to the voltage source terminal 11, and the source of the n-type MOS transistor is connected to the ground terminal 12. The drains of the p-type and n-type MOS transistors serve as the output terminals of the CMOS inverter.
[0055] The switching threshold voltage of a CMOS inverter is Vth. Vth = (βnVthn + βp(Vcc - Vthp)) / (βn + βp), where βn is the conductivity factor of the n-type MOSFET, βp is the conductivity factor of the p-type MOSFET, Vthn is the threshold voltage of the n-type MOSFET, and Vthp is the absolute value of the threshold voltage of the p-type MOSFET. Under the condition that βnVthn and βpVthp are similar, we can obtain Vth = Vccβp / (βn + βp), where βp / (βn + βp) is a parameter of the CMOS itself. After the CMOS inverter is fabricated, βp / (βn + βp) is a fixed value. Therefore, the switching threshold of the CMOS inverter is proportional to the voltage at voltage source terminal 11.
[0056] In some other embodiments, the first inverter 24 is a Schmitt trigger inverter. In addition to including n-type and p-type MOSFETs, a Schmitt trigger inverter introduces hysteresis, meaning the input signal must cross a certain threshold range to change the output state. Even if the input signal has noise or small fluctuations, as long as the fluctuations do not exceed a certain range, the output of the Schmitt trigger inverter will not be affected, thus avoiding false triggering and preventing CMOS inverter erroneous flipping, thereby improving the stability of charging and discharging delay times.
[0057] Please refer to Figure 4 , Figure 4 The diagram shown is a schematic block diagram of another embodiment of the delay circuit 1 of this application. Figure 5 As shown Figure 4 The circuit diagram of the delay circuit, such as Figure 4 and Figure 5 As shown, the delay circuit 1 includes a second inverter 30 and two delay units 20, which are a first delay unit 201 and a second delay unit 202, respectively. The second inverter 30 is connected between the first delay unit 201 and the second delay unit 202, and can invert the signal output from the first delay unit 201 as the output of the second delay unit 202. Therefore, regardless of whether the control terminal 21 is low or high, the capacitor 23 of one of the first delay unit 201 and the second delay unit 202 is in the charging process, while the capacitor 23 of the other is in the discharging state.
[0058] For example, assuming control terminal 21 is low, capacitor 23 in the first delay unit 201 is charging, generating a first charging delay, while capacitor 23 in the second delay unit 202 is discharging, generating a second discharging delay. When control terminal 21 is low, the overall delay of delay circuit 1 is the sum of the first charging delay and the second discharging delay. Assuming control terminal 21 is high, capacitor 23 in the first delay unit 201 is discharging, generating a first discharging delay, while capacitor 23 in the second delay unit 202 is charging, generating a second charging delay. When control terminal 21 is high, the overall delay of delay circuit 1 is the sum of the first discharging delay and the second charging delay.
[0059] Furthermore, the first current output terminal 13 and the second current output terminal 14 are connected to the first delay unit 201, with the first current I1 and the second current I2 being the charging current and discharging current of the first delay unit 201, respectively; the third current output terminal 131 and the fourth current output terminal 141 are connected to the second delay unit 202, with the third current I3 and the fourth current I4 being the charging current and discharging current of the second delay unit 202, respectively. Thus, regardless of whether the control terminal 21 is at a high level or a low level, its overall delay duration includes a charging delay and a discharging delay, which can at least partially offset the influence of the manufacturing process of the first inverter 24 on the switching threshold voltage of the first inverter 24, thereby mitigating or even completely offsetting the influence of the manufacturing process of the first inverter 24 on the delay duration of the delay circuit 1.
[0060] In some embodiments, the flip threshold Vth of the first inverter 24 of the first delay unit 201 and the second delay unit 202 is the same; the ratio of the first current I1 to the fourth current I4 and the ratio of the second current I2 to the third current I3 are the same as the ratio of the capacitor 23 in the first delay unit 201 to the capacitor 23 in the second delay unit 202.
[0061] To more specifically illustrate how the technical solution of this embodiment can offset the influence of the manufacturing process of the first inverter 24 on the delay duration of the delay circuit 1, an example is given. Assume the voltage at voltage source terminal 11 is VCC, the first current I1 is proportional to the voltage at voltage source terminal 11, and its magnitude is aVCC; the second current I2 is proportional to the voltage at voltage source terminal 11, and its magnitude is bVCC; the switching threshold of the first inverter 24 is proportional to the voltage at power supply terminal 11; the switching threshold Vth of the first inverter 24 in the first delay unit 201 and the second delay unit 202 is the same; the first inverters of the first delay unit 201 and the second delay unit 202... The flip threshold Vth of phase 24 is kVCC; the capacitor 23 in the first delay unit 201 has a value of C1, and the capacitor 23 in the second delay unit 202 has a value of C2; the third current I3 is proportional to the voltage of the voltage source terminal 11, and the value of the third current I3 is cVCC, where c is the ratio of the third current proportionality coefficient to the resistance value of resistor 15; the fourth current I4 is proportional to the voltage of the voltage source terminal 11, and the value of the fourth current I4 is dVCC, where d is the ratio of the fourth current proportionality coefficient to the resistance value of resistor 15.
[0062] When capacitor 23 in the first delay unit 201 is charging and capacitor 23 in the second delay unit 202 is discharging, the first charging delay generated by the first delay unit 201 is kC1 / a, and the second discharging delay generated by the second delay unit 202 is (1-k)C2 / d. The overall delay of the delay circuit 1 is kC1 / a + (1-k)C2 / d. When the ratio of the first current I1 to the fourth current I4 is the same as the ratio of capacitor 23 in the first delay unit 201 to capacitor 23 in the second delay unit 202, the parameter k can be canceled out. k is the proportionality coefficient between the switching threshold voltage of the first inverter 24 and the power supply voltage, and this coefficient is related to the manufacturing process of the first inverter 24. Therefore, by adopting the technical solution provided in this embodiment, the delay duration of the delay circuit 1 can maintain the same parameter value when the process parameters fluctuate.
[0063] If a product includes multiple circuits, and all of these different circuits use the delay circuit 1 provided in the embodiments of this application, the delay duration parameters between the multiple different circuits can maintain the same value, thus maintaining the consistency of time parameters in different circuits.
[0064] When capacitor 23 in the first delay unit 201 is discharging and capacitor 23 in the second delay unit 202 is charging, the first discharge delay generated by the first delay unit 201 is (1-k)C1 / b, the second charging delay generated by the second delay unit 202 is kC2 / c, and the overall delay of the delay circuit 1 is (1-k)C1 / b + kC2 / c. When the ratio of the second current I2 to the third current I3 is the same as the ratio of capacitor 23 in the first delay unit 201 to capacitor 23 in the second delay unit 202, the parameter k can be canceled out.
[0065] It is understandable that the flip threshold Vth of the first inverter 24 of the first delay unit 201 and the second delay unit 202 is the same. This can mean that the flip threshold Vth of the first inverter 24 of the first delay unit 201 and the second delay unit 202 is exactly the same, or it can mean that the difference between the flip threshold Vth of the first inverter 24 of the first delay unit 201 and the second delay unit 202 is less than a preset difference limit.
[0066] The ratios of the first current I1 and the fourth current I4, and the ratios of the second current I2 and the third current I3, are all the same as the ratio of the capacitor 23 in the first delay unit 201 to the capacitor 23 in the second delay unit 202. This can mean that the ratios of the first current I1 and the fourth current I4, and the ratios of the second current I2 and the third current I3, are numerically identical to the ratios of the capacitors 23 in the first delay unit 201 and the second delay unit 202. Alternatively, it can mean that the difference between the ratio of the first current I1 and the fourth current I4 and the ratio of the capacitors 23 in the first delay unit 201 and the second delay unit 202 is within a preset range, and the difference between the ratio of the second current I2 and the third current I3 and the ratio of the capacitors 23 in the first delay unit 201 and the second delay unit 202 is within a preset range.
[0067] In other embodiments, the first inverter 24 of the first delay unit 201 and the second delay unit 202 has the same flip threshold Vth; the first current I1 and the fourth current I4 are the same; the second current I2 and the third current I3 are the same; and the capacitor 23 in the first delay unit 201 is the same as the capacitor 23 in the second delay unit 202. This also cancels out the parameter k, avoiding the influence of the manufacturing process of the first inverter 24 on the delay duration.
[0068] By adopting the technical solution provided in this embodiment, the overall delay time generated at the control terminal 21, whether at a high level or a low level, is independent of the voltage at the voltage source terminal 11 and the manufacturing process of the first inverter 24, thereby improving the accuracy of the delay time.
[0069] This application also provides a driving circuit, including a delay circuit 1 as described in any of the above embodiments. The limitations and descriptions of the delay circuit 1 described above also apply to the driving circuit, and will not be repeated here.
[0070] It should be understood that this application is not limited to the content already described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A delay circuit, characterized in that, include: A bias current generating unit includes a voltage source terminal, a ground terminal, a first current output terminal, and a second current output terminal. The first current output terminal is used to output a first current, and the second current output terminal is used to output a second current. Both the first current and the second current are proportional to the voltage of the voltage source terminal. The delay unit includes a control terminal, a selection switch, a capacitor, and a first inverter. The control terminal is connected to the selection switch, which is also connected to the capacitor, the voltage source terminal, and the ground terminal. A first current output terminal is connected between the voltage source terminal and the selection switch, and a second current output terminal is connected between the selection switch and the ground terminal. The selection switch, controlled by the control terminal, selectively connects the capacitor and the voltage source terminal to charge the capacitor with the first current, or connects the capacitor and the ground terminal to discharge the capacitor with the second current. The capacitor is connected to the first inverter, and the switching threshold voltage of the first inverter is proportional to the voltage of the voltage source terminal.
2. The delay circuit according to claim 1, characterized in that, The bias current generating unit includes a reference current generating module, a first current mirror, and a second current mirror. The reference current generating module generates a reference current that is proportional to the voltage at the voltage source terminal. The first current mirror is connected to the reference current generating module and the first current output terminal, respectively, and is used to form the first current based on the mirror image of the reference current. The second current mirror is connected to the reference current generating module and the second current output terminal, respectively, and is used to form the second current based on the mirror image of the reference current.
3. The delay circuit according to claim 2, characterized in that, The reference current generation module includes a resistor and a first transistor. The resistor and the first transistor are connected in series between the voltage source terminal and the ground terminal. The ratio of the voltage at the voltage source terminal to the PN junction voltage drop of the first transistor is greater than a set ratio.
4. The delay circuit according to claim 3, characterized in that, The reference current generation module further includes a second transistor, which forms a third current mirror with the first transistor.
5. The delay circuit according to claim 4, characterized in that, The reference current generating module further includes a first adjustable resistor and a second adjustable resistor, wherein the first adjustable resistor is connected between the first transistor and the ground terminal, and the second adjustable resistor is connected between the second transistor and the ground terminal.
6. The delay circuit according to claim 5, characterized in that, Both the first adjustable resistor and the second adjustable resistor include a fuse adjustment element, which includes multiple fuses. By blowing at least one of the multiple fuses, the magnitude of the corresponding first adjustable resistor and the second adjustable resistor is adjusted.
7. The delay circuit according to claim 1, characterized in that, The selection switch includes a first switch and a second switch. The control terminal is connected to both the first switch and the second switch. The first switch is connected between the voltage source and the capacitor, and the second switch is connected between the capacitor and the ground terminal. When the first switch is controlled to be turned on by the control terminal and the second switch is controlled to be turned off by the control terminal, the first switch connects the capacitor and the voltage source. When the second switch is controlled to be turned on by the control terminal and the first switch is controlled to be turned off by the control terminal, the second switch connects the capacitor and the ground terminal.
8. The delay circuit according to claim 7, characterized in that, The first switching transistor is a p-type MOS transistor, and the second switching transistor is an n-type MOS transistor. The gates of both the first and second switching transistors are connected to the control terminal. The source of the first switching transistor is connected to the voltage source terminal. The drains of the first and second switching transistors are connected to each other and to one end of the capacitor. The source of the second switching transistor and the other end of the capacitor are connected to the ground terminal.
9. The delay circuit according to claim 1, characterized in that, The first inverter is a Schmitt inverter.
10. The delay circuit according to claim 1, characterized in that, The delay circuit further includes a second inverter and two delay units, the two delay units being a first delay unit and a second delay unit, and the second inverter being connected between the first delay unit and the second delay unit; The bias current generating unit further includes a third current output terminal and a fourth current output terminal. The bias current generating unit is used to generate a third current and a fourth current, both of which are proportional to the voltage of the voltage source terminal. The first current output terminal and the second current output terminal are connected to the first delay unit, and the first current and the second current are the charging current and the discharging current of the first delay unit, respectively; the third current output terminal and the fourth current output terminal are connected to the second delay unit, and the third current and the fourth current are the charging current and the discharging current of the second delay unit, respectively.
11. The delay circuit according to claim 10, characterized in that, The first inverters of the first delay unit and the second delay unit have the same flip-flop threshold; the ratio of the first current to the fourth current and the ratio of the second current to the third current are the same as the ratio of the capacitor in the first delay unit to the capacitor in the second delay unit.
12. A driving circuit comprising the delay circuit as described in any one of claims 1-11.