Drive circuit
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU SHIDAI SUXIN TECH CO LTD
- Filing Date
- 2025-08-14
- Publication Date
- 2026-07-21
Smart Images
Figure CN224538177U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, and more specifically, to a driving circuit. Background Technology
[0002] In existing technologies, the testing of RF front-end systems, especially for RF front-end devices operating with single-tone sine waves, such as LNAs, PAs, TRs, and SIP modules, often employs signal sources, such as vector network analyzers (VGAs). VGAs support RF parameter testing under pulse conditions, such as S-parameters, power, efficiency, harmonics, and intermodulation, which is crucial for evaluating device performance in pulsed operating modes. However, in practical applications, the built-in TTL pulse signal output channel of VGAs presents the following technical problems when driving devices under test (DUTs) with high current requirements: the built-in TTL output signal of VGAs has weak load-carrying capacity, with a maximum drive current of only about 30mA. This is insufficient for testing DUTs requiring high drive current, especially for the transmit path (TX path) in modules operating under saturation conditions; switching pulse source output channels is cumbersome, requiring changes to wiring paths and manual toggling of switches. Utility Model Content
[0003] The main objective of this application is to provide a driving circuit that at least solves the problems of existing driving circuits requiring manual switching of signal output channels and having poor load-carrying capacity.
[0004] To achieve the above objectives, according to one aspect of this application, a driving circuit is provided, comprising: a switching module having multiple signal channels, the input terminals of the signal channels being connected to a signal source; a control module having multiple input terminals and multiple output terminals, the multiple input terminals of the control module being connected to the signal source, and the multiple output terminals of the control module being connected one-to-one with the input terminals of the multiple signal channels, the control module being used to control one of the signal channels in the switching module corresponding to the input terminal of the control module to be turned on when the input terminal of the control module detects that the signal source outputs a signal; and a driver module, the input terminal of the driver module being connected to the output terminal of the signal channel, the output terminal of the driver module being used to output the signal, the driver module being used to improve the load capacity of the driving circuit, and the signal being used to drive the device under test to operate.
[0005] Optionally, the driver module includes a dual-channel driver chip, a P-type transistor, and an N-type transistor. The two output terminals of the dual-channel driver chip are electrically connected to the gates of the P-type transistor and the N-type transistor, respectively. The drain of the P-type transistor is electrically connected to the drain of the N-type transistor. The source of the N-type transistor is grounded. The source of the P-type transistor is connected to a power supply terminal. The drains of the P-type transistor and the N-type transistor are the output terminals of the driver module.
[0006] Optionally, the driver module further includes a Schmitt trigger, the input of which is connected to the output of the switching module, and the output of which is electrically connected to the input of the dual-channel driver chip.
[0007] Optionally, the driver module further includes: a first resistor unit and a second resistor unit, wherein a first end of the first resistor unit is electrically connected to the output terminal of the dual-channel driver chip, a second end of the first resistor unit is electrically connected to the gate of the P-type transistor, a first end of the second resistor unit is electrically connected to the output terminal of the dual-channel driver chip, and a second end of the second resistor unit is electrically connected to the gate of the N-type transistor.
[0008] Optionally, the driver module further includes: a first unidirectional conduction unit and a second unidirectional conduction unit, wherein the first unidirectional conduction unit is connected in parallel with the first resistor unit, and the second unidirectional conduction unit is connected in parallel with the second resistor unit.
[0009] Optionally, the driver module further includes a filter unit, which is electrically connected to the drain of the P-type transistor and the drain of the N-type transistor.
[0010] Optionally, the filtering unit includes a capacitor unit and a third resistor unit, wherein the first terminal of the capacitor unit is electrically connected to the drain of the P-type transistor and the N-type transistor, and the third terminal of the capacitor unit is electrically connected to the third resistor unit.
[0011] Optionally, the driver module further includes a pull-up unit and a pull-down unit, wherein the pull-up unit is electrically connected to the output terminal of the dual-channel driver chip and the source of the P-type transistor, respectively, and the pull-down unit is electrically connected to the output terminal of the dual-channel driver chip and the source of the N-type transistor, respectively.
[0012] Optionally, the switching module is a switch module, the switch module is a multi-channel switch module, and the multi-channel switch module includes multiple single-pole single-throw switch units.
[0013] Optionally, the driving circuit further includes a power supply module, which is electrically connected to the signal source, the control module, and the driver module.
[0014] Applying the technical solution of this application, the driving circuit includes a switching module, a control module, and a driver module for connection to a signal source. When the control module detects a signal output from the signal source at its input terminal, it automatically controls one signal channel in the switching module corresponding to the input terminal of the control module to be activated. When facing at least one signal output from the signal source, it can automatically switch the output signal channel without manual switching. The input terminal of the driver module is connected to the output terminal of the switching module. The driver module enhances the load-carrying capacity of the driving circuit, enabling the signal output from the driver module to successfully drive the device under test, thus solving the problems of manual signal channel switching and poor load-carrying capacity in existing technologies. Attached Figure Description
[0015] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:
[0016] Figure 1 A schematic diagram of a driving circuit provided in an embodiment of this application is shown;
[0017] Figure 2 A schematic diagram of the structure of a driver module according to an embodiment of this application is shown;
[0018] Figure 3 A schematic diagram of the structure of a switching module provided according to an embodiment of this application is shown.
[0019] The above figures include the following reference numerals:
[0020] 10. Driver module; 11. Dual-channel driver chip; 12. P-type transistor; 13. N-type transistor; 14. Schmitt trigger; 15. Filtering unit; 20. Signal source; 30. Switching module; 40. Control module; 50. Connection port; 60. Power supply module. Detailed Implementation
[0021] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0024] As described in the background section, the TTL output signal of the vector network detector (VND) in the prior art has a weak load-carrying capacity, with a maximum drive current of only about 30mA. This is insufficient for DUT testing that requires a large drive current, especially for GaNPA, GaAs PA, and the TX path in SIP modules that operate under saturation conditions. To solve the problem of poor load-carrying capacity of the drive circuit in the prior art, the embodiments of this application provide a drive circuit.
[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention.
[0026] According to one embodiment of this application, a driving circuit is provided, such as... Figure 1As shown, the device includes a driver module 10, a switching module 30 for connection to a signal source 20, and a control module 40. The switching module 30 has multiple signal channels, the input terminals of which are connected to the signal source 20. The control module 40 has multiple input terminals and multiple output terminals. The multiple input terminals of the control module 40 are connected to the signal source 20, and the multiple output terminals of the control module 40 are connected one-to-one with the input terminals of the multiple signal channels. When the control module 40 detects a signal output from the signal source 20 at its input terminal, it controls one signal channel in the switching module 30 corresponding to the input terminal of the control module 40 to be turned on. The driver module 10 has its input terminal connected to the output terminal of the signal channel, and its output terminal is used to output a signal. The driver module 10 is used to improve the load capacity of the drive circuit, and the signal is used to drive the device under test.
[0027] When the control module detects a signal from the signal source at its input, it automatically closes a switching unit corresponding to that input, automatically switching the signal output path. If multiple inputs simultaneously detect a signal, the control module prioritizes the highest-priority signal channel, deactivating it while deactivating the others. This eliminates the need for manual switching, as the drive circuit automatically switches the switching module's signal channels. The driver module's input is connected to the switching module's output. The driver module enhances the drive circuit's load capacity, ensuring the output signal successfully drives the device under test, thus resolving the issues of manual signal output channel switching and poor load capacity in existing technologies.
[0028] In the above embodiments, when only one output terminal of the signal source 20 outputs a signal to the input terminal of the control module 40, the output terminal of the control module 40 corresponding to the input terminal of the signal source 20 outputs a control signal to the switching module 30. This control signal turns on one signal channel in the switching module 30 corresponding to the input terminal of the signal source 20, and controls the other signal channels to be deactivated. The signal is then output from the activated signal channel to the driver module 10. When the signal source 20 simultaneously outputs signals to multiple input terminals of the control module 40, according to the pre-set priority in the control module 40, the highest-priority signal channel among the signal channels corresponding to the output terminals of the signal source 20 is turned on. For example, if the signal source 20 has four output terminals, namely Pulse1, Pulse2, Pulse3, and Pulse4, and the pre-stored priority in the control module 40 is from highest to lowest as follows: the signal channel corresponding to Pulse1, the signal channel corresponding to Pulse2, the signal channel corresponding to Pulse3, and Pulse4. When Pulse1 and Pulse2 simultaneously output signals, the control module 40 will control the signal channel corresponding to Pulse1 to be active, and deactivate the other signal channels. Similarly, when Pulse2 and Pulse4 simultaneously output signals, the control module 40 will control the signal channel corresponding to Pulse2 to be active, and deactivate the other signal channels. Furthermore, when Pulse1, Pulse2, and Pulse4 simultaneously output signals, the control module 40 will control the signal channel corresponding to Pulse1 to be active, and deactivate the other signal channels. By setting the priority of the signal channels in the control module 40, automatic switching can be performed when signal channel switching is required. The control module 40 can be implemented using a driver chip or driver circuit, which can also reduce the size of the circuit.
[0029] In the above embodiments, the signal source can be a vector network analyzer. The vector network analyzer outputs pulse signals to trigger the pulse operating mode of the device under test. The male connector for connecting the output of the vector network analyzer to other devices can be a DR15 interface. The vector network analyzer includes single-pulse source channel type and multi-pulse source channel type. The single-pulse source channel type has one pulse source and outputs pulse signals through only one channel. During testing, pulse measurement can be selected simply by configuring the vector network analyzer software. The multi-channel type includes multiple pulse sources, allowing simultaneous control of multiple pulse sources to output pulse signals or independent control of a single pulse source to output pulse signals. The driving circuit of this application can automatically switch between outputs when multiple outputs of the vector network analyzer simultaneously output pulse signals, improving output efficiency.
[0030] In the above embodiments, the switching module further includes multiple indicator lights. One indicator light may be used to indicate that all signal channels are not closed, while the remaining multiple indicator lights are electrically connected to each signal channel. Alternatively, there may be multiple indicator lights electrically connected to each signal channel. When a signal channel is conducting and current flows through it, the indicator light electrically connected to that signal channel will light up or change color, allowing observation of which output terminal is sending the signal and which signal channel is conducting. To keep the circuit compact, 0402 surface-mount LEDs can be used as status indicators. When there is no signal output, red LED1 remains constantly lit. When the first output terminal (Pulse1) of the signal source outputs a signal, LED2 in the corresponding signal channel flashes green for 1 second; when the second output terminal (Pulse2) outputs a signal, LED3 in the corresponding signal channel flashes green for 1 second; when the third output terminal (Pulse3) outputs a signal, LED4 in the corresponding signal channel flashes green for 1 second; and when the fourth output terminal (Pulse4) outputs a signal, LED5 in the corresponding signal channel flashes green for 1 second. This provides a clear indication of whether there is a signal output, improving ease of use and reducing troubleshooting time when the signal source has no output signal. The type of indicator light can be selected according to the actual situation and is not limited to the above types.
[0031] In the above embodiments, such as Figure 1 As shown, the drive circuit also includes a connection port 50, which is used to output the signal from the driver module 10 to the device under test (DUT) requiring timing synchronization. The output of the driver module 10 is connected to the DUT via the connection port 50. The connection port 50 can be a BNC connector, a microwave high-frequency connector (SMA interface), or a server information block (SMB) interface. The DUT can be a module operating under saturation conditions, such as a GaN PA (gallium nitride power amplifier), a GaAs PA (gallium arsenide power amplifier), or a SIP module (system-in-package). Based on the dual-path chip and complementary output structure of the drive circuit, the output signal has a load current of approximately 300mA, and the high-level output waveform has a voltage drop of only 0.1V, which meets the driving conditions for the module operating under saturation conditions.
[0032] In some alternative implementations, such as Figure 2As shown, the driver module 10 includes a dual-channel driver chip 11, a P-type transistor 12, and an N-type transistor 13. The two output terminals of the dual-channel driver chip 11 are electrically connected to the gates of the P-type transistor 12 and the N-type transistor 13, respectively. The drain of the P-type transistor 12 is electrically connected to the drain of the N-type transistor 13. The source of the N-type transistor 13 is grounded, and the source of the P-type transistor 12 is connected to the power supply terminal. The drains of the P-type transistor 12 and the N-type transistor 13 are the output terminals of the driver module 10. The P-type transistor 12 and the N-type transistor 13 form a complementary output circuit, which can effectively amplify and transmit signals. Furthermore, the dual-channel driver chip 11 can effectively amplify the transmitted signal. The two output terminals of the dual-channel driver chip 11 are electrically connected to the gates of the P-type transistor 12 and N-type transistor 13, respectively. This allows the dual-channel driver chip 11 to simultaneously control the switching states of the two transistors. When the signal received by the chip is low, the chip outputs a high level, turning on the N-type transistor 13 and turning off the P-type transistor 12. The low resistance of the N-type transistor 13 in its on-state allows it to carry a large current, improving its current driving capability. When the signal received by the chip is high, the chip outputs a low level, turning off the N-type transistor 13 and turning on the P-type transistor 12. The P-type transistor 12, with its low resistance when on, can carry a larger current, and a high level at its source further enhances its current driving capability. Through the complementary output circuit and the amplification effect of the dual-channel driver chip, the driving current is significantly increased, improving the load capacity and enabling the signal output from the driver module to successfully drive the device under test.
[0033] In the above optional embodiments, the P-type transistor can be a PMOS and the N-type transistor can be an NMOS, but when used as a switch, it must meet the requirements of a sufficiently fast switching time (not greater than 20ns) and a sufficiently small on-resistance (less than 0.3Ω). The above dual-path chip can be a dual-path MOSFET driver chip or other chip with a delay time of less than 30ns.
[0034] In this application, P-type and N-type transistors form a complementary output circuit. This improves upon the situation where, when using two PMOS transistors, it is difficult to directly connect the output to ground because they are on at high levels and off at low levels. This limits the low-level states that the circuit can generate, and may not achieve a true 0V output, resulting in poor driving performance. Furthermore, it improves upon the situation where, when using two NMOS transistors, although a direct grounding of the low level is possible, the high-level state is determined by the voltage drop between the source and drain when the transistor is on. This may not provide an output voltage that is exactly equal to the power supply voltage, thus affecting the amplitude and quality of the signal.
[0035] To improve the anti-interference capability of the aforementioned driver module, in some optional implementations, such as Figure 2As shown, the driver module 10 also includes a Schmitt trigger 14. The input of the Schmitt trigger 14 is connected to the output of the switching module, and the output of the Schmitt trigger 14 is electrically connected to the input of the dual-channel driver chip 11. Based on the design of the Schmitt trigger 14, the dual-channel driver chip 11, and the complementary output circuit, the driver module 10 has a two-stage circuit structure. The first stage, using the Schmitt trigger 14, is mainly for anti-interference. The second stage, using the dual-channel driver chip 11 and the complementary output circuit, is used to increase the signal output load capacity and maintain the output voltage at +3.3V. The time delay of the entire driver module 10 is within 40ns.
[0036] Specifically, when the signal source is a pulse signal output from a vector network analyzer, the output state does not immediately change when the input pulse signal drops from a high level (above the rising threshold voltage of the Schmitt trigger 14). The output state only returns to a low level when the input pulse voltage drops below the falling threshold voltage of the Schmitt trigger 14. This characteristic forms a "hysteresis" voltage range, meaning that the output state does not change when the input fluctuates between the rising and falling threshold voltages. Furthermore, the pulse signal output from the vector network analyzer is a PWM signal with arbitrary duty cycle and period. The low-latency (<5ns) high-speed Schmitt trigger 14 can improve the PWM waveform, thereby enhancing the circuit's anti-interference capability.
[0037] In some alternative implementations, such as Figure 2 As shown, the driver module 10 further includes a pull-up unit R1 and a pull-down unit R2. The pull-up unit R1 is electrically connected to the output terminal of the dual-channel driver chip 11 and the source of the P-type transistor 12, respectively. The pull-down unit R2 is electrically connected to the output terminal of the dual-channel driver chip 11 and the source of the N-type transistor 13, respectively. The pull-up unit R1 can provide a stable high voltage level to the P-type transistor 12 when the dual-channel driver chip 11 outputs a high-level signal, thus keeping the P-type transistor 12 in the off state. The pull-down unit R2 can provide a stable low voltage level to the N-type transistor 13 when the dual-channel driver chip 11 outputs a low-level signal, thus keeping the N-type transistor 13 in the off state. This prevents the P-type transistor 12 and the N-type transistor 13 from being accidentally turned on due to uncertain output levels at the moment of power-on. Furthermore, there may be parasitic capacitance between the gate and source of P-type transistor 12 and N-type transistor 13. When the power is off, the pull-up unit R1 and pull-down unit R2 can provide a discharge path for the parasitic capacitance, which can reduce the risk of the parasitic capacitance continuously charging the transistor after the power is off, keeping the transistor in a conducting state, and causing breakdown due to the uncertainty of the voltage level when the power is on again.
[0038] In the above embodiments, the pull-up unit can also be formed by multiple resistors connected in series or multiple resistors connected in parallel. If the transistor's drive voltage is high, multiple resistors connected in series can be used to form the pull-up unit to increase the drive voltage provided by the pull-up unit. If the transistor needs to shunt current, multiple resistors connected in parallel can be used to form the pull-up unit to shunt the current.
[0039] When a transistor rapidly switches from the off state to the on state, or from the on state to the off state, additional oscillations or ringing may occur on the signal line due to the effects of parasitic inductance and capacitance. This can lead to signal distortion and degraded circuit performance. To improve high-frequency ringing and other phenomena in the output signal from the dual-channel driver chip, in some optional implementations, such as... Figure 2 As shown, the driver module 10 further includes a first resistor unit R3 and a second resistor unit R4. The first end of the first resistor unit R3 is electrically connected to the output terminal of the dual-channel driver chip 11, and the second end of the first resistor unit R3 is electrically connected to the gate of the P-type transistor 12. The first end of the second resistor unit R4 is electrically connected to the output terminal of the dual-channel driver chip 11, and the second end of the second resistor unit R4 is electrically connected to the gate of the N-type transistor 13. The first resistor unit R3 and the second resistor unit R4 can appropriately limit the current flowing into the transistor gate, slow down the switching speed of the transistor, reduce the instantaneous current surge, and reduce the ringing amplitude generated during rapid transistor switching, thereby improving signal quality. During high-speed switching, there may be parasitic inductance and capacitance energy in the circuit. This energy will be released at the edge of the signal, causing ringing. The first resistor unit R3 and the second resistor unit R4 can also absorb these parasitic inductance and capacitance to reduce the possibility of ringing or reduce the ringing amplitude.
[0040] In some alternative implementations, such as Figure 2As shown, the driver module 10 further includes: a first unidirectional conduction unit D1 and a second unidirectional conduction unit D2. The first unidirectional conduction unit D1 is connected in parallel with the first resistor unit R3, and the second unidirectional conduction unit D2 is connected in parallel with the second resistor unit R4. Each unidirectional conduction unit can be composed of at least one high-speed switching diode. High-speed switching diodes have extremely low switching times, enabling them to quickly cut off the residual current at the transistor gate, reducing the transistor's turn-off time and thus ensuring rapid turn-off. Rapid turn-off reduces the transition time between high and low levels, improving signal clarity and accuracy, and reducing ringing effects. Furthermore, the first unidirectional conduction unit D1 and the second unidirectional conduction unit D2 are electrically connected in parallel with the first resistor unit R3 and the second resistor unit R4, respectively. The first unidirectional conduction unit D1 and the second unidirectional conduction unit D2 can also quickly guide residual charge on the transistor gate to ground or power supply, reducing the pressure on the first resistor unit R3 and the second resistor unit R4 to absorb residual charge. This allows the transistor to return to the cut-off state more quickly when turned off, reducing ringing during the turn-off process.
[0041] To filter high-frequency overshoot signals or ringing, in some alternative implementations, such as Figure 2 As shown, the driver module 10 further includes a filter unit 15, which is electrically connected to the drain of the P-type transistor and the drain of the N-type transistor. The filter unit 15 can effectively absorb high-frequency noise in the signal, rapidly attenuate the oscillation amplitude, and reduce high-frequency overshoot and ringing amplitude.
[0042] In some alternative implementations, such as Figure 2 As shown, the filter unit 15 includes a capacitor unit C1 and a third resistor unit R5. The first terminal of the capacitor unit C1 is electrically connected to the drain of the P-type transistor and the N-type transistor, and the third terminal of the capacitor unit C1 is electrically connected to the third resistor unit R5. The capacitor unit C1 can be selected as a high-frequency filter capacitor, forming an RC filter unit with the third resistor unit R5. The capacitor unit C1 can achieve voltage smoothing during charging and discharging, effectively absorbing high-frequency noise, while the third resistor unit R5 can absorb excess energy to suppress circuit oscillation and reduce the oscillation amplitude.
[0043] In some alternative implementations, such as Figure 3 As shown, the switching module 30 is a switch module, which is a multi-channel switch module, comprising multiple single-pole single-throw switch units. It can be configured as follows: Figure 3 (a) shows a single-pole single-throw multi-channel switch module, where multiple switch units are used to connect one-to-one with multiple output terminals of a signal source. The multi-channel switch module can also... Figure 3(b) Single-pole multi-throw multi-channel switch module. Switching module 30 is a multi-channel switch module that can be matched with a signal source with multiple channels. The signal source can be a vector network analyzer. The timing synchronization measurement can be achieved by triggering the DUT (Device Under Test) with the pulse signal output by the pulse source inside the vector network analyzer.
[0044] In some alternative implementations, such as Figure 1 As shown, the drive circuit also includes a power supply module 60, which is electrically connected to the signal source 20, the control module 40, and the driver module 10. The power supply module 60 can be a low dropout linear regulator (LDO) chip with a maximum output current of 1A. The Type-C interface of the power supply module 60 can be connected to the USB-A port on the rear panel of the signal source 20 via a USB adapter cable to power the driver module 10 and the control module 40. The +5V output from the Type-C interface powers the dual-channel driver chip of the driver module 10, and the +5V is converted to +3.3V and electrically connected to the source of the P-type transistor.
[0045] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0046] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0047] As can be seen from the above description, the embodiments of this application achieve the following technical effects:
[0048] 1) When the control module of this application detects a signal output from the signal source at its input terminal, it automatically controls the closing of a switching unit corresponding to the aforementioned input terminal. This allows for automatic switching of the signal output path. When multiple input terminals of the control module simultaneously detect a signal output from the signal source, it controls the highest priority signal channel to conduct according to the priority of the signal channels pre-stored in the control module, while the signal channels corresponding to other output terminals remain closed. This eliminates the need for manual switching when signal channel switching is required, as the drive circuit can automatically switch and conduct the signal channels of the switching module. The input terminal of the driver module is connected to the output terminal of the switching module. The driver module can enhance the load capacity of the drive circuit, enabling the signal output from the driver module's output terminal to smoothly drive the device under test, thus solving the problems of manual switching of signal output channels and poor load capacity in existing technologies.
[0049] 2) The switching module of this application is equipped with an indicator light. When the signal channel is conducting and current flows through it, the indicator light that is electrically connected to the signal channel will be lit or change color, so that it can be observed which signal channel is conducting and whether there is a signal output at the signal source more intuitively. This improves the ease of use and reduces the troubleshooting time when there is no output signal from the signal source.
[0050] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A drive circuit characterized by comprising: include: The switching module has multiple signal channels, the input terminals of which are used to connect to a signal source; The control module has multiple input terminals and multiple output terminals. The multiple input terminals of the control module are connected to a signal source, and the multiple output terminals of the control module are connected one-to-one with the input terminals of the multiple signal channels. The control module is used to control one of the signal channels in the switching module corresponding to the input terminal of the control module to be turned on when the input terminal of the control module detects that the signal source outputs a signal. A driver module, the input terminal of which is connected to the output terminal of the signal channel, the output terminal of which is used to output the signal, the driver module is used to improve the load capacity of the drive circuit, and the signal is used to drive the device under test to operate.
2. The drive circuit according to claim 1, characterized by The driver module includes a dual-channel driver chip, a P-type transistor, and an N-type transistor. The two output terminals of the dual-channel driver chip are electrically connected to the gates of the P-type transistor and the N-type transistor, respectively. The drain of the P-type transistor is electrically connected to the drain of the N-type transistor. The source of the N-type transistor is grounded. The source of the P-type transistor is connected to the power supply terminal. The drains of the P-type transistor and the N-type transistor are the output terminals of the driver module.
3. The drive circuit according to claim 2, characterized in that, The driver module also includes: A Schmitt trigger is provided, wherein the input terminal of the Schmitt trigger is connected to the output terminal of the switching module, and the output terminal of the Schmitt trigger is electrically connected to the input terminal of the dual-channel driver chip.
4. The drive circuit according to claim 2, characterized by The driver module also includes: A first resistor unit and a second resistor unit, wherein the first end of the first resistor unit is electrically connected to the output terminal of the dual-channel driver chip, the second end of the first resistor unit is electrically connected to the gate of the P-type transistor, the first end of the second resistor unit is electrically connected to the output terminal of the dual-channel driver chip, and the second end of the second resistor unit is electrically connected to the gate of the N-type transistor.
5. The drive circuit according to claim 4, characterized in that, The driver module also includes: A first unidirectional conducting unit and a second unidirectional conducting unit, wherein the first unidirectional conducting unit is connected in parallel with the first resistor unit, and the second unidirectional conducting unit is connected in parallel with the second resistor unit.
6. The drive circuit according to claim 2, characterized by The driver module also includes: A filtering unit is electrically connected to the drain of the P-type transistor and the drain of the N-type transistor.
7. The drive circuit according to claim 6, characterized in that, The filtering unit includes: The capacitor unit and the third resistor unit are provided. The first terminal of the capacitor unit is electrically connected to the drain of the P-type transistor and the N-type transistor, and the third terminal of the capacitor unit is electrically connected to the third resistor unit.
8. The drive circuit of claim 2, wherein, The driver module also includes: The device includes a pull-up unit and a pull-down unit. The pull-up unit is electrically connected to the output terminal of the dual-channel driver chip and the source of the P-type transistor, respectively. The pull-down unit is electrically connected to the output terminal of the dual-channel driver chip and the source of the N-type transistor, respectively.
9. The drive circuit of claim 1, wherein, The switching module is a switch module, which is a multi-channel switch module, and the multi-channel switch module includes multiple single-pole single-throw switch units.
10. The drive circuit according to claim 9, characterized in that, The driving circuit also includes: A power module for electrically connecting with the signal source, the control module and the driver module. A power module for electrically connecting with the signal source, the control module and the driver module.