A phase-locked loop lock loss detection and recovery circuit, a phase-locked loop circuit and an electronic device

Abstract

The utility model describes a kind of phase-locked loop lockout detection and recovery circuit, comprising: reference voltage generating circuit, lockout voltage or operating voltage is output based on feedback control signal, lockout voltage is less than operating voltage;Comparison circuit, the output end of reference voltage generating circuit is connected to the first input end, second input end receives control voltage, to compare and output comparison signal to the voltage of reference voltage generating circuit output and control voltage;Logic gate circuit, the output end of comparison circuit is connected, and feedback control signal is output based on comparison signal and loop switch signal.The utility model further describes a kind of phase-locked loop circuit comprising above-mentioned phase-locked loop lockout detection and recovery circuit and electronic equipment comprising the phase-locked loop circuit.The application using extremely simple analog circuit has realized the function of phase-locked loop loop lockout reset, greatly improves the flexibility of locking recovery circuit.

Description

Technical Field

[0001] This utility model relates to the field of communications, and in particular to a phase-locked loop (PLL) loss detection and recovery circuit, a PLL circuit including the PLL loss detection and recovery circuit, and an electronic device including the PLL circuit. Background Technology

[0002] Phase-locked loops (PLLs) have a significant impact on improving equipment performance, ensuring signal synchronization, and driving technological development in modern electronic devices. With continuous technological advancements, the application of PLLs will become more widespread, and their influence on modern electronic devices will become even more pronounced.

[0003] Phase-locked loops (PLLs) have three operating phases: the locked phase, the unlocked phase, and the setup phase. In existing PLL unlock detection technology, digital detection circuits are typically used to detect the difference between the feedback clock count and a predetermined number of counts within each set period. When the difference exceeds a set threshold within a certain set period, the PLL is considered unlocked, causing the PLL frequency synthesizer to re-enter the open-loop coarse adjustment phase. Currently, there is an urgent need to design analog circuits to replace digital circuits and achieve independent control of the unlocked voltage point and the locked voltage point, thereby increasing the flexibility of the PLL lock-up recovery circuit. Utility Model Content

[0004] In view of this, the present invention provides a phase-locked loop (PLL) loss detection and recovery circuit, comprising: a reference voltage generation circuit, which outputs a loss voltage or a working voltage based on a feedback control signal, wherein the loss voltage is less than the working voltage; a comparison circuit, wherein a first input terminal is connected to the output terminal of the reference voltage generation circuit, and a second input terminal receives a control voltage to compare the voltage output by the reference voltage generation circuit with the control voltage and output a comparison signal; and a logic gate circuit, connected to the output terminal of the comparison circuit, which outputs a feedback control signal based on the comparison signal and the loop switch signal.

[0005] Optionally, the reference voltage generation circuit includes a voltage generation circuit, a first reference voltage circuit, a second reference voltage circuit, and a selection circuit; the voltage generation circuit is used to generate multiple unlock voltages and multiple operating voltages; the first reference voltage circuit is connected between the voltage generation circuit and the selection circuit to output a fixed unlock voltage to the selection circuit; the second reference voltage circuit is connected between the voltage generation circuit and the selection circuit to output a fixed operating voltage to the selection circuit; the control terminal of the selection circuit receives a feedback control signal and selectively outputs the unlock voltage or the operating voltage based on the feedback control signal.

[0006] Optionally, the first reference voltage circuit includes at least a first mux selector, the multiple inputs of which respectively receive multiple unlock voltages output by the voltage generation circuit, and selectively output one of the unlock voltages based on a register control signal; the second reference voltage circuit includes at least a second mux selector, the multiple inputs of which respectively receive multiple operating voltages output by the voltage generation circuit, and selectively output one of the operating voltages based on a register control signal; the selection circuit includes a third mux selector, which outputs either the unlock voltage or the operating voltage based on a feedback control signal.

[0007] Optionally, the voltage range for various unlocking voltages is 0.1V to 0.4V, and the voltage range for various operating voltages is 0.9V to 1.2V.

[0008] Optionally, the voltage generation circuit includes N resistors connected in series, with the other end of the first resistor connected to the power supply voltage and the other end of the last resistor grounded, wherein N≥5, and the output voltage between any two adjacent resistors is sent to the first reference voltage circuit or the second reference voltage circuit.

[0009] Optionally, the comparison circuit includes a comparator and a hysteresis circuit; the non-inverting input of the comparator is connected to the output of the reference voltage generation circuit, and the inverting input of the comparator is connected to the hysteresis circuit; the hysteresis circuit receives the control voltage and adjusts the hysteresis time of the comparator switching based on the switching control signal.

[0010] Optionally, the hysteresis circuit includes a resistor network and a capacitor. One end of the resistor network receives the control voltage, and the other end of the resistor network is connected to the inverting input terminal of the comparator along with the upper plate of the capacitor. The lower plate of the capacitor is grounded. The resistor network includes at least two resistors connected in series, and at least one of the two resistors is connected in parallel with a switching transistor to adjust the hysteresis time of the comparator switching by controlling the conduction of the switching transistor through a switching control signal.

[0011] Optionally, the logic gate circuit includes interconnected NAND gates and NOT gates. One end of the NAND gate receives the loop switch signal, the other end of the NAND gate is connected to the output of the comparator circuit, and the output of the NAND gate is connected to the input of the NOT gate, so as to output the feedback control signal through the NOT gate.

[0012] This utility model also provides a phase-locked loop circuit, including: a frequency-phase detector, which outputs a corresponding pulse signal based on the phase difference and frequency difference between a reference clock signal and a feedback clock signal; a charge pump, connected to the frequency-phase detector, which outputs a corresponding charging current or discharging current based on the pulse signal, and outputs a control voltage based on the charging current or discharging current; a voltage-controlled oscillator, connected to the charge pump, which outputs a corresponding clock signal according to the control voltage and feeds back the feedback clock signal to the frequency-phase detector; and the above-mentioned phase-locked loop loss detection and recovery circuit, which outputs a feedback control signal to the frequency-phase detector and the voltage-controlled oscillator to turn the frequency-phase detector and the voltage-controlled oscillator on or off.

[0013] This invention also provides an electronic device that includes the above-described phase-locked loop circuit.

[0014] Compared with the prior art, the present invention has at least the following outstanding advantages:

[0015] This application adopts a technical solution based on a phase-locked loop (PLL) loss detection and recovery circuit with an adjustable control voltage. It uses an extremely simple circuit to realize the function of PLL loop loss reset, which solves the technical problems of complex architecture and excessive area of ​​the original circuit. It also realizes independent control of the detection of the loss voltage point and the recovery of the lock voltage point, which greatly improves the flexibility of the lock recovery circuit. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a phase-locked loop circuit structure in the prior art;

[0017] Figure 2 This is a schematic diagram of a phase-locked loop loss detection and recovery circuit provided in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of another phase-locked loop loss detection and recovery circuit provided in this embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the voltage generation circuit provided in an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of another phase-locked loop loss detection and recovery circuit provided in this embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of a phase-locked loop circuit provided in an embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of another phase-locked loop circuit provided in this embodiment of the present invention. Detailed Implementation

[0023] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described below in conjunction with the accompanying drawings and embodiments.

[0024] It should be noted that specific details are set forth in the following description to provide a full understanding of the present invention. However, the present invention can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0025] like Figure 1 As shown, Figure 1 This is a schematic diagram of a phase-locked loop (PLL) circuit structure in the prior art, which includes:

[0026] The phase-frequency discriminator PFD_CP outputs pull-up and pull-down pulse signals based on the phase and frequency differences between the reference clock signal Ref_clk and the feedback clock signal Fb_clk. The charge pump LPF, connected to the phase-frequency discriminator PFD_CP, generates corresponding charging or discharging currents based on the aforementioned pull-up or pull-down pulse signals and outputs a control voltage Vctrl. The voltage-controlled oscillator VCO, connected to the charge pump LPF, outputs the corresponding clock signal through PLL_out based on the control voltage Vctrl and feeds back the feedback clock signal Fb_clk to the phase-frequency discriminator PFD_CP.

[0027] If a phase-locked loop (PLL) circuit in the present technology is in the unlocking stage, a corresponding PLL_pd signal is usually generated by a digital circuit to control the switching of the devices in the PLL circuit and restore it to normal operation.

[0028] Therefore, this application uses analog circuits instead of digital circuits to achieve independent control of the detection of the unlock voltage point and the recovery of the lock voltage point, thereby increasing the flexibility of the phase-locked loop lock recovery circuit.

[0029] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a phase-locked loop (PLL) loss detection and recovery circuit provided in an embodiment of the present invention, comprising:

[0030] Reference voltage generation circuit 10 outputs either the unlock voltage Vref_lo or the operating voltage Vref_hi based on the feedback control signal PLL_loop_pd, where the unlock voltage Vref_lo is less than the operating voltage Vref_hi.

[0031] Optionally, the unlock voltage Vref_lo has a voltage range of 0.1V to 0.4V, and the operating voltage Vref_hi has a voltage range of 0.9V to 1.2V.

[0032] Understandably, the reference voltage generation circuit 10 can selectively output different voltage values ​​based on the feedback control signal PLL_loop_pd. The feedback control signal PLL_loop_pd indicates whether the phase-locked loop (PLL) circuit is in an unlocked or unlocked state. The unlocked state refers to the PLL circuit being in the setup or locking phase. For example, when the feedback control signal PLL_loop_pd is 0, the PLL circuit is in an unlocked state, and the reference voltage generation circuit 10 outputs an unlocked voltage Vref_lo. Conversely, when the feedback control signal PLL_loop_pd is 1, the PLL circuit is in an unlocked state, and the reference voltage generation circuit 10 outputs an operating voltage Vref_hi.

[0033] The comparison circuit 20 has a first input terminal connected to the output terminal of the reference voltage generation circuit 10, and a second input terminal receiving the control voltage Vctrl, so as to compare the voltage vref_loop output by the reference voltage generation circuit 10 with the control voltage Vctrl and output a comparison signal.

[0034] Understandably, the voltage value of the voltage Vref_loop output by the reference voltage generation circuit 10 is either the unlock voltage Vref_lo or the operating voltage Vref_hi. That is, the comparator circuit 20 can compare the unlock voltage Vref_lo and the control voltage Vctrl and output a comparison signal, or it can compare the operating voltage Vref_hi and the control voltage Vctrl and output a comparison signal.

[0035] Logic gate circuit 30 is connected to the output of comparator circuit 20, and outputs feedback control signal PLL_loop_pd based on the comparison signal and loop switch signal PLL_pd.

[0036] Optionally, the logic gate circuit 30 may include interconnected NAND gates (nor) and NOT gates (inv). One end of the NAND gate (nor) receives the loop switch signal PLL_pd, and the other end of the NAND gate (nor) is connected to the output of the comparator circuit 210. The output of the NAND gate (nor) is connected to the input of the NOT gate (inv) so that the feedback control signal PLL_loop_pd is output through the NOT gate (inv).

[0037] Specifically, the loop switch signal PLL_pd indicates whether the phase-locked loop (PLL) circuit is in the on or off phase. For example, when the loop switch signal PLL_pd is 0, the PLL circuit is in the on phase, and when the loop switch signal PLL_pd is 1, the PLL circuit is in the off phase.

[0038] In this embodiment of the application, when the loop switch signal PLL_pd = 0, the phase-locked loop circuit is in the open stage. If the phase-locked loop is in a non-unlocked state, the voltage Vref_loop output by the reference voltage generation circuit 10 in the initial state is equal to the unlocked voltage Vref_lo. At this time, the voltage value of the control voltage Vctrl is higher than the unlocked voltage Vref_lo, so the comparison signal output is 0, and the corresponding feedback control signal PLL_loop_pd output is also 0.

[0039] When the loop switch signal PLL_pd = 0, the phase-locked loop (PLL) circuit is in the open phase. If the PLL starts to be in an unlocked state, the control voltage Vctrl will decrease rapidly due to the rapid increase in the loop frequency. When the control voltage Vctrl is lower than the unlocked voltage Vref_lo, the comparison signal output is 1, and the corresponding feedback control signal PLL_loop_pd output is also 1. This controls the reference voltage generation circuit 10 to switch Vref_loop from the unlocked voltage Vref_lo to the operating voltage Vref_hi. The frequency and phase detectors and voltage-controlled oscillators of the PLL are also switched to the off state based on the feedback control signal PLL_loop_pd. At this time, the Vctrl voltage will gradually increase. When the Vctrl voltage is higher than the operating voltage Vref_hi, the comparison signal is 0, the PLL_loop_pd output is 0, and the output voltage Vref_loop of the reference voltage generation circuit 10 switches back to the unlocked voltage Vref_lo, and the PLL circuit returns to the locked state.

[0040] When the loop switch signal PLL_pd = 1, the feedback control signal PLL_loop_pd outputs 1, and the entire phase-locked loop circuit is in the off state.

[0041] Therefore, this application adopts a technical solution based on a phase-locked loop (PLL) loss detection and recovery circuit with an adjustable control voltage. It uses an extremely simple circuit to realize the function of PLL loop loss reset, which solves the technical problems of complex architecture and excessive area of ​​the original circuit. It also realizes independent control of the detection of the loss voltage point and the recovery of the lock voltage point, which greatly improves the flexibility of the lock recovery circuit.

[0042] In some embodiments, in conjunction with reference Figures 3-5 The reference voltage generation circuit 10 includes a voltage generation circuit 101, a first reference voltage circuit 111, a second reference voltage circuit 112, and a selection circuit 120.

[0043] Voltage generation circuit 101 is used to generate multiple unlock voltages Vref_lo and multiple operating voltages Vref_hi;

[0044] Optionally, the voltage generation circuit 101 may include N resistors connected in series. The other end of the first resistor among the N resistors is connected to the power supply voltage, and the other end of the last resistor among the N resistors is grounded. Where N ≥ 5, and the output voltage between any two adjacent resistors is sent to either the first reference voltage circuit 111 or the second reference voltage circuit 112, then the voltage generation circuit 101 can generate at least four voltage values. Specifically, as shown... Figure 4 As shown, the voltage generation circuit 101 includes a first resistor R11, a second resistor R21, a third resistor R31, a fourth resistor R41, a fifth resistor R51, a sixth resistor R61, a seventh resistor R71, an eighth resistor R81, and a ninth resistor R91 connected in series. The other end of the first resistor R11 is connected to the power supply voltage VDD, and the other end of the ninth resistor R91 is grounded. Specifically, a first voltage V1 is output between the first resistor R11 and the second resistor R21; a second voltage V2 is output between the second resistor R21 and the third resistor R31; a third voltage V3 is output between the third resistor R31 and the fourth resistor R41; and a third voltage V41 is output between the fourth resistor R41 and the fifth resistor R51. The fourth voltage V4 is output between the fifth resistor R51 and the sixth resistor R61, the sixth voltage V6 is output between the sixth resistor R61 and the seventh resistor R71, the seventh voltage V7 is output between the seventh resistor R71 and the eighth resistor R81, and the eighth voltage V8 is output between the eighth resistor R81 and the ninth resistor R91. Thus, the first voltage V1 < the second voltage V2 < the third voltage V3 < the fourth voltage V4 < the fifth voltage V5 < the sixth voltage V6 < the seventh voltage V7 < the eighth voltage V8. The voltages V1-V4 are output as the unlock voltage to the first reference voltage circuit 111, and the voltages V5-V8 are output as the working voltage to the second reference voltage circuit 112.

[0045] The first reference voltage circuit 111 is connected between the voltage generation circuit 101 and the selection circuit 120 to output a fixed unlock voltage Vref_lo to the selection circuit 120.

[0046] Optional, such as Figure 5As shown, the first reference voltage circuit 111 includes at least a first mux selector. Multiple input terminals of the first mux selector receive various unlock voltages Vref_lo output by the voltage generation circuit 101, and selectively output one of the unlock voltages Vref_lo based on the register control signal sel<1:0>. It can be understood that the register control signal refers to setting the value of the unlock voltage Vref_lo by sending a signal through a register. The value range is the first voltage V1, the second voltage V2, the third voltage V3, and the fourth voltage V4. Therefore, the corresponding register control signal has 2 bits, meaning the register control signal sel<1:0> can be 00, 01, 10, or 11 to correspond to the output of the four voltages V1-V4 respectively. Further optionally, the voltage range of the various unlock voltages Vref_lo is 0.1V to 0.4V, meaning the first mux selector selectively outputs a voltage value between 0.1V and 0.4V based on the register control signal.

[0047] The second reference voltage circuit 112 is connected between the voltage generation circuit 101 and the selection circuit 120 to output a fixed working voltage to the selection circuit 120.

[0048] Optionally, the second reference voltage circuit 112 includes at least a second mux selector. Multiple inputs of the second mux selector receive various operating voltages Vref_hi output by the voltage generation circuit 101, and selectively output one of the operating voltages Vref_hi based on the register control signal sel<1:0>. Similarly, the register control signal sets the value of the operating voltage Vref_hi by sending a signal through the register. The value range is the fifth voltage V5, the sixth voltage V6, the seventh voltage V7, and the eighth voltage V8. That is, the register control signal sel<1:0> can be 00, 01, 10, or 11 to correspond to the output of the four voltages V5-V8 respectively. Further, optionally, the voltage range of the various operating voltages Vref_hi is 0.9V to 1.2V, meaning the second mux selector selectively outputs a voltage value between 0.9V and 1.2V based on the register control signal.

[0049] The control terminal of the selection circuit 120 receives the feedback control signal PLL_loop_pd and selectively outputs the unlock voltage Vref_lo or the operating voltage Vref_hi based on the feedback control signal PLL_loop_pd.

[0050] Optionally, the selection circuit 120 includes a third mux selector, which outputs an unlock voltage Vref_lo or an operating voltage Vref_hi based on a feedback control signal.

[0051] In this embodiment, multiple adjustable levels of the unlock voltage Vref_lo or the operating voltage Vref_hi are achieved through a mux selector, further increasing the robustness of the phase-locked loop recovery circuit. Secondly, multiple unlock voltages Vref_lo and operating voltages Vref_hi are generated by using multiple series resistors, eliminating the need for additional bias current and reference voltage, thus reducing the layout area.

[0052] In some embodiments, reference Figure 3 and Figure 5 The comparator circuit 20 includes a comparator 210 and a hysteresis circuit 220;

[0053] The non-inverting input of comparator 220 is connected to the output of reference voltage generation circuit 10, and the inverting input of comparator 210 is connected to hysteresis circuit 220.

[0054] Hysteresis circuit 220 receives control voltage Vctrl and adjusts the hysteresis time of comparator 210 based on the switching control signal.

[0055] Optionally, the hysteresis circuit 220 includes a resistor network and a capacitor. One end of the resistor network receives a control voltage, and the other end of the resistor network is connected to the inverting input of the comparator along with the upper plate of the capacitor. The lower plate of the capacitor is grounded. The resistor network includes at least two resistors connected in series, and at least one of the two resistors is connected in parallel with a switching transistor to adjust the hysteresis time of the comparator switching by controlling the conduction of the switching transistor through a switching control signal. For example, as shown... Figure 5 As shown, the hysteresis circuit 220 includes a resistor network formed by a first hysteresis resistor R1, a second hysteresis resistor R2, a third hysteresis resistor R3, and a fourth hysteresis resistor R4 connected in series; a first switch 221 connected in parallel with the second hysteresis resistor R2; and a second switch 222 connected in parallel with the third hysteresis resistor R3 and the fourth hysteresis resistor R4. Both the first switch 221 and the second switch 222 are turned on or off based on a switch control signal. One end of the resistor network receives a control voltage Vctrl, and the other end of the resistor network is connected to the inverting input terminal of the comparator 210 along with the upper plate of the capacitor 223. The lower plate of the capacitor 223 is grounded. In this embodiment, by switching the first switch 221 and the second switch 222, there are four adjustable hysteresis time levels: both the first switch 221 and the second switch 222 are off, the first switch 221 is on but the second switch 222 is off, the first switch 221 is off but the second switch 222 is on, and both the first switch 221 and the second switch 222 are on. The hysteresis time under the above four levels decreases in sequence.

[0056] If the control voltage Vctrl is directly connected to the inverting input of the comparator, glitches in the control voltage Vctrl may cause the comparator to flip incorrectly, resulting in an error in the signal output. Therefore, in this embodiment, the hysteresis circuit formed by the resistor network and capacitor can be used as an RC filter to avoid small glitches and pulses in the control voltage Vctrl causing the comparator to flip incorrectly. Furthermore, by controlling the number of series resistors by turning the switching transistor on and off, the hysteresis time of the comparator can be adjusted, further increasing the robustness of the comparator circuit.

[0057] This application also provides a phase-locked loop circuit, such as Figure 6 As shown, the phase-locked loop circuit includes:

[0058] The phase and frequency detector PFD_CP outputs a corresponding pulse signal based on the phase difference and frequency difference between the reference clock signal Ref_clk and the feedback clock signal Fb_clk.

[0059] The charge pump LPF is connected to the frequency and phase detector PFD_CP. Based on the pulse signal, it outputs the corresponding charging current or discharging current, and outputs the control voltage Vctrl based on the charging current or discharging current.

[0060] The voltage-controlled oscillator (VCO) is connected to the charge pump (LPF). Based on the control voltage (Vctrl), it outputs the corresponding clock signal through PLL_out and feeds back the feedback clock signal (Fb_clk) to the phase-frequency detector (PFD_CP).

[0061] The aforementioned phase-locked loop (PLL) loss detection and recovery circuit includes: a reference voltage generation circuit, which outputs a loss voltage Vref_lo or a working voltage Vref_hi based on the feedback control signal PLL_loop_pd, wherein the loss voltage Vref_lo is less than the working voltage Vref_hi; a comparison circuit, whose first input is connected to the output of the reference voltage Vref generation circuit and whose second input receives the control voltage Vctrl, to compare the voltage vref_loop output by the reference voltage generation circuit with the control voltage Vctrl and output a comparison signal; and a logic gate circuit, connected to the output of the comparison circuit, which outputs a feedback control signal PLL_loop_pd to the phase-frequency detector PFD_CP and the voltage-controlled oscillator VCO based on the comparison signal and the loop switch signal PLL_pd, to turn the phase-frequency detector PFD_CP and the voltage-controlled oscillator VCO on or off.

[0062] Optional, such as Figure 7As shown, based on the above embodiment, the phase-locked loop circuit further includes: a frequency divider / N, one end of which is connected to the voltage-controlled oscillator (VCO), and the other end of which is connected to the frequency and phase detector (PFD_CP), so as to divide the clock signal output by the VCO and output a feedback clock signal Fb_clk to the frequency and phase detector (PFD_CP).

[0063] In this embodiment, when the loop switch signal PLL_pd = 0, the phase-locked loop (PLL) circuit is in the open phase. If the PLL loop is in a non-unlocked state, the voltage Vref_loop output by the reference voltage generation circuit 10 in the initial state is equal to the unlocked voltage Vref_lo. At this time, the control voltage Vctrl is higher than the unlocked voltage Vref_lo, so the comparison signal output is 0, and the corresponding feedback control signal PLL_loop_pd output is also 0. When the loop switch signal PLL_pd = 0, the PLL circuit is in the open phase, and the PLL loop begins to be in an unlocked state, the control voltage Vctrl will decrease rapidly due to the rapid increase in the loop frequency. When the control voltage Vctrl is lower than the unlocked voltage Vref_lo, the comparison signal output is 1, and the corresponding feedback control signal PLL_loop_pd output is also 1. The output of _loop_pd is also 1, which controls the reference voltage generation circuit 10 to switch Vref_loop from the unlock voltage Vref_lo to the operating voltage Vref_hi. The phase-locked loop's frequency and phase detectors and voltage-controlled oscillators are also switched to the off state based on the feedback control signal PLL_loop_pd. At this time, the Vctrl voltage will gradually increase. When the Vctrl voltage is higher than the operating voltage Vref_hi, the comparison signal is 0, the output of PLL_loop_pd is 0, and the output of PLL_loop_pd is 0. At this time, the output voltage Vref_loop of the reference voltage generation circuit 10 switches back to the unlock voltage Vref_lo, and the phase-locked loop returns to the locked state. When the loop switch signal PLL_pd = 1, the output of the feedback control signal PLL_loop_pd is 1, and the entire phase-locked loop circuit is in the off state.

[0064] Therefore, this application adopts a phase-locked loop circuit that includes an adjustable control voltage phase-locked loop loss detection and recovery circuit. It uses an extremely simple circuit to realize the function of phase-locked loop loss reset, which solves the technical problems of complex architecture and excessive area of ​​the original architecture. It also realizes independent control of the detection of the loss voltage point and the recovery of the lock voltage point, which greatly improves the flexibility of the lock recovery circuit.

[0065] This application also provides an electronic device including the aforementioned phase-locked loop (PLL) circuit. PLLs are found in various high-frequency applications, from simple clock cleanup circuits to local oscillators (LOs) used in high-performance radio communication links, as well as ultrafast switching frequency synthesizers in vector network analyzers (VNAs), image sensors, and the like.

[0066] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the protection scope of the present invention.

Claims

1. A phase-locked loop (PLL) loss detection and recovery circuit, characterized in that, include: A reference voltage generation circuit outputs an unlock voltage or a working voltage based on a feedback control signal, wherein the unlock voltage is less than the working voltage. The comparison circuit has a first input terminal connected to the output terminal of the reference voltage generation circuit, and a second input terminal receiving a control voltage to compare the voltage output by the reference voltage generation circuit with the control voltage and output a comparison signal. A logic gate circuit is connected to the output of the comparator circuit and outputs the feedback control signal based on the comparator signal and the loop switch signal.

2. The phase-locked loop loss detection and recovery circuit as described in claim 1, characterized in that, The reference voltage generation circuit includes a voltage generation circuit, a first reference voltage circuit, a second reference voltage circuit, and a selection circuit; The voltage generating circuit is used to generate various unlock voltages and various operating voltages; The first reference voltage circuit is connected between the voltage generation circuit and the selection circuit to output a fixed unlock voltage to the selection circuit; The second reference voltage circuit is connected between the voltage generating circuit and the selection circuit to output a fixed operating voltage to the selection circuit; The control terminal of the selection circuit receives the feedback control signal and selectively outputs the unlock voltage or the operating voltage based on the feedback control signal.

3. The phase-locked loop loss detection and recovery circuit as described in claim 2, characterized in that, The first reference voltage circuit includes at least a first mux selector. The multiple input terminals of the first mux selector respectively receive multiple unlock voltages output by the voltage generation circuit, and selectively output one of the unlock voltages based on the register control signal. The second reference voltage circuit includes at least a second mux selector. The multiple input terminals of the second mux selector respectively receive multiple operating voltages output by the voltage generation circuit, and selectively output one of the operating voltages based on the register control signal. The selection circuit includes a third mux selector, which outputs the unlock voltage or the operating voltage based on the feedback control signal.

4. The phase-locked loop loss detection and recovery circuit as described in claim 2, characterized in that, The voltage range of the various unlocking voltages is 0.1V to 0.4V, and the voltage range of the various operating voltages is 0.9V to 1.2V.

5. The phase-locked loop loss detection and recovery circuit as described in claim 2, characterized in that, The voltage generation circuit includes N resistors connected in series. The other end of the first resistor in the N resistors is connected to the power supply voltage, and the other end of the last resistor in the N resistors is grounded. N ≥ 5, and the voltage output between any two adjacent resistors is sent to the first reference voltage circuit or the second reference voltage circuit.

6. The phase-locked loop loss detection and recovery circuit as described in claim 1, characterized in that, The comparison circuit includes a comparator and a hysteresis circuit; The non-inverting input of the comparator is connected to the output of the reference voltage generation circuit, and the inverting input of the comparator is connected to the hysteresis circuit. The hysteresis circuit receives the control voltage and adjusts the hysteresis time of the comparator switching based on the switch control signal.

7. The phase-locked loop loss detection and recovery circuit as described in claim 6, characterized in that, The hysteresis circuit includes a resistor network and a capacitor. One end of the resistor network receives the control voltage, and the other end of the resistor network and the upper plate of the capacitor are connected to the inverting input terminal of the comparator. The lower plate of the capacitor is grounded. The resistor network includes at least two resistors connected in series, and at least one of the two resistors is connected in parallel with a switching transistor, so as to adjust the hysteresis time of the comparator switching by controlling whether the switching transistor is turned on or off through the switching control signal.

8. The phase-locked loop loss detection and recovery circuit as described in claim 1, characterized in that, The logic gate circuit includes interconnected NAND gates and NOT gates. One end of the NAND gate receives the loop switch signal, the other end of the NAND gate is connected to the output of the comparator circuit, and the output of the NAND gate is connected to the input of the NOT gate, so as to output the feedback control signal through the NOT gate.

9. A phase-locked loop circuit, characterized in that, include: The frequency and phase detector outputs a corresponding pulse signal based on the phase difference and frequency difference between the reference clock signal and the feedback clock signal; A charge pump, connected to the frequency and phase detector, outputs a corresponding charging current or discharging current based on the pulse signal, and outputs a control voltage based on the charging current or discharging current. A voltage-controlled oscillator, connected to the charge pump, outputs a corresponding clock signal according to the control voltage, and feeds back the feedback clock signal to the frequency and phase detector; The phase-locked loop loss detection and recovery circuit as described in any one of claims 1-8 outputs the feedback control signal to the frequency and phase detector and the voltage-controlled oscillator to turn the frequency and phase detector and the voltage-controlled oscillator on or off.

10. An electronic device, characterized in that, Includes the phase-locked loop circuit as described in claim 9.

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