Multi-channel signal detection system and optical module

Abstract

The utility model discloses a kind of multi-channel signal detection system and optical module, comprising: digital signal processor, control module and first inverter circuit;Digital signal processor includes: at least two first signal level output port;Control module includes: first interrupt input interface and drain open circuit output interface;Each first signal level output port is connected with first interrupt input interface by first inverter circuit;Wherein, first inverter circuit, the output level of each first signal level output port is configured to level inversion, as the circuit of the first input level of first interrupt input interface after line and logic processing;Wherein, control module is configured to drain open circuit output interface output corresponding instruction signal with first input level. Only control module provides an interface to receive the signal processing result of multi-channel in digital signal processor, so that multi-channel signal detection can be supported simultaneously.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a multi-channel signal detection system and optical module. Background Technology

[0002] In the Quad Small Form Factor Pluggable 112 Multi Source Agreement (QSFP112 MSA) and the Quad Small Form Factor Pluggable-Double Density MultiSource Agreement (QSFP-DD MSA), the Interrupt (IntL) / Receiver Loss of Signal-Low (RxLOSL) is a functionally multiplexed active-low indicator using an open-drain output level to indicate changes in the optical module's status or a fault condition. This signal is pulled high to the positive supply voltage (Vcc) when the optical module is inserted into the motherboard.

[0003] In RxLOSL operating mode, most applications only require a response time of no more than 100ms, meaning the digital signal processor (DSP) register status can be read via the integrated circuit bus for monitoring. However, in the fast optical response mode within RxLOSL, a response time of 1ms is required, and the time required for software reading is insufficient to meet protocol requirements. Utility Model Content

[0004] This invention provides a multi-channel signal detection system and optical module, enabling the optical module to simultaneously support multi-channel signal detection, determine the working state of the optical module at a higher speed, and improve the level response efficiency of the RxLOSL working mode.

[0005] In a first aspect, this utility model provides a multi-channel signal detection system, including: a digital signal processor, a control module, and a first inverting circuit; the digital signal processor includes: at least two first signal level output ports; the control module includes: a first interrupt input interface and an open-drain output interface;

[0006] Each first signal level output port is connected to the first interrupt input interface through a first inverting circuit;

[0007] The first inverting circuit is configured to invert the output level of each first signal level output port and use the result of wired-AND logic processing as the first input level of the first interrupt input interface.

[0008] The control module is configured to output an indication signal corresponding to the first input level at the open-drain output interface.

[0009] Secondly, this utility model embodiment also provides an optical module, including a multi-channel signal detection system as described in any of the above embodiments.

[0010] This utility model provides a multi-channel signal detection system and optical module, including: a digital signal processor, a control module, and a first inverting circuit; the digital signal processor includes: at least two first signal level output ports; the control module includes: a first interrupt input interface and an open-drain output interface; each first signal level output port is connected to the first interrupt input interface through the first inverting circuit; wherein, the first inverting circuit is configured to invert the output level of each first signal level output port and use it as the first input level of the first interrupt input interface after wired-AND logic processing; wherein, the control module is configured to output an indication signal corresponding to the first input level at the open-drain output interface. By adopting the above technical solution, the output levels of multiple first signal level output ports in the digital signal processor are inverted and wired-ANDed through the first inverting circuit to obtain the first input level of the first interrupt input interface in the input control module. This enables simultaneous processing of multiple channels of signals in the digital signal processor, and only requires the control module to provide one interrupt input interface to receive the signal processing results of multiple channels in the digital signal processor. This reduces circuit complexity, allows multi-channel signal detection to be supported simultaneously without the need for one-to-one multiple software reads, and enables the determination of the working state in the optical module at a higher speed, thus improving the level response efficiency.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1A schematic diagram of the structure of a multi-channel signal detection system provided in an embodiment of this utility model;

[0014] Figure 2 A circuit structure example diagram of a multi-channel signal detection system provided for an embodiment of this utility model;

[0015] Figure 3 This invention provides a schematic diagram of another multi-channel signal detection system for embodiments of the present invention.

[0016] Figure 4 An example circuit structure diagram of another multi-channel signal detection system provided in this embodiment of the present invention;

[0017] Figure 5 An example circuit structure diagram of another multi-channel signal detection system provided in this embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] In one embodiment, Figure 1 This is a schematic diagram of a multi-channel signal detection system provided in an embodiment of the present invention. This multi-channel signal detection system is applicable to situations requiring rapid response signal status detection for optical modules using multi-channel protocols. The multi-channel signal detection system 1 includes: a digital signal processor 11, a control module 12, and a first inverting circuit 13.

[0021] The digital signal processor 11 includes at least two first signal level output ports 111; the control module 12 includes a first interrupt input interface 121 and an open-drain output interface 122.

[0022] Each first signal level output port 111 is connected to the first interrupt input interface 121 through the first inverting circuit 13.

[0023] The first inverting circuit 13 is configured to invert the output level of each first signal level output port 111 and use the result of wired-AND logic processing as the first input level of the first interrupt input interface 121.

[0024] The control module 12 is configured to output an indication signal corresponding to the first input level at the open-drain output interface 122.

[0025] The control module 12 is used to output an indication signal at the open-drain output interface 122 according to the first input level in the first working mode.

[0026] In this embodiment, the multi-channel signal detection system 1 can be specifically understood as a system used to simultaneously detect signals acquired from multiple channels in a DSP, and to promptly output a prompt signal when any channel malfunctions. In some examples, the multi-channel signal detection system can be installed in optical modules used in data centers and high-performance computing networks to quickly detect the operating status of the optical modules and promptly issue an indication signal when a fault is detected, prompting personnel to check and modify the system.

[0027] In this embodiment, the digital signal processor 11 can be specifically understood as an electronic device in the multi-channel signal detection system 1 used to process high-speed digital signals, compensate for damage during signal transmission, and improve the performance and reliability of the optical communication system. The digital signal processor 11 may include at least two first signal level output ports 111, each of which is used to output the loss of lock (LOL) signal of the optical signal in one channel.

[0028] In this embodiment, the control module 12 can be specifically understood as an electronic device in the multi-channel signal detection system 1 used for interacting with external devices and for internal control, monitoring, and communication. It can be used to process and detect signals input from the digital signal processor 11 to determine the operating state of the multi-channel signal detection system 1. The first operating mode can be specifically understood as the RxLOSL operating mode.

[0029] In this embodiment, the first inverting circuit 13 can be specifically understood as a circuit between the digital signal processor 11 and the control module 12, used to invert the levels of the multi-channel electrical signals output by the digital signal processor 11 and perform wired-AND logic processing, so that the multi-channel electrical signals can be integrated into a single signal input to the control module 12. Specifically, the wired-AND logic can be understood as connecting the output terminals of multiple logic gates with open-collector or open-drain output structures to the same wire, so that the output terminal is pulled high only when all logic gate outputs are high; and if any logic gate output is low, the output terminal is pulled low. That is, in this embodiment, the first inverting circuit can be understood as connecting the signals of multiple first signal level output ports to the same wire, and inputting them to the control module 12 through the wire and the pull-up resistor connected to the wire.

[0030] In this embodiment, the first interrupt input interface 121 can be specifically understood as the input interface in the control module 12 used to receive the operating status signal of the digital signal processor 11 in the RxLOSL operating mode. The open-drain output interface 122 can be specifically understood as the output interface in the control module 12 used to output the IntL / RxLOSL status externally, which can be understood as the indication signal in this embodiment of the present invention. In some examples, the open-drain output interface 122 can be connected to a gold finger to output the indication signal externally through the gold finger.

[0031] Specifically, the multi-channel signal detection system 1 includes at least a digital signal processor 11 and a control module 12. The digital signal processor 11 includes at least two first signal level output ports 111, each corresponding to one channel on the digital signal processor 11. That is, the digital signal processor 11 can simultaneously output multiple channels of electrical signals through multiple first signal level output ports 111. The control module 12 includes a first interrupt input interface 121 for receiving the operating status signal of the digital signal processor 11 in RxLOSL operating mode, and an open-drain output interface 122 for outputting indication signals. Each first signal level output port 111 is connected to the first interrupt input interface 121 through a first inverting circuit 13 to realize the conversion and input of multi-channel signals to a single interface. When the multi-channel signal detection system 1 is in its first operating mode, the digital signal processor 11 outputs LOL signals through multiple first signal level output ports 111. Each LOL signal, as the output level of its respective first signal level output port 111, is inverted by the first inverting circuit 13 and processed by wired-AND logic to serve as the first input level of the first interrupt input interface 121 in the control module 12. That is, if the control module 12 receives the first input level of the first interrupt input interface 121, it can be considered to be operating in the first operating mode. The signal processing logic of the first operating mode determines the indication signal that should be output at the open-drain output interface 122 based on the first input level.

[0032] It is understood that the indication signal in the embodiments of this utility model can be understood as a signal used to issue an alarm to the outside world, and the embodiments of this utility model do not limit it in this way.

[0033] The technical solution of this utility model embodiment provides a multi-channel signal detection system, including: a digital signal processor, a control module, and a first inverting circuit; the digital signal processor includes: at least two first signal level output ports; the control module includes: a first interrupt input interface and an open-drain output interface; each first signal level output port is connected to the first interrupt input interface through the first inverting circuit; the first inverting circuit is used to invert the output level of each first signal level output port, and after wired-AND logic processing, it is used as the first input level of the first interrupt input interface; the control module is used to output an indication signal at the open-drain output interface according to the first input level in a first working mode. By adopting the above technical solution, the output levels of multiple first signal level output ports in the digital signal processor are inverted and wired-ANDed through the first inverting circuit to obtain the first input level of the first interrupt input interface in the input control module. This enables simultaneous processing of multiple channels of signals in the digital signal processor, and only requires the control module to provide one interrupt input interface to receive the signal processing results of multiple channels in the digital signal processor. This reduces circuit complexity, allows multi-channel signal detection to be supported simultaneously without the need for one-to-one multiple software reads, and enables the determination of the working state in the optical module at a higher speed, thus improving the level response efficiency.

[0034] In some examples, the level state of the indicator signal corresponding to the first input level is consistent with the level state of the first input level.

[0035] In some examples, control module 12 is specifically used for:

[0036] In the first operating mode, an indication signal with the same level as the first input level is output at the open-drain output interface 122.

[0037] Specifically, in the first operating mode, the processing logic of the control module 12 for the input signal to the first interrupt input interface 121 and the output signal of the open-drain output interface 122 is to maintain the level state unchanged. That is, in the first operating mode, if the first input level of the first signal level output port 111 is high, the indicator signal output by the open-drain output interface 122 is a high-level signal to indicate that the multi-channel signal detection system 1 is in an abnormal state; if the first input level of the first signal level output port 111 is low, the indicator signal output by the open-drain output interface 122 is a low-level signal to indicate that there is a fault of received signal loss in the multi-channel signal detection system 1, thereby realizing the simultaneous detection and external prompting of signal loss in multiple channels.

[0038] In some examples, Figure 2A circuit structure example diagram of a multi-channel signal detection system provided for an embodiment of this utility model is shown below. Figure 2 As shown, taking an example with 4 first signal level output ports 111, this is an illustrative example. Since each first signal level output port 111 is used to output the LOL signal, for ease of description, ... Figure 2 In this code, LOL1-LOL4 represent the four first signal level output ports 111, RX_SD (Receive Signal Detection) represents the first interrupt input interface 121, and RXLOSL represents the open-drain output interface 122.

[0039] like Figure 2 As shown, the first inverting circuit 13 includes a first pull-up resistor 131 and at least two first switching devices 132. It can be understood that when the number of first signal level output ports 111 is 4, the number of first switching devices 132 is also 4.

[0040] Among them, the first signal level output port 111 corresponds one-to-one with the first switching device 132.

[0041] The first pull-up resistor 131 is connected in series between the power supply (VCCIO) of the control module 12 and the first interrupt input interface 121; the control terminal of the first switching device 132 is connected to the corresponding first signal level output port 111; each first switching device 132 is connected in parallel between the ground terminal and the first interrupt input interface 121.

[0042] Optionally, the first switching device 132 may be an N-type metal-oxide-semiconductor field-effect transistor (N MOS). For ease of description, in... Figure 2 In this document, NMOS1-NMOS4 refer to four first switching devices 132. The control terminal of the first switching device 132 is an NMOS whose gate is connected to the first signal level output port 111, whose source is connected to the ground terminal, and whose drain is connected to the first interrupt input interface 121 corresponding to the first switching device 132.

[0043] Specifically, when the open-drain output interface 122 of the control module 12 is configured to operate in the first operating mode, i.e., in RxLOSL mode, LOL1, LOL2, LOL3, and LOL4 of the digital signal processor 11 correspond to the signal status outputs of channels 1, 2, 3, and 4, respectively. When all four channels of the digital signal processor 11 are operating normally, the output level of the first signal level output port 111 corresponding to LOL1, LOL2, LOL3, and LOL4 is low. At this time, NMOS1-NMOS4 are turned off, and the signal input to the first interrupt input interface 121 is high. At this time, the control module 12 outputs a high-level indication signal to the open-drain output interface 122 to indicate that there is no fault in the first operating mode. When any one or more of the four channels of the digital signal processor 11 lose signal in LOLx (x = 1, 2, 3, 4), the faulty channel will output a high level, and its corresponding NMOSx (x = 1, 2, 3, 4) will be turned on. The signal input to the first interrupt input interface 121 will be in a low level state. At this time, the control module 12 will output a low level state indication signal to the open-drain output interface 122 to indicate that a fault has occurred in the first working mode.

[0044] It should be clarified that since the drain voltage of the MOSFET is the voltage of its matched level, the open-drain characteristic in this embodiment of the invention allows for the selection of different drain voltages. That is, the power supply voltage VDDIO of the digital signal processor 11 and the power supply voltage VCCIO of the control module 12 can be the same or different, avoiding the limitation that the control module 12 needs to keep the voltages of the two consistent when it directly reads signals from the digital signal processor 11.

[0045] To more clearly describe the operating state of the multi-channel signal detection system in the first operating mode, this section uses a logic truth table to display the high and low levels of each interface, where 1 represents a high level, 0 represents a low level, and x represents 0 or 1, as shown in the table below:

[0046] LOL1 LOL2 LOL3 LOL4 RX_SD RXLOSL 0 0 0 0 1 1 1 x x x 0 0 x 1 x x 0 0 x x 1 x 0 0 x x x 1 0 0

[0047] In some examples, Figure 3 This invention provides a schematic diagram of another multi-channel signal detection system, which is further enriched based on the above embodiments. The multi-channel signal detection system 1 further includes: a second inverting circuit 14; a digital signal processor 11, which also includes: a second signal level output port 112; a control module 12, which also includes: a second interrupt input interface 123.

[0048] The second signal level output port 112 is connected to the second interrupt input port 123 through the second inverting circuit 14.

[0049] The second inverting circuit 14 is configured to invert the output level of the second signal level output port 112 and use it as the second input level of the second interrupt input interface 123.

[0050] The control module 12 is also configured to output an alarm indication signal corresponding to the second input level at the open-drain output interface 122.

[0051] The control module 12 is also used to output an indication signal at the open-drain output interface 122 according to the second input level in the second working mode.

[0052] In this embodiment, the second signal level output port 112 can be specifically understood as the output port of the digital signal processor 11 used to output the interrupt (INTR) status signal.

[0053] In this embodiment, the second working mode can be specifically understood as the IntL working mode.

[0054] In this embodiment, the second inverting circuit 14 can be specifically understood as a circuit between the digital signal processor 11 and the control module 12, used to invert the level of the INTR status signal output by the digital signal processor 11 and then use it as an input to the control module 12. The second interrupt input interface 123 can be specifically understood as an input interface in the control module 12 used to receive the operating status signal of the digital signal processor 11 in the IntL operating mode.

[0055] Specifically, when the multi-channel signal detection system 1 is in the second operating mode, the digital signal processor 11 outputs an INTR status signal through the second signal level output port 112. This INTR status signal, as the output level of the second signal level output port 112, is inverted by the second inverting circuit 14 and then used as the second input level of the second interrupt input interface 123. That is, if the control module 12 receives the second input level of the second interrupt input interface 123, it can be considered to be operating in the second operating mode. The signal processing logic using the second operating mode determines the indication signal that should be output at the open-drain output interface 122 based on the second input level.

[0056] In some examples, the level state of the indicator signal corresponding to the second input level is the opposite of the level state of the second input level.

[0057] In some examples, control module 12 is specifically used for:

[0058] In the second operating mode, an indication signal with the opposite level state to the second input level is output at the open-drain output interface 122.

[0059] Specifically, in the second operating mode, the processing logic between the input signal to the second interrupt input interface 123 and the output signal of the open-drain output interface 122 of the control module 12 is an inverted level state. That is, in the second operating mode, if the second input level of the second signal level output port 112 is high, the indicator signal output by the open-drain output interface 122 is a low-level signal to indicate that there is an interruption abnormality in the DSP of the multi-channel signal detection system 1; and if the second input level of the second signal level output port 112 is low, the indicator signal output by the open-drain output interface 122 is a high-level signal to indicate that the multi-channel signal detection system 1 is in a normal state.

[0060] In some examples, Figure 4 This is an example circuit structure diagram of another multi-channel signal detection system provided in an embodiment of the present invention, which is as follows: Figure 2 The circuit structure of the multi-channel signal detection system shown is further enriched. For ease of description, in Figure 4 INTR refers to the second signal level output port 112, and INTL refers to the second interrupt input interface 123.

[0061] like Figure 4 As shown, the second inverting circuit 14 includes a second pull-up resistor 141 and a second switching device 142. The second pull-up resistor 141 is connected in series between the power supply (VCCIO) of the control module 12 and the second interrupt input interface 123; the control terminal of the second switching device 142 is connected to the second signal level output port 112; the second switching device 142 is connected in series between the ground terminal and the second interrupt input interface 123.

[0062] Optionally, the second switching device 142 can also be an N-type MOSFET. For ease of description, in Figure 4 In this context, NMOS5 is used to refer to the second switching device 142. The control terminal of the second switching device 142 is an NMOS whose gate is connected to the second signal level output port 112, whose source is connected to ground, and whose drain is connected to the second interrupt input interface 123 corresponding to the second switching device 142.

[0063] Specifically, when the open-drain output interface 122 of the control module 12 is configured to operate in the second operating mode, i.e., IntL mode, and the digital signal processor 11 is in normal working condition, the output level of the INTR interface, i.e., the second signal level output port 112, is high. After being inverted by NMOS5, the signal input to the second interrupt input interface 123 is low. At this time, the control module 12 outputs a high-level indication signal to the open-drain output interface 122 to indicate that there is no fault in the second operating mode. When the digital signal processor 11 experiences an abnormal operating state, the output level of the INTR interface, i.e., the second signal level output port 112, is low. After being inverted by NMOS5, the signal input to the second interrupt input interface 123 is high. At this time, the control module 12 outputs a low-level indication signal to the open-drain output interface 122 to indicate that a fault has occurred in the second operating mode.

[0064] In some examples, Figure 5 This is an example circuit structure diagram of another multi-channel signal detection system provided in an embodiment of the present invention, which is as follows: Figure 4 The circuit structure of the multi-channel signal detection system shown is further enriched, such as... Figure 5 As shown, the digital signal processor 11 further includes: a first integrated circuit bus interface 113; the control module 12 further includes: a second integrated circuit bus interface 124. For ease of description, in... Figure 5 In this text, I2C1 refers to the first integrated circuit bus interface 113, and I2C2 refers to the second integrated circuit bus interface 124.

[0065] The first integrated circuit bus interface 113 is connected to the second integrated circuit bus interface 124 via an integrated circuit bus.

[0066] The control module 12 is also used to read the register status of the digital signal processor 11 through the second integrated circuit bus interface 124, and output an indication signal at the open-drain output interface 122 according to the register status.

[0067] It should be clarified that, in the above embodiments, the control module 12 may include at least one of the following:

[0068] Microcontroller Unit (MCU); Digital Signal Processing Chip; Programmable Logic Controller (PLC); Field-Programmable Gate Array (FPGA); System of Chip (SOC).

[0069] In one embodiment, the present invention also provides an optical module, including a multi-channel signal detection system 1 as provided in any of the above embodiments.

[0070] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A multi-channel signal detection system, characterized in that, include: Digital signal processor, control module, and first inverting circuit; The digital signal processor includes: at least two first signal level output ports; the control module includes: a first interrupt input interface and an open-drain output interface. Each of the first signal level output ports is connected to the first interrupt input interface through the first inverting circuit; The first inverting circuit is configured to invert the output level of each of the first signal level output ports and use the result of wired-AND logic processing as the first input level of the first interrupt input interface. The control module is configured to output an indication signal corresponding to the first input level at the open-drain output interface.

2. The multi-channel signal detection system according to claim 1, characterized in that, The first inverting circuit includes: a first pull-up resistor and at least two first switching devices; Each of the first signal level output ports corresponds one-to-one with the first switching device. The first pull-up resistor is connected in series between the power supply of the control module and the first interrupt input interface; The control terminal of the first switching device is connected to the corresponding first signal level output port; Each of the first switching devices is connected in parallel between the ground terminal and the first interrupt input interface.

3. The multi-channel signal detection system according to claim 1, characterized in that, The level state of the indicator signal corresponding to the first input level is consistent with the level state of the first input level.

4. The multi-channel signal detection system according to claim 1, characterized in that, The multi-channel signal detection system further includes: a second inverting circuit; the digital signal processor further includes: a second signal level output port; the control module further includes: a second interrupt input interface; The second signal level output port is connected to the second interrupt input interface through the second inverting circuit; The second inverting circuit is configured to invert the output level of the second signal level output port and use it as the second input level of the second interrupt input interface. The control module is further configured to output an indication signal corresponding to the second input level at the open-drain output interface.

5. The multi-channel signal detection system according to claim 4, characterized in that, The second inverting circuit includes: a second pull-up resistor and a second switching device; The second pull-up resistor is connected in series between the power supply of the control module and the second interrupt input interface; The control terminal of the second switching device is connected to the second signal level output port; The second switching device is connected in series between the ground terminal and the second interrupt input interface.

6. The multi-channel signal detection system according to claim 4, characterized in that, The level state of the indicator signal corresponding to the second input level is opposite to the level state of the second input level.

7. The multi-channel signal detection system according to claim 2 or 5, characterized in that, The first switching device and / or the second switching device are N-type metal-oxide-semiconductor field-effect transistors; In this configuration, the gate of the N-type metal-oxide-semiconductor field-effect transistor is the control terminal, the source is grounded, and the drain is connected to the corresponding interrupt input interface.

8. The multi-channel signal detection system according to any one of claims 1-6, characterized in that, The power supply voltage of the digital signal processor may be the same as or different from the power supply voltage of the control module.

9. The multi-channel signal detection system according to any one of claims 1-6, characterized in that, The control module includes at least one of the following: microcontroller; Digital signal processing chip; Programmable logic controller; Field-programmable gate arrays (FPGAs); System-on-a-chip.

10. The multi-channel signal detection system according to any one of claims 1-6, characterized in that, The digital signal processor further includes: a first integrated circuit bus interface; the control module further includes: a second integrated circuit bus interface; The first integrated circuit bus interface is connected to the second integrated circuit bus interface through the integrated circuit bus.

11. An optical module, characterized in that, include: The multi-channel signal detection system as described in any one of claims 1-10.

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