A display system supporting access of multiple video formats
By using a multi-standard interface module and a video signal conversion and processing module, the interface compatibility problem of the vehicle display system was solved, achieving video signal compatibility and stable display for different vehicle models, reducing modification costs and environmental pollution.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAMEN INTRETECH AUTOMOTIVE ELECTRONICS CO LTD
- Filing Date
- 2025-08-01
- Publication Date
- 2026-07-21
AI Technical Summary
Existing in-vehicle display systems suffer from insufficient signal compatibility due to their interface architecture design, making them incompatible with the video signal output standards of different vehicle models. This results in high upgrade costs for users and serious environmental pollution problems.
It adopts a multi-standard combination interface module and a multi-standard video signal conversion and processing module, which supports the access and conversion of various video formats such as YPbPr, HDMI, AV, VGA, SERDES, and AHD. The decoding chip converts various signals into RGB888 signals that can be recognized by the LCD display module, and the filtering module removes noise and interference. The connecting cable adopts a multi-layer shielding structure to protect against electromagnetic interference.
It achieves video signal compatibility and universality across different vehicle models, reduces the need for display terminal replacement, lowers production costs, improves display quality and stability, and adapts to complex electromagnetic environments.
Smart Images
Figure CN224538237U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of automotive display technology, and in particular to a display system that supports access to multiple video formats. Background Technology
[0002] With the booming development of the intelligent connected vehicle industry, the demand for functional integration and interactive experience in in-vehicle multimedia systems is continuously increasing. However, due to limitations in interface architecture design, insufficient signal compatibility has become a common technical bottleneck in current in-vehicle display systems. Traditional in-vehicle displays mostly adopt a single interface configuration: for example, devices equipped only with HDMI interfaces cannot adapt to analog composite video signals such as AV and YPbPr, making them difficult to be compatible with vehicles equipped with older central control systems; while display terminals based on analog interfaces cannot meet the transmission requirements of high-definition digital signals (such as SERDES), forming a significant "interface barrier".
[0003] From an industry development perspective, automotive electronic and electrical architecture is rapidly evolving from a distributed to a domain-centralized model, with significant differences in video signal output standards between the central control systems and multimedia players of different vehicle models. Specifically, high-end models have gradually adopted transmission protocols based on interfaces such as SERDES, HDMI, and AHD, while economy vehicles still widely use analog video transmission solutions such as AV, VGA, and YPbPr.
[0004] Existing display systems require separate interface solutions for economy and high-end vehicles, lacking universality and multi-standard signal processing capabilities. Upgrading the vehicle's central control system or replacing the player often necessitates replacing the entire display terminal. This situation significantly increases user modification costs, generates substantial electronic waste, causes environmental pollution, and severely restricts the technological universality and sustainable development of in-vehicle display systems. Utility Model Content
[0005] To address the aforementioned problems, the purpose of this invention is to provide a display system that supports access to multiple video formats.
[0006] This utility model is implemented using the following method: A display system supporting multiple video format access includes a power supply module, a liquid crystal display module, a display control module, and a display driver module. The power supply module is electrically connected to the liquid crystal display module, the display control module, and the display driver module. It also includes a multi-standard interface module and a multi-standard video signal conversion and processing module. The power supply module is electrically connected to both the multi-standard interface module and the multi-standard video signal conversion and processing module. The multi-standard interface module is communicatively connected to the multi-standard video signal conversion and processing module. The multi-standard video signal conversion and processing module is communicatively connected to the display control module and the liquid crystal display module. The multi-standard video signal conversion and processing module converts the signals input by the multi-standard interface module into signals that the liquid crystal display module can recognize.
[0007] Preferably, the multi-standard interface module has a YPbPr interface, an HDMI interface, an AV interface, a VGA interface, a SERDES interface, and an AHD interface. The multi-standard video signal conversion and processing module includes AV, YPbPr, VGA, and HDMI decoding chips and a SERDES deserialization chip, as well as an AHD video decoding LCD control chip. The output terminals of the AV, YPbPr, VGA, and HDMI decoding chips and the SERDES deserialization chip are connected to the input terminals of the AHD video decoding LCD control chip, and the output terminal of the AHD video decoding LCD control chip is connected to the liquid crystal display module. Signals input from the V, YPbPr, VGA, and HDMI interfaces are converted into RGB888 signals by the AV, YPbPr, VGA, and HDMI decoding chips, respectively, and then input to the AHD video decoding LCD control chip to output RGB888 signals to the LCD module. Signals input from the SERDES interface are converted into BT.656 signals by the SERDES deserialization chip, and then input to the AHD video decoding LCD control chip to be converted into RGB888 signals for output to the LCD module. Signals input from the AHD interface are decoded into RGB888 signals by the AHD video decoding LCD control chip and output to the LCD module.
[0008] Preferably, the MCU of the display control module is connected and controlled with the AV, YPBPR, VGA, and HDMI decoding chips, the SERDES deserialization chip, and the AHD video decoding LCD control chip via an I2C bus and GPIO ports. The AV, YPBPR, VGA, and HDMI decoding chips include TSUMV56RUU and LT9211C. The signals input from AV, YPBPR, VGA, and HDMI are uniformly converted into LVDS signals by TSUMV56RUU and input to LT9211C. The LVDS signals are then converted into RGB888 signals by LT9211C and input to the AHD video decoding LCD control chip.
[0009] Preferably, the YPbPr interface, HDMI interface, AV interface, VGA interface, SERDES interface, AHD interface, and AV interface are all connected to a filtering module.
[0010] Preferably, the filtering module of the HDMI interface includes multiple common-mode inductors, which are connected in series between the HDMI interfaces of the AV, YPbPr, VGA, and HDMI decoding chips.
[0011] Preferably, the filtering module of the SERDES interface is a π-shaped filtering module, which is connected to the input terminal of the SERDES interface; the filtering module of the AV interface is a π-shaped filtering module, which is connected between the input terminal of the AV interface and the AV input terminal of the AV, YPbPr, VGA, or HDMI decoding chip; and the filtering module of the AHD interface is a π-shaped filtering module, which is connected between the input terminal of the AHD interface and the AHD input terminal of the AHD video decoding LCD control chip.
[0012] Preferably, the filtering module of the YPBPR interface includes an EMI filtering module and a π-shaped filtering module. The EMI filtering module and the π-shaped filtering module are connected in series between the interface end of the YPBPR interface and the YPBPR interface of the AV, YPBPR, VGA, and HDMI decoding chips. The EMI filtering module consists of multiple common-mode inductors, and the π-shaped filtering module includes a ferrite bead and a capacitor.
[0013] Preferably, the input terminal of the YPBPR interface is further connected to a voltage clamping and DC-DC anti-static module. The voltage clamping and DC-DC anti-static module includes a polarized capacitor connected in series to each pin of the YPBPR interface input side. The two ends of the polarized capacitor are respectively connected to one end of a transient suppression diode, and the other end of the transient suppression diode is grounded. The positive terminal of the polarized capacitor is connected to the input terminal of the YPBPR interface, and the EMI filter module of the YPBPR interface is connected in series to the negative terminal of the polarized capacitor.
[0014] Preferably, the input side of the VGA interface is connected to an electrostatic discharge (ESD) protection and surge protection module. The ESD protection and surge protection module includes one end of a transient suppression diode connected to each pin of the VGA interface input side, the other end of the transient suppression diode being grounded, and a resistor connected in parallel to each transient suppression diode.
[0015] Preferably, the outer surface of the connecting cable for the YPBPR interface, HDMI interface, AV interface, VGA interface, SERDES interface, AHD interface and AV interface is sequentially wrapped with an aluminum foil layer, a braided mesh shielding layer and a PVC layer; the aluminum foil layer is made of single-sided aluminum foil with the conductive side of the single-sided aluminum foil facing outward.
[0016] The beneficial effects of this utility model are as follows: This utility model provides a display system that supports multiple video format access. Compared with the prior art, this utility model has at least the following technical effects: 1. By adding a multi-standard combination interface module and a multi-standard video signal conversion and processing module, it can realize the access and conversion of various different video format signals, breaking the "interface barrier" of traditional vehicle display systems. This allows the same display system to adapt to different signal input standards, improving the system's versatility and compatibility. It also reduces the overall replacement requirement of the display terminal when upgrading the vehicle's central control system or replacing the player, helping to reduce production costs and promoting sustainable industrial development. 2. It achieves accurate conversion of different types of interface input signals, uniformly converting various signals such as AV, YPbPr, VGA, HDMI, AHD, and SERDES into RGB888 signals that the LCD display module can recognize. This ensures stable transmission and normal display of video signals, adapting to multiple signal input formats and improving the system's versatility and compatibility. 3. Each interface is connected to a filtering module, which can filter the input signals, remove noise and interference from the signals, improve signal purity, and thus improve the display quality and stability of the display system. 4. The multi-layered shielding structure of each interface connection cable can effectively shield external electromagnetic interference, reduce signal loss and interference during signal transmission, and ensure the integrity and reliability of signal transmission, making it especially suitable for complex electromagnetic environments in vehicles. Attached Figure Description
[0017] Figure 1 This is a block diagram illustrating the control principle of a display system that supports multiple video formats.
[0018] Figure 2 This is a schematic diagram of the AV, YPbPr, VGA, and HDMI decoding chips and peripheral circuits of the multi-format video signal conversion and processing module of this utility model.
[0019] Figure 3 This is the utility model Figure 2 A magnified view of the left side.
[0020] Figure 4 This is the utility model Figure 2 A magnified view of the central section.
[0021] Figure 5 This is the utility model Figure 2 A magnified view of the right side.
[0022] Figure 6 This is a schematic diagram of the AHD video decoding LCD control chip and peripheral circuit of the multi-standard video signal conversion and processing module of this utility model.
[0023] Figure 7 This is the utility model Figure 6 A magnified view of the left side.
[0024] Figure 8 This is the utility model Figure 6 A magnified view of the right side.
[0025] Figure 9 This is a schematic diagram of the HDMI interface and peripheral circuit of this utility model.
[0026] Figure 10 This is a circuit diagram of the SERDES interface and SERDES deserialization chip of this utility model.
[0027] Figure 11 This is the circuit schematic diagram of the YPBPR interface of this utility model.
[0028] Figure 12 This is the circuit schematic diagram of the VGA interface of this utility model.
[0029] Figure 13 This is the circuit schematic diagram of the AV interface of this utility model.
[0030] Figure 14 This is a circuit schematic diagram of the MCU part of the display control module of this utility model.
[0031] Figure 15 This is a schematic diagram of the connecting wire of this utility model.
[0032] Figure 16 This is a cross-sectional structural diagram of the connecting line of this utility model.
[0033] Explanation of reference numerals: 1. Power supply module; 2. LCD display module; 3. Display control module; 4. Display driver module; 5. Multi-standard combination interface module; 6. Multi-standard video signal conversion and processing module; 7. Aluminum foil layer; 8. Braided mesh shielding layer; 9. PVC layer. Detailed Implementation
[0034] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0035] Please see Figures 1 to 16A display system supporting multiple video format access includes a power module 1, a liquid crystal display module 2, a display control module 3, and a display driver module 4. The power module 1 is electrically connected to the liquid crystal display module 2, the display control module 3, and the display driver module 4. The system also includes a multi-standard interface module 5 and a multi-standard video signal conversion and processing module 6. The power module 1 is electrically connected to both the multi-standard interface module 5 and the multi-standard video signal conversion and processing module 6. The multi-standard interface module 5 is communicatively connected to the multi-standard video signal conversion and processing module 6. The multi-standard video signal conversion and processing module 6 is communicatively connected to the display control module 3 and the liquid crystal display module 2. The multi-standard video signal conversion and processing module 6 converts the signals input from the multi-standard interface module 5 into signals that the liquid crystal display module 2 can recognize. By adding a multi-standard combination interface module 5 and a multi-standard video signal conversion and processing module 6, the system can access and convert signals of various video formats, breaking down the "interface barrier" of traditional vehicle display systems. This allows the same display system to adapt to different signal input standards, improving the system's versatility and compatibility. It also reduces the need for complete replacement of the display terminal when upgrading the vehicle's central control system or changing the player, helping to lower production costs and promoting sustainable industrial development. The power supply module 1, LCD display module 2, display control module 3, and display driver module 4 all utilize existing technologies and are not subject to specific protection requirements.
[0036] Please see Figures 1 to 14Preferably, the multi-standard interface module 5 has a YPbPr interface, an HDMI interface, an AV interface, a VGA interface, a SERDES interface, and an AHD interface. The multi-standard video signal conversion and processing module 6 includes AV, YPbPr, VGA, and HDMI decoding chips and a SERDES deserialization chip, as well as an AHD video decoding LCD control chip. The output terminals of the AV, YPbPr, VGA, and HDMI decoding chips and the SERDES deserialization chip are connected to the input terminal of the AHD video decoding LCD control chip, and the output terminal of the AHD video decoding LCD control chip is connected to the liquid crystal display module 2. Signals input from the V, YPbPr, VGA, and HDMI interfaces are converted into RGB888 signals by the AV, YPbPr, VGA, and HDMI decoding chips, respectively, and then input to the AHD video decoding LCD control chip for outputting RGB888 signals to the LCD display module 2. Signals input from the SERDES interface are converted into BT.656 signals by the SERDES deserialization chip, and then input to the AHD video decoding LCD control chip for conversion into RGB888 signals for output to the LCD display module 2. Signals input from the AHD interface are decoded into RGB888 signals by the AHD video decoding LCD control chip for output to the LCD display module 2. This achieves precise conversion of different types of interface input signals, uniformly converting AV, YPbPr, VGA, HDMI, AHD, and SERDES signals into RGB888 signals recognizable by the LCD display module 2, ensuring stable video signal transmission and normal display, and adapting to multiple signal input formats, thus improving the system's versatility and compatibility.
[0037] Please see Figures 1 to 14Preferably, the MCU of the display control module 3 is connected and controlled via an I2C bus and GPIO port to the AV, YPBPR, VGA, and HDMI decoding chips, the SERDES deserialization chip, and the AHD video decoding LCD control chip, thereby enabling the switching of signal channels and screen pushing display of the LCD display module 2. The AV, YPBPR, VGA, and HDMI decoding chips include TSUMV56RUU and LT9211C. The signals input from AV, YPBPR, VGA, and HDMI are uniformly converted into LVDS signals by TSUMV56RUU and input to LT9211C. The LVDS signals are then converted into RGB888 signals by LT9211C and input to the AHD video decoding LCD control chip TP6891. This module employs a dedicated decoding chip processing architecture to achieve multi-format signal conversion and processing. For AV, YPbPr, VGA, and HDMI: it uses a decoding chip (TSUMV56RUU) with AV, YPbPr, VGA, and HDMI inputs and LVDS / RGB outputs, which is converted into RGB888 signals via LT9211C; for SERDES: it uses a DS90UB934 deserialization chip to convert LVDS signals into BT.656 digital signals for output to TP6891; for AHD: it uses TP6891 to directly decode and convert AHD signals and then push them to the screen display, simultaneously supporting input of RGB888 signals and BT.656 digital signals.
[0038] Please see Figures 1 to 14 Preferably, the YPbPr, HDMI, AV, VGA, SERDES, AHD, and AV interfaces are all connected to filtering modules. Each interface is connected to a filtering module, which can filter the input signals, remove noise and interference, improve signal purity, and thus enhance the display quality and stability of the display system.
[0039] Please see Figure 9Preferably, the HDMI interface filtering module includes multiple common-mode inductors, which are connected in series between the HDMI interfaces of the AV, YPbPr, VGA, and HDMI decoding chips. Four common-mode inductors, L11, L12, L13, and L14, are connected to the input side of the HDMI interface. This effectively suppresses common-mode interference in the HDMI interface signal, ensuring stable transmission of high-definition signals. The HDMI interface filtering module also includes transient suppression diodes TVS5-TVS10 connected to the input side of the HDMI interface. When the HDMI interface is subjected to electrostatic discharge (ESD) or a sudden high-voltage surge (such as electrical sparks when plugging or unplugging devices), the transient suppression diodes quickly conduct, clamping the excessive voltage within a safe range and directing the current to the ground terminal. This prevents high voltage from damaging subsequent decoding chips (such as TSUMV56RUU) or interface circuits, thereby protecting the stability of HDMI signal transmission and the lifespan of the interface. The HDMI interface filtering module also includes resistors R90 and R92 connected in series on the SCL (clock line) and SDA (data line) of the HDMI interface as current-limiting resistors. During I2C communication, these resistors limit the bus current, preventing damage to the MCU of the display control module 3 or the communication interface of the HDMI device due to excessive instantaneous current, thus ensuring the stability of the I2C bus communication. A transistor (MMBT3904M) is used to process the HPD signal when an external HDMI device is connected. This transistor amplifies the weak signal to a level that the display control module 3 can recognize, ensuring that the system can quickly detect the device connection status and trigger subsequent signal decoding and display processes, guaranteeing immediate responsiveness upon device connection.
[0040] Please see Figures 6 to 8 , Figure 10 , Figure 13 Preferably, the filtering module of the SERDES interface is a π-shaped filtering module (see...). Figure 10 The π-shaped filter module is connected to the input terminal of the SERDES interface. This π-shaped filter module consists of capacitors C188, C2146, C168, C189, C2147, C169, and inductor L2105, etc.; the filter module of the AV interface is a π-shaped filter module (see...). Figure 13 Its π-shaped filter module is connected between the input terminal of the AV interface and the AV input terminal of the AV, YPbPr, VGA, and HDMI decoding chips. The π-shaped filter module includes capacitors C133 and C134 and a ferrite bead FB14; the filter module of the AHD interface is a π-shaped filter module (see...). Figures 6 to 8The π-shaped filter module is connected between the input terminal of the AHD interface and the AHD input terminal of the AHD video decoding LCD control chip. The π-shaped filter module includes capacitors C2170 and C87, and a ferrite bead FB11. The π-shaped filter module effectively filters out differential-mode and common-mode interference in the SERDES, AV, and AHD interface signals, improving signal purity. In practical applications, the capacitor and inductor parameters of the π-shaped filter module can be adjusted according to the signal frequency of different interfaces to achieve the best filtering effect and meet the needs of different scenarios.
[0041] Please see Figure 11 Preferably, the filtering module of the YPBPR interface includes an EMI filtering module and a π-shaped filtering module. The EMI filtering module and the π-shaped filtering module are connected in series between the interface end of the YPBPR interface and the YPBPR interface of the AV, YPBPR, VGA, and HDMI decoding chips. The EMI filtering module consists of multiple common-mode inductors, such as differential-mode inductors L17, L18, and L19. The π-shaped filtering module includes ferrite beads (FB49, FB50, FB51) and capacitors (C467, C470, C471, C447, C448, and C449). Capacitor C447 is connected in parallel with resistor R148, capacitor C448 is connected in parallel with resistor R149, and capacitor C449 is connected in parallel with resistor R150. Through two-stage filtering, electromagnetic interference is first suppressed, and then differential-mode and common-mode interference are further filtered out, greatly improving the quality of the YPBPR interface signal. In practical applications, the number and parameters of common-mode inductors in EMI filter modules can be adjusted according to the complexity of the electromagnetic environment, and the component parameters of π-type filter modules can also be optimized according to signal characteristics to meet the needs of different scenarios.
[0042] Please see Figure 11Preferably, the input terminal of the YPBPR interface is also connected to a voltage clamping and DC-DC anti-static module. The voltage clamping and DC-DC anti-static module includes polarized capacitors connected in series to each pin of the YPBPR interface input side (such as polarized capacitor CE12+ connected to the first pin, polarized capacitor CE13+ connected to the second pin, polarized capacitor CE14+ connected to the third pin, polarized capacitor CE15+ connected to the fourth pin, polarized capacitor CE16+ connected to the fifth pin, and polarized capacitor CE17+ connected to the sixth pin). The two ends of the polarized capacitors are respectively connected to one end of a transient suppression diode, and the other end of the transient suppression diode is grounded. The positive terminal of the polarized capacitor is connected to the input terminal of the YPBPR interface, and the EMI filter module of the YPBPR interface is connected in series to the negative terminal of the polarized capacitor. Transient voltage suppressor diodes connected to the positive terminal (such as TVS22-TVS27) are used for voltage clamping, while those connected to the negative terminal are used for electrostatic discharge (ESD) protection (such as TVS55-TVS60). Polarized capacitors isolate DC current, thus achieving voltage clamping, DC isolation, and ESD protection for the YPBPR interface. This prevents damage to the interface due to abnormal voltage or ESD, improving its reliability and lifespan. In practical applications, the capacitance and voltage rating of the polarized capacitor can be selected based on the characteristics of the input signal, and the response speed and clamping voltage of the transient voltage suppressor diodes can be adjusted according to protection requirements to meet the needs of different scenarios.
[0043] Please see Figure 12 Preferably, the input side of the VGA interface is connected to an electrostatic discharge (ESD) protection and surge protection module. This module includes a transient voltage suppressor (VT) diode connected to one end of each pin of the VGA interface input side, with the other end of the VT diode grounded. A resistor is connected in parallel with each VT diode. This effectively prevents damage to the VGA interface from electrostatic discharge and surges, ensuring stable VGA signal input. In practical applications, the type of VT diode can be selected according to the protection level requirements, and the resistance value can be adjusted according to signal transmission needs to meet different scenario requirements.
[0044] Please see Figures 15 to 16Preferably, the outer surfaces of the connecting cables for the YPbPr, HDMI, AV, VGA, SERDES, AHD, and AV interfaces are sequentially wrapped with an aluminum foil layer 7, a braided mesh shielding layer 8, and a PVC layer 9. The aluminum foil layer 7 is made of single-sided aluminum foil with the conductive side facing outwards. This multi-layered shielding structure effectively shields against external electromagnetic interference, reduces signal loss and interference during transmission, and ensures the integrity and reliability of signal transmission, making it particularly suitable for the complex electromagnetic environment of automotive applications. The multi-layered shielding structure effectively blocks external electromagnetic interference, reduces signal transmission loss, and ensures the integrity of signal transmission. In practical applications, the aluminum foil layer 7 can be double-sided aluminum foil to enhance the shielding effect, the braiding density of the braided mesh shielding layer 8 can be adjusted according to shielding requirements, and the PVC layer can be made of materials resistant to high and low temperatures and aging to adapt to the automotive environment and meet the needs of different scenarios.
[0045] The working principle of this utility model is as follows:
[0046] When an external video signal is input through the corresponding interface of the multi-standard combination interface module 5 (such as YPbPr interface, HDMI interface, AV interface, AHD interface, RGB interface, SERDES interface, etc.), the signal first enters the corresponding interface circuit. For interfaces connected to filtering modules and protection modules, the signal will first be processed by these modules. For example, the filtering module removes noise and interference from the signal, and the protection module prevents damage to the interface and subsequent circuits caused by static electricity, surges, etc. At the same time, the multi-layer shielding structure of the connecting cable also plays an anti-interference role during signal transmission.
[0047] After initial processing, the signals enter the multi-format video signal conversion and processing module 6. Signals input from the AV, YPbPr, VGA, and HDMI interfaces are processed by the AV, YPbPr, VGA, and HDMI decoding chips, respectively. First, the TSUMV56RUU converts the signals into LVDS signals, then the LT9211C converts them into RGB888 signals, and finally the AHD video decoding LCD control chip TP6891. Signals from the SERDES interface are converted to BT.656 signals by the SERDES deserialization chip, then input to the AHD video decoding LCD control chip TP6891 for conversion into RGB888 signals. Signals from the AHD interface are directly decoded into RGB888 signals by the AHD video decoding LCD control chip TP6891.
[0048] The MCU of the display control module 3 controls the chips in the multi-format video signal conversion and processing module 6 via the I2C bus and GPIO ports to ensure that the signal conversion process is carried out in an orderly manner. After the conversion is completed, the AHD video decoding LCD control chip outputs the RGB888 signal to the LCD display module 2, and at the same time, the display driver module 4 drives the LCD display module 2 to work, ultimately achieving a clear display of the video signal.
[0049] Several points should be noted: First, in the description of this application, it should be noted that, unless otherwise specified and limited, the terms "installation", "connection" and "linkage" should be interpreted broadly, and can be mechanical or electrical connection, or internal connection between two components, or direct connection. "Up", "down", "left", "right", etc. are only used to indicate relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may change.
[0050] Secondly: The accompanying drawings of the embodiments disclosed in this utility model only involve the structures involved in the embodiments disclosed in this utility model. Other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of this utility model can be combined with each other.
[0051] Finally, the above description is only a preferred embodiment of the present utility model. The protection scope of the present utility model is not limited to the above embodiments. All technical solutions that fall within the scope of the present utility model are protected by the present utility model.
[0052] It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of this utility model should also be considered within the scope of protection of this utility model.
Claims
1. A display system supporting multiple video format access, comprising a power supply module, a liquid crystal display module, a display control module, and a display driver module, wherein the power supply module is electrically connected to the liquid crystal display module, the display control module, and the display driver module, characterized in that: It also includes a multi-standard interface module and a multi-standard video signal conversion and processing module. The power supply module is electrically connected to the multi-standard interface module and the multi-standard video signal conversion and processing module. The multi-standard interface module is communicatively connected to the multi-standard video signal conversion and processing module. The multi-standard video signal conversion and processing module is communicatively connected to the display control module and the liquid crystal display module. The multi-standard video signal conversion and processing module converts the signal input by the multi-standard interface module into a signal that the liquid crystal display module can recognize.
2. The display system supporting multiple video format access according to claim 1, characterized in that: The multi-standard interface module has YPbPr, HDMI, AV, VGA, SERDES, and AHD interfaces. The multi-standard video signal conversion and processing module includes AV, YPbPr, VGA, and HDMI decoding chips and SERDES deserialization chips, as well as an AHD video decoding LCD control chip. The outputs of the AV, YPbPr, VGA, and HDMI decoding chips and the SERDES deserialization chip are connected to the input of the AHD video decoding LCD control chip, and the output of the AHD video decoding LCD control chip is connected to the LCD display module. Signals input from the AV, YPbPr, VGA, and HDMI interfaces are converted into RGB888 signals by the AV, YPbPr, VGA, and HDMI decoding chips, and then input to the AHD video decoding LCD control chip to output RGB888 signals to the LCD display module. Signals input from the SERDES interface are converted into BT.656 signals by the SERDES deserialization chip, and then input to the AHD video decoding LCD control chip to be converted into RGB888 signals for output to the LCD display module. Signals input from the AHD interface are decoded into RGB888 signals by the AHD video decoding LCD control chip and output to the LCD display module.
3. A display system supporting multiple video format access according to claim 2, characterized in that: The MCU of the display control module is connected and controlled by the AV, YPBPR, VGA, and HDMI decoding chips, the SERDES deserialization chip, and the AHD video decoding LCD control chip via an I2C bus and GPIO ports. The AV, YPBPR, VGA, and HDMI decoding chips include TSUMV56RUU and LT9211C. The signals input from AV, YPBPR, VGA, and HDMI are uniformly converted into LVDS signals by TSUMV56RUU and input to LT9211C. The LVDS signals are then converted into RGB888 signals by LT9211C and input to the AHD video decoding LCD control chip.
4. A display system supporting multiple video format access according to claim 2, characterized in that: The YPbPr, HDMI, AV, VGA, SERDES, AHD, and AV interfaces are all connected to filtering modules.
5. A display system supporting multiple video format access according to claim 4, characterized in that: The filtering module of the HDMI interface includes multiple common-mode inductors, which are connected in series between the HDMI interfaces of the AV, YPbPr, VGA, and HDMI decoding chips.
6. A display system supporting multiple video format access according to claim 4, characterized in that: The filtering module of the SERDES interface is a π-shaped filtering module, which is connected to the input terminal of the SERDES interface. The filtering module of the AV interface is a π-shaped filtering module, which is connected between the input terminal of the AV interface and the AV input terminal of the AV, YPbPr, VGA, and HDMI decoding chips. The filtering module of the AHD interface is a π-shaped filtering module, which is connected between the input terminal of the AHD interface and the AHD input terminal of the AHD video decoding LCD control chip.
7. A display system supporting multiple video format access according to claim 4, characterized in that: The filtering module of the YPBPR interface includes an EMI filtering module and a π-shaped filtering module. The EMI filtering module and the π-shaped filtering module are connected in series between the interface end of the YPBPR interface and the YPBPR interface of the AV, YPBPR, VGA and HDMI decoding chips. The EMI filtering module is composed of multiple common mode inductors, and the π-shaped filtering module includes a ferrite bead and a capacitor.
8. A display system supporting multiple video format access according to claim 7, characterized in that: The input terminal of the YPBPR interface is also connected to a voltage clamping and DC-DC anti-static module. The voltage clamping and DC-DC anti-static module includes a polarized capacitor connected in series to each pin of the YPBPR interface input side. The two ends of the polarized capacitor are respectively connected to one end of a transient suppression diode, and the other end of the transient suppression diode is grounded. The positive terminal of the polarized capacitor is connected to the input terminal of the YPBPR interface, and the EMI filter module of the YPBPR interface is connected in series to the negative terminal of the polarized capacitor.
9. A display system supporting multiple video format access according to claim 4, characterized in that: The input side of the VGA interface is connected to an electrostatic discharge (ESD) protection and surge protection module. The ESD protection and surge protection module includes a transient suppression diode connected to one end of each pin of the VGA interface input side, the other end of the transient suppression diode being grounded, and a resistor connected in parallel to each transient suppression diode.
10. A display system supporting multiple video format access according to claim 2, characterized in that: The outer surface of the connecting cables for YPBPR, HDMI, AV, VGA, SERDES, AHD, and AV interfaces is sequentially wrapped with an aluminum foil layer, a braided mesh shielding layer, and a PVC layer; the aluminum foil layer is made of single-sided aluminum foil with the conductive side facing outwards.