System for realizing long-distance transmission of MIPI-CPHY image signal
By using a long-distance transmission system for SerDes signals, parallel data is converted into C-PHY signals using the Serializer and Deserializer modules, solving the problem of signal attenuation of MIPI-CPHY image signals during long-distance transmission and achieving high-quality image signal transmission and detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHANGSHA SEICHI ELECTRONIC TECHNOLOGIES CO LTD
- Filing Date
- 2025-08-21
- Publication Date
- 2026-07-21
AI Technical Summary
During long-distance transmission, MIPI-CPHY image signals are susceptible to signal attenuation, leading to a decrease in signal quality and affecting the accuracy and stability of detection.
The SerDes signal is output by the signal generator unit. The parallel data is converted into a serial signal by the serializer module. The deserializer module on the baseboard unit converts the SerDes signal into a C-PHY signal. The signal is then processed by the FPGA and bridge chip of the core board unit to achieve long-distance signal transmission.
It improves signal transmission distance and anti-interference capability, reduces the number of signal lines, maintains the integrity and accuracy of high-speed signals, adapts to different types of display screens, and improves detection accuracy and stability.
Smart Images
Figure CN224538240U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of image processing technology, and in particular to a system for long-distance transmission of MIPI-CPHY image signals. Background Technology
[0002] In the fields of digital communications, integrated circuit design, and high-speed signal transmission, MIPI is a widely used interface standard for connecting processors or FPGAs in mobile devices to peripherals. C-PHY is a physical layer interface in the MIPI standard used to connect cameras or displays.
[0003] With the continuous iteration of panel display technology, the refresh rate and resolution of display panels in the panel testing field are getting higher and higher, thus requiring higher image signal rates. To improve signal integrity and ensure test accuracy during product testing, the signal quality requirements after high-speed signals have undergone multiple jumpers are becoming increasingly stringent. For commonly used high-speed MIPI-CPHY signals (such as those used in mobile phone OLED panels), the signal is transmitted in a single-ended manner, and long transmission distances can cause signal attenuation.
[0004] In existing technologies, there is an urgent need to solve the problem of maintaining high-quality signals during long-distance transmission. Utility Model Content
[0005] This application provides a system for long-distance transmission of MIPI-CPHY image signals, which can realize the long-distance transmission of MIPI-CPHY image signals.
[0006] This application provides a system for long-distance transmission of MIPI-CPHY image signals, comprising a signal generator unit, a base plate unit, and a screen unit. The signal generator unit is connected to the base plate unit, and the base plate unit is connected to the screen unit. The signal generator unit is provided with a serializer module, and the base plate unit is provided with a deserializer module that matches the serializer module. The signal generator unit is used to output a SerDes signal. The base plate unit is used to receive the SerDes signal output by the signal generator unit, and the base plate unit is used to convert the SerDes signal into a C-PHY signal and output it to the screen unit.
[0007] Optionally, a core board unit is provided on the base plate unit, the core board unit is connected to the base plate unit, the Deserializer module is disposed on the core board unit, and the core board unit is used to receive SerDes signals from the base plate unit, convert the SerDes signals into C-PHY signals, and input the C-PHY signals into the base plate unit.
[0008] Optionally, the core board unit includes an FPGA and a bridge chip; the FPGA is connected to the bridge chip, and the FPGA is used to receive SerDes signals from the Deserializer module and convert the SerDes signals into serial / parallel data; the bridge chip is used to receive serial / parallel data from the FPGA, convert the serial / parallel data into C-PHY signals, and input the C-PHY signals into the baseboard unit.
[0009] Optionally, the Serializer module includes four consistent differential drive circuits, and the Deserializer module includes a CDR circuit and four differential receiver circuits matched with the differential drive circuits. The CDR circuit is used to provide a clock signal to the FPGA.
[0010] Optionally, each differential drive circuit includes MOSFETs Q1-Q4, resistors R1-R2, multiplexers mux1-mux2, a Sel signal, a current source Irange1, and a power supply voltage VDD1; the power supply voltage VDD1 is connected to the source of MOSFET Q1 and the source of MOSFET Q2; the Sel signal is connected to the input terminals of multiplexers mux1 and mux2 respectively; the output terminal of multiplexer mux1 is connected to the gate of MOSFET Q1 and the gate of MOSFET Q2; the drain of MOSFET Q1 is connected to resistor R... The first end of resistor R1 is connected to the drain of MOSFET Q3, and a differential signal output terminal TX_P is led out. The drain of MOSFET Q2 is connected to the first end of resistor R2, and the second end of resistor R2 is connected to the drain of MOSFET Q4, and a differential signal output terminal TX_N is led out. The sources of MOSFET Q3 and MOSFET Q4 are connected to the output terminal of current source Irange1. The ground terminal of current source Irange1 is grounded, and the output terminal of multiplexer mux2 is connected to the control terminal of current source Irange1.
[0011] Optionally, each differential receiver circuit includes MOSFETs Q5-Q8, resistors R3-R4, multiplexers mux3-mux4, a Sel2 signal, a current source Irange2, and a power supply voltage VDD2. VDD2 is connected to the sources of MOSFETs Q5 and Q6. The Sel2 signal is connected to the inputs of multiplexers mux3 and mux4, respectively. The output of multiplexer mux3 is connected to the gates of MOSFETs Q5 and Q6. The differential signal receiver RX_N is connected to the gate of MOSFET Q7, and is used to connect to the differential signal output TX_N. The receiving terminal RX_P is connected to the gate of MOSFET Q8, and the differential signal receiving terminal RX_P is used to connect to the differential signal output terminal TX_P; the drain of MOSFET Q5 is connected to the first end of resistor R3, and the second end of resistor R3 is connected to the drain of MOSFET Q7; the drain of MOSFET Q6 is connected to the first end of resistor R4, and the second end of resistor R4 is connected to the drain of MOSFET Q8; the sources of MOSFET Q7 and MOSFET Q8 are connected to the output terminal of current source Irange2, the ground terminal of current source Irange2 is connected to ground, and the output terminal of multiplexer mux4 is connected to the control terminal of current source Irange2.
[0012] Optionally, the core board unit is connected to the baseboard unit via a BIB connector; or, the core board unit is soldered to the baseboard unit via a QFN package.
[0013] Optionally, the signal generator unit includes an inline mode and an offline mode.
[0014] Optionally, when the signal generator unit uses inline mode, the signal generator unit is connected to the base plate unit via a pin die or pogo-pin crimping method.
[0015] Optionally, when the signal generator unit uses offline mode, the signal generator unit is connected to the base plate unit via a high-speed connector.
[0016] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:
[0017] 1. Improve signal transmission distance and anti-interference capability. Since the signal generator unit outputs a SerDes differential signal, differential transmission is less dependent on the ground wire than single-ended transmission and has a stronger ability to suppress common-mode interference. Therefore, it can maintain signal quality and reduce bit error rate during long-distance transmission.
[0018] 2. Reduce the number of signal lines and simplify wiring design. By converting parallel data into serial signals for transmission using the Serializer module, the number of signal lines is significantly reduced compared to directly transmitting parallel signals, which helps to reduce wiring complexity and interconnection costs.
[0019] 3. Maintain the integrity of high-speed signals. SerDes signals have excellent spectral characteristics, which can effectively reduce signal reflection and distortion under high-speed transmission, thereby ensuring the quality of the signal waveform received by the backplane unit.
[0020] 4. Facilitates connection with different types of display screens. The base unit can convert the received SerDes signal into a C-PHY signal output, enabling the system to be directly compatible with display screens using the MIPI C-PHY interface, reducing the need for additional adapter modules.
[0021] 5. Improved accuracy and stability of detection. Since the conversion from SerDes to C-PHY is completed at the base unit, the screen unit receives a standard C-PHY signal, thereby improving the accuracy of signal analysis during panel detection and reducing misjudgments caused by signal distortion. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of a system for long-distance transmission of MIPI-CPHY image signals in an embodiment of this application;
[0023] Figure 2 This is a schematic diagram of the structure of the signal generator unit and the core board unit in an embodiment of this application;
[0024] Figure 3 This is another schematic diagram of the system structure for long-distance transmission of MIPI-CPHY image signals in this application embodiment;
[0025] Figure 4 This is a structural schematic diagram of a base plate unit in an embodiment of this application;
[0026] Figure 5 This is a schematic diagram of another structure of the base plate unit in the embodiments of this application;
[0027] Figure 6 This is a schematic diagram of a core board unit in an embodiment of this application. Detailed Implementation
[0028] In this application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and other terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used to describe the relative positional relationship between the components or parts and do not specifically limit the specific installation orientation of each component or part.
[0029] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.
[0030] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.
[0031] Furthermore, the structures, proportions, sizes, etc., drawn in the accompanying drawings of this application are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modification to the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.
[0032] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0033] Please see Figures 1 to 6 One embodiment of the system for long-distance transmission of MIPI-CPHY image signals in this application includes:
[0034] The system comprises a signal generator unit, a base plate unit 2, and a screen unit 3. The signal generator unit is connected to the base plate unit 2, and the base plate unit 2 is connected to the screen unit 3. The signal generator unit is equipped with a serializer module, and the base plate unit 2 is equipped with a deserializer module that matches the serializer module. The signal generator unit is used to output SerDes signals. The base plate unit 2 is used to receive the SerDes signals output by the signal generator unit and to convert the SerDes signals into C-PHY signals and output them to the screen unit 3.
[0035] The signal generator unit converts parallel data from video sources or image processing chips into high-speed serial signals. Serialization refers to the process of compressing multiple parallel data streams into single or multiple high-speed serial signals according to certain timing rules, which can significantly reduce the number of physical lines and improve signal transmission bandwidth efficiency. SerDes (Serializer / Deserializer) is a widely used technology in high-speed data communication, which can realize the mutual conversion between parallel and serial signals, and has the ability to resist interference and reduce clock skew. The Deserializer module of the base unit 2 can receive and parse the SerDes signal, restore the serial signal to parallel data, and then convert the parallel data into a signal format conforming to the MIPI C-PHY standard through internal circuitry. C-PHY is a new high-speed data transmission interface standard that achieves higher data transmission rates with fewer differential line channels through multi-phase coding technology (usually three-phase coding), suitable for the image transmission requirements of high-resolution, high-refresh-rate displays. The screen unit 3 receives and decodes signals through its C-PHY interface to drive the display screen and achieve high-quality image display.
[0036] In this embodiment, using SerDes signals for long-distance transmission maintains signal integrity and timing stability even with long physical connections, effectively reducing the risk of data errors caused by signal attenuation and noise interference. The baseboard unit 2 parses and converts the received high-speed SerDes signal, ensuring that the final output C-PHY signal conforms to the display panel interface standard while maintaining data integrity and high transmission rate, thus achieving stability and reliability of image signals during long-distance transmission. In this way, the entire device can significantly improve the reliability and stability of long-distance image transmission while maintaining high-resolution, high-refresh-rate image transmission requirements, and adapt to the needs of different display devices and application scenarios.
[0037] Optionally, a core board unit 4 is provided on the base plate unit 2. The core board unit 4 is connected to the base plate unit 2. The Deserializer module is provided on the core board unit 4. The core board unit 4 is used to receive the SerDes signal from the base plate unit 2, convert the SerDes signal into a C-PHY signal, and input the C-PHY signal into the base plate unit 2.
[0038] A core board unit 4 is mounted on the baseboard unit 2, and the core board unit 4 is connected to the baseboard unit 2. The deserializer module is mounted on the core board unit 4. The core board unit 4 receives the SerDes signal transmitted from the baseboard unit 2, parses the high-speed serial signal, restores it to parallel data, converts it into a signal format conforming to the MIPI C-PHY standard, and then returns the generated C-PHY signal to the baseboard unit 2, from which it is output to the screen unit 3. By integrating the deserializer module and the C-PHY signal generation module onto the core board unit 4, signal processing can be centralized and modularized, facilitating subsequent system expansion and upgrades, while maintaining high bandwidth, high stability, and low bit error rate during signal conversion. The core board unit 4 allows the baseboard unit 2 to focus on interface management and signal distribution, improving the overall reliability and flexibility of the system, and helping to maintain the integrity of the C-PHY signal and the stability of the display effect in complex wiring or long-distance transmission scenarios.
[0039] In this embodiment, by integrating a Deserializer module on the core board unit 4 and performing SerDes to C-PHY conversion, the system can maintain high signal integrity and low bit error rate under long-distance transmission conditions, while reducing the signal processing load of the baseboard unit 2, so that the image data received by the screen unit 3 can maintain high quality and stability, thereby realizing reliable transmission for long-distance high-resolution image display.
[0040] Optionally, core board unit 4 includes FPGA 41 and bridge chip 42. FPGA 41 is connected to bridge chip 42. FPGA 41 is used to receive SerDes signals from the Deserializer module and convert the SerDes signals into serial / parallel data. Bridge chip 42 is used to receive serial / parallel data from FPGA 41, convert the serial / parallel data into C-PHY signals, and input the C-PHY signals into baseboard unit 2.
[0041] The core board unit 4 includes an FPGA 41 and a bridge chip 42. The FPGA 41 is connected to the bridge chip 42. The FPGA 41 receives SerDes signals from the Deserializer module and converts them into serial or parallel data. The bridge chip 42 receives serial / parallel data from the FPGA 41, converts it into a signal conforming to the MIPI C-PHY standard, and inputs the C-PHY signal to the baseboard unit 2. Through the processing of the FPGA 41, the system can flexibly parse and process high-speed SerDes signals, including signal retiming, data reconstruction, and necessary signal conditioning operations. The bridge chip 42 further completes the conversion of serial / parallel data to C-PHY signals, ensuring that the output signal can match the interface standard of the screen unit 3, guaranteeing data integrity and high-quality transmission. This structure, through the collaborative work of the FPGA 41 and the bridge chip 42, enables the core board unit 4 to efficiently handle complex signal conversion tasks, while reducing the processing load of the baseboard unit 2 and improving the overall stability and reliability of the system.
[0042] In this embodiment, by introducing FPGA41 and bridge chip42 in the core board unit 4 to collaboratively process the conversion between SerDes signal and C-PHY signal, the system can maintain high signal integrity, low bit error rate and high bandwidth characteristics under long-distance transmission conditions, ensuring that the image data received by the screen unit 3 has stable timing and high-quality display effect, thereby realizing the reliability and stability of long-distance, high-resolution image transmission.
[0043] Optionally, the Serializer module includes four consistent differential drive circuits, and the Deserializer module includes a CDR circuit and four differential receiver circuits matched with the differential drive circuits. The CDR circuit is used to provide clock signals to the FPGA41.
[0044] The core board unit 4 includes an FPGA 41 and a bridge chip 42, which are connected. The FPGA 41 receives SerDes signals from the Deserializer module and converts them into serial or parallel data. The bridge chip 42 receives serial / parallel data from the FPGA 41, converts it into a signal conforming to the MIPI C-PHY standard, and inputs the C-PHY signal to the backplane unit 2. The FPGA 41 can flexibly parse and process high-speed SerDes signals, including signal retiming and data reconstruction, while the bridge chip 42 is responsible for converting the processed data into a C-PHY signal output, ensuring that the signal matches the interface standard of the screen unit 3. This structure, through the collaborative work of the FPGA 41 and the bridge chip 42, enables the core board unit 4 to efficiently handle signal conversion tasks, while reducing the processing load of the backplane unit 2, thus improving the overall processing efficiency and stability of the system.
[0045] In this embodiment, the SerDes signal is parsed and converted by FPGA41 and bridge chip42, enabling the system to maintain signal integrity and low bit error rate under long-distance transmission conditions, while ensuring high bandwidth and high stability of C-PHY signal output. This achieves stable, reliable, and high-quality display of image data received by screen unit 3, and improves the overall long-distance image transmission capability of the system.
[0046] Optionally, each differential drive circuit includes MOSFETs Q1-Q4, resistors R1-R2, multiplexers mux1-mux2, a Sel signal, a current source Irange1, and a power supply voltage VDD1. The power supply voltage VDD1 is connected to the sources of MOSFETs Q1 and Q2. The Sel signal is connected to the inputs of multiplexers mux1 and mux2, respectively. The output of multiplexer mux1 is connected to the gates of MOSFETs Q1 and Q2. The drain of MOSFET Q1 is connected to the first end of resistor R1, and the second end of resistor R1 is connected to the drain of MOSFET Q3, providing a differential signal output terminal TX_P. The drain of MOSFET Q2 is connected to the first end of resistor R2, and the second end of resistor R2 is connected to the drain of MOSFET Q4, providing a differential signal output terminal TX_N. The sources of MOSFETs Q3 and Q4 are connected to the output of the current source Irange1. The grounding terminal of current source Irange1 is grounded, and the output terminal of multiplexer mux2 is connected to the control terminal of current source Irange1.
[0047] Each differential drive circuit includes MOSFETs Q1-Q4, resistors R1-R2, multiplexers mux1-mux2, a Sel signal, a current source Irange1, and a power supply voltage VDD1. The power supply voltage VDD1 is connected to the sources of MOSFETs Q1 and Q2, providing a stable operating voltage for the differential drive circuit. The Sel signal is connected to the inputs of multiplexers mux1 and mux2, used to control the operating mode and signal path selection of the differential drive circuit. The output of multiplexer mux1 is connected to the gates of MOSFETs Q1 and Q2, allowing flexible control of the drive terminals by selecting the input signal path. The drain of MOSFET Q1 is connected to the drain of MOSFET Q3 through resistor R1, and a differential signal output terminal TX_P is provided; the drain of MOSFET Q2 is connected to the drain of MOSFET Q4 through resistor R2, and a differential signal output terminal TX_N is provided. The sources of MOSFETs Q3 and Q4 are connected to the output of current source Irange1, which is grounded. The output of multiplexer mux2 is connected to the control terminal of current source Irange1 to achieve dynamic adjustment of the output current. Through the combination of resistors, current sources, and MOSFETs, the differential drive circuit can simultaneously generate matched drive current and voltage swing at the positive and negative terminals, thus ensuring high linearity and symmetry of the output signal. It should be noted that resistors R1 and R2 have the same resistance value. Furthermore, the parameters of MOSFETs Q3 and Q4 are symmetrical.
[0048] The differential drive circuit enables the generation and driving of high-speed differential signals. MOSFETs Q1-Q4 are responsible for switching and current transfer in the drive signal path, respectively. Resistors R1-R2 provide necessary voltage distribution and impedance matching, ensuring symmetrical voltage amplitude and phase at the differential signal outputs TX_P and TX_N. The cooperation of the Sel signal and multiplexers mux1-mux2 allows for flexible selection of different input paths and current magnitudes, enabling various operating modes, such as optimized driving under different signal rates or transmission conditions. Current source Irange1 works in conjunction with MOSFETs Q3 and Q4 to achieve precise control of the output current, thereby stabilizing the drive to the load and reducing signal distortion caused by cable or load variations. The overall structure achieves high-efficiency differential signal driving by separating the drive and current control paths, while providing flexible adjustment capabilities to adapt to different transmission environments.
[0049] In this embodiment, the differential drive circuit structure and functional division enable the system to output a differential signal with high linearity, high symmetry and stability. At the same time, it has the ability to flexibly control the current and signal path, effectively enhancing the anti-interference performance and transmission reliability of the signal. Especially in the long-distance high-speed signal transmission environment, it can ensure the integrity and stability of the differential signal, thereby improving the overall system signal quality and long-distance transmission performance.
[0050] Optionally, each differential receiver circuit includes MOSFETs Q5-Q8, resistors R3-R4, multiplexers mux3-mux4, a Sel2 signal, a current source Irange2, and a power supply voltage VDD2. VDD2 is connected to the sources of MOSFETs Q5 and Q6. The Sel2 signal is connected to the inputs of multiplexers mux3 and mux4, respectively. The output of multiplexer mux3 is connected to the gates of MOSFETs Q5 and Q6. The differential signal receiver RX_N is connected to the gate of MOSFET Q7 and is used to connect to the differential signal output TX_N. The differential signal receiver RX_P is connected to the gate of MOSFET Q8 and is used to connect to the differential signal output TX_P. The drain of MOSFET Q5 is connected to the first end of resistor R3, and the second end of resistor R3 is connected to the drain of MOSFET Q7. The drain of MOSFET Q6 is connected to the first terminal of resistor R4, and the second terminal of resistor R4 is connected to the drain of MOSFET Q8. The sources of MOSFETs Q7 and Q8 are connected to the output of current source Irange2. The ground terminal of current source Irange2 is connected to ground, and the output of multiplexer mux4 is connected to the control terminal of current source Irange2.
[0051] Each differential receiver circuit includes MOSFETs Q5-Q8, resistors R3-R4, multiplexers mux3-mux4, a Sel2 signal, a current source Irange2, and a power supply voltage VDD2. The power supply voltage VDD2 is connected to the sources of MOSFETs Q5 and Q6, providing a stable operating voltage for the differential receiver circuit. The Sel2 signal is connected to the inputs of multiplexers mux3 and mux4, used to control the operating mode and signal path selection of the receiving path. The output of multiplexer mux3 is connected to the gates of MOSFETs Q5 and Q6, enabling flexible control of the differential signal receiver by selecting the input signal path. The differential signal receiver terminals RX_P and RX_N are connected to the gates of MOSFETs Q8 and Q7, respectively, for connection to the differential signal output terminals TX_P and TX_N, realizing the reception of differential signals. The drain of MOSFET Q5 is connected to the drain of MOSFET Q7 through resistor R3, and the drain of MOSFET Q6 is connected to the drain of MOSFET Q8 through resistor R4. The sources of MOSFETs Q7 and Q8 are connected to the output of current source Irange2, which is grounded. The output of multiplexer mux4 is connected to the control terminal of current source Irange2, enabling the regulation and control of the received current. This structure, through the combination of MOSFETs, resistors, multiplexers, and current sources, can accurately receive and amplify the input differential signal, providing a stable and reliable signal foundation for subsequent signal processing.
[0052] The differential receiver circuit can receive high-speed differential signals and ensure signal integrity. MOSFETs Q5-Q6 are responsible for signal amplification and path control at the receiving end, while MOSFETs Q7-Q8 work with the current source to form a symmetrical differential output. Resistors R3-R4 are used for voltage distribution and impedance matching to ensure the amplitude and phase symmetry of the differential signal at the receiving end. The Sel2 signal, in conjunction with multiplexers mux3-mux4, allows for flexible selection of different input paths and current modes, enabling multiple operating modes at the receiving end to adapt to different signal rates and transmission conditions. The current source Irange2 works in conjunction with MOSFETs Q7-Q8 to achieve precise control of the current at the receiving end, improving the consistency and stability of signal amplification. The overall structure achieves high-efficiency, high-linearity differential signal reception by separating the signal control and current drive paths.
[0053] By combining MOSFETs, multiplexers, resistors, and current sources in the differential receiver circuit, accurate reception and robust amplification of high-speed differential signals are achieved. This enables the system to maintain signal integrity, low distortion, and high linearity under long-distance transmission conditions. At the same time, flexible adjustment is achieved through the Sel2 signal and mux control, which improves the receiver's ability to suppress signal interference and the overall system stability. This ensures that subsequent processing and display units can acquire high-quality differential signals, achieving reliability and stability for long-distance high-speed image transmission.
[0054] Optionally, core board unit 4 is connected to baseboard unit 2 via a BIB connector. Alternatively, core board unit 4 is soldered to baseboard unit 2 via a QFN package.
[0055] Signal and power transmission are achieved through a fixed connection between the core board unit 4 and the baseboard unit 2. This connection can be achieved using either a BIB connector or a QFN package. The BIB (Board-In-Board) connector provides a high-density, multi-pin pluggable interface, enabling a detachable connection between the core board unit 4 and the baseboard unit 2, facilitating rapid installation, disassembly, or modular upgrades. The QFN (Quad Flat No-lead) package offers low lead inductance and a compact soldering method, suitable for space-constrained scenarios or those requiring high-density integration. These two different connection methods allow the system to flexibly select the appropriate method based on the specific installation environment or maintenance requirements, enabling diverse configurations for the connection between the core board unit 4 and the baseboard unit 2.
[0056] In this embodiment, BIB connectors or QFN packages are used to achieve diverse connection methods between the core board unit 4 and the baseboard unit 2, making the system more flexible in installation, maintenance, and modular design. The pluggable nature of BIB connectors improves the convenience of system debugging and upgrades, while QFN packages are suitable for compact layout requirements, enabling the system to quickly adapt to different application scenarios, achieving flexible selection of installation methods and structural layouts, while ensuring the stability of high-speed signal transmission.
[0057] Optionally, the signal generator unit includes inline mode and offline mode.
[0058] Optionally, when the signal generator unit uses inline mode, the signal generator unit is connected to the base plate unit 2 via a pin die or pogo-pin crimping method.
[0059] Optionally, when the signal generator unit is in offline mode, the signal generator unit is connected to the base plate unit 2 via a high-speed connector.
[0060] The signal generator unit includes both inline and offline operating modes to accommodate different system connection and installation requirements.
[0061] When the signal generator unit is used in inline mode, it is connected to the base plate unit 2 via pin die or pogo-pin crimping. This method provides low impedance and stable electrical contact, is suitable for short-distance or fixed installation scenarios, facilitates quick installation and disassembly, and is convenient for on-site debugging and maintenance.
[0062] When the signal generator unit is in offline mode, it is connected to the baseboard unit 2 via a high-speed connector. The high-speed connector supports the transmission of high-bandwidth SerDes signals and has good anti-interference capabilities and pluggability, making it suitable for applications where the signal generator unit and the baseboard unit 2 are physically independent or require flexible combination.
[0063] In this embodiment, by providing both inline and offline connection modes, the system can flexibly select the connection method between the signal generator unit and the base plate unit 2 according to different installation environments, spatial layouts, and maintenance requirements. The inline mode improves the convenience and debugging efficiency of short-distance fixed installation, while the offline mode provides modularity and pluggable flexibility to meet the high-speed signal transmission requirements under different physical layout conditions, thereby enhancing the overall adaptability and deployment flexibility of the system.
[0064] It should be noted that the above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A system for long-distance transmission of MIPI-CPHY image signals, characterized in that, include: The system includes a signal generator unit, a base plate unit, and a screen unit, wherein the signal generator unit is connected to the base plate unit, and the base plate unit is connected to the screen unit. The signal generator unit is equipped with a serializer module, and the base plate unit is equipped with a deserializer module that matches the serializer module; The signal generator unit is used to output a SerDes signal; the base plate unit is used to receive the SerDes signal output by the signal generator unit, and the base plate unit is used to convert the SerDes signal into a C-PHY signal and output it to the screen unit.
2. The system according to claim 1, characterized in that, A core board unit is provided on the base plate unit and is connected to the base plate unit. The Deserializer module is disposed on the core board unit. The core board unit is used to receive SerDes signals from the base plate unit, convert the SerDes signals into C-PHY signals, and input the C-PHY signals into the base plate unit.
3. The system according to claim 2, characterized in that, The core board unit includes an FPGA and a bridge chip; The FPGA is connected to the bridge chip, and the FPGA is used to receive the SerDes signal from the Deserializer module and convert the SerDes signal into serial / parallel data. The bridge chip is used to receive serial / parallel data from the FPGA, convert the serial / parallel data into C-PHY signals, and input the C-PHY signals into the baseboard unit.
4. The system according to claim 3, characterized in that, The serializer module includes four consistent differential drive circuits, and the deserializer module includes a CDR circuit and four differential receiver circuits matched with the differential drive circuits. The CDR circuit is used to provide a clock signal for the FPGA.
5. The system according to claim 4, characterized in that, Each differential drive circuit includes MOSFETs Q1-Q4, resistors R1-R2, multiplexers mux1-mux2, Sel signal, current source Irange1, and power supply voltage VDD1; The power supply voltage VDD1 is connected to the source of MOSFET Q1 and the source of MOSFET Q2; the Sel signal is connected to the input terminals of multiplexers mux1 and mux2 respectively; the output terminal of multiplexer mux1 is connected to the gate of MOSFET Q1 and the gate of MOSFET Q2; the drain of MOSFET Q1 is connected to the first end of resistor R1, the second end of resistor R1 is connected to the drain of MOSFET Q3 and leads out the differential signal output terminal TX_P; the drain of MOSFET Q2 is connected to the first end of resistor R2, the second end of resistor R2 is connected to the drain of MOSFET Q4 and leads out the differential signal output terminal TX_N; the sources of MOSFET Q3 and MOSFET Q4 are connected to the output terminal of current source Irange1; the ground terminal of current source Irange1 is grounded, and the output terminal of multiplexer mux2 is connected to the control terminal of current source Irange1.
6. The system according to claim 5, characterized in that, Each differential receiver circuit includes MOSFETs Q5-Q8, resistors R3-R4, multiplexers mux3-mux4, Sel2 signal, current source Irange2, and power supply voltage VDD2. VDD2 is connected to the source of MOSFET Q5 and the source of MOSFET Q6. The Sel2 signal is connected to the inputs of multiplexer mux3 and multiplexer mux4, respectively. The output of multiplexer mux3 is connected to the gates of MOSFET Q5 and MOSFET Q6. The differential signal receiver RX_N is connected to the gate of MOSFET Q7 and is used to connect to the differential signal output TX_N. The differential signal receiver RX_P is connected to the gate of MOSFET Q8 and is used to connect to the differential signal output TX_N. The signal output terminal TX_P is connected; the drain of the MOSFET Q5 is connected to the first end of the resistor R3, and the second end of the resistor R3 is connected to the drain of the MOSFET Q7; the drain of the MOSFET Q6 is connected to the first end of the resistor R4, and the second end of the resistor R4 is connected to the drain of the MOSFET Q8; the sources of the MOSFET Q7 and the MOSFET Q8 are connected to the output terminal of the current source Irange2, the ground terminal of the current source Irange2 is connected to ground, and the output terminal of the multiplexer mux4 is connected to the control terminal of the current source Irange2.
7. The system according to any one of claims 2 to 6, characterized in that, The core board unit is connected to the base plate unit via a BIB connector; Alternatively, the core board unit can be soldered to the base plate unit via a QFN package.
8. The system according to any one of claims 1 to 6, characterized in that, The signal generator unit includes inline mode and offline mode.
9. The system according to claim 8, characterized in that, When the signal generator unit uses inline mode, the signal generator unit is connected to the base plate unit via a pin die or pogo-pin crimping method.
10. The system according to claim 8, characterized in that, When the signal generator unit is in offline mode, it is connected to the base plate unit via a high-speed connector.