Impedance control printed circuit board for ai server

Abstract

The utility model relates to an impedance control printed wiring board for AI server, including the multilayer stack structure formed by three times of pressing, three times of pressing add core board layer in proper order from inside to outside, at least contain two pre-solidified core board layer in each pressing, the core board layer keeps solidified state and the dielectric layer thickness is invariable in the pressing process, and the adjacent core board layer is pressed through the semi-solid sheet, vertical line is set between the core board layer, and the vertical line is the copper column structure formed through the graphic electroplating process, at least one group of high speed signal line is arranged in the core board layer, and the adjacent layer on both sides of high speed signal line is the ground layer, in the combination of core board layer and semi-solid sheet, the dielectric layer thickness of core board layer is the main reference layer of impedance control, the utility model provides an impedance control printed wiring board for AI server, reduces high speed signal distortion through three times of pressing process and copper column interconnection technology, has the advantages such as high interlayer alignment precision, good impedance consistency.

Description

Technical Field

[0001] This utility model relates to the field of printed circuit board technology, specifically to a high-precision impedance control printed circuit board structure suitable for AI servers. Background Technology

[0002] As AI server data transmission rates climb to over 100Gbps, the bottlenecks of traditional PCBs in high-frequency, high-speed applications are becoming increasingly apparent, mainly due to the following shortcomings: Impedance mismatch caused by lamination deformation: Traditional single-layer lamination of multilayer boards is prone to interlayer displacement (layer offset) due to thermal deformation during high temperature and high pressure process, resulting in uneven dielectric layer thickness and misalignment of signal reference plane, which ultimately causes impedance fluctuation of more than ±10%, seriously damaging signal integrity.

[0003] Excessive tolerance of vertical lines: Vertical interconnect lines formed by etching process (such as vias, buried vias, etc.) are difficult to control in terms of line width / diameter and copper thickness tolerance (for example, tolerance of ±8μm), which causes the actual impedance to deviate from the design target value, resulting in impedance mismatch and reflection in the signal path.

[0004] High-speed signal crosstalk is severe: High-speed signals are easily interfered with by adjacent traces in high-density cabling environments. The lack of effective inter-layer isolation and shielding leads to a significant increase in signal crosstalk, signal distortion rate, and bit error risk.

[0005] While existing technologies explore the use of segmented pressing (such as double pressing) to mitigate some of the thermal deformation problems, key pain points remain unresolved: Insufficient dielectric stability of the core layer: The thickness uniformity and thermal stability of the core layer as a key dielectric reference layer during the lamination process were not adequately guaranteed.

[0006] Insufficient vertical interconnect precision: There is a lack of effective manufacturing methods for high-precision, low-tolerance vertical interconnect structures (such as copper pillars), making it difficult to achieve precise and controllable vertical impedance matching. Utility Model Content

[0007] In view of this, the present invention provides an impedance control printed circuit board for AI servers, which reduces high-speed signal distortion through a three-stage lamination process and copper pillar interconnection technology, and has the advantages of high interlayer alignment accuracy and good impedance consistency.

[0008] The objective of this utility model is achieved through the following technical solution: An impedance-controlled printed circuit board for an AI server includes a multi-layer stacked structure formed by three lamination processes. The three lamination processes sequentially stack core layers from the inside out, with each lamination containing at least two pre-cured core layers. The core layers remain in a cured state during the lamination process, and the dielectric layer thickness remains constant. Adjacent core layers are laminated together using a prepreg. Vertical lines are provided between the core layers, and these vertical lines are copper pillar structures formed by pattern electroplating. At least one set of high-speed signal lines is laid on the core layers, and the adjacent layers on both sides of the high-speed signal lines are ground layers. In the combination of core layers and prepregs, the dielectric layer thickness of the core layers serves as the primary reference layer for impedance control.

[0009] The core advantage of this impedance-controlled printed circuit board stems from its unique structural design and manufacturing process. It employs a multi-layered structure formed by three lamination processes, with each lamination containing at least two pre-cured core layers. These core layers remain cured during lamination, ensuring the stability and consistency of the dielectric layer thickness. Combined with a prepreg as an interlayer adhesive, this design avoids the thermal deformation and stress concentration problems that easily occur in traditional single-lamination processes, improving the overall alignment accuracy and dimensional control. The vertical lines are formed by copper pillar structures using a patterned electroplating process, directly shaping the circuit pattern and eliminating the need for compensation in traditional etching processes. This significantly reduces linewidth tolerance and impedance fluctuations, directly improving the integrity and reliability of signal transmission, especially in high-speed scenarios, reducing the risk of signal distortion and reflection. High-speed signal lines are laid on the core board layer and configured with adjacent grounding layers on both sides, forming an effective electromagnetic shielding structure that effectively suppresses crosstalk and noise interference and optimizes the signal-to-noise ratio of high-frequency signals. At the same time, the dielectric layer of the core board layer serves as the main reference layer for impedance control. Its cured state ensures the uniformity and independence of dielectric thickness. Compared with prepreg, this design reduces impedance deviation caused by changes in material thickness, enhances the accuracy and predictability of overall impedance control, and enables more stable performance output in high-speed communication of AI servers.

[0010] Preferably, the multilayer structure formed by three pressings includes a first pressing to form an intermediate core board layer group containing high-speed signal lines, a second pressing to stack a second outer core board layer on the upper and lower surfaces of the intermediate core board layer group, and a third pressing to stack an outermost core board layer on the upper and lower surfaces of the second outer core board layer. Through layered pressing, high-speed signal lines with controlled impedance are independently arranged in multiple core board layers.

[0011] By employing a three-stage lamination process, the intermediate core board layer, the second outermost layer, and the outermost layer are formed sequentially. Each lamination focuses on a specific layer group, achieving modular and phased stacking construction. This structure allows for the independent placement of high-speed signal lines within the intermediate core board layer during the first lamination, with the second outermost and outermost layers gradually expanded in subsequent laminations. Impedance control parameters for each layer group can be individually optimized during lamination, avoiding interlayer interference or error accumulation. The independent placement is achieved through the phased lamination design, enabling high-speed signal lines in different layers to have their ground planes and dielectric references configured independently at their respective manufacturing stages, reducing the cross-influence of signal layers in the overall board design. This simplifies the high-speed signal routing process, improving manufacturing yield and maintainability. Independent lamination in a layered manner makes the geometric deformation of each core board layer group easier to control, ensuring the maintenance of interlayer alignment accuracy and perpendicularity, further reducing impedance fluctuations. This allows multiple high-speed signal lines to achieve highly consistent signal performance across different layers, making it particularly suitable for AI servers requiring multi-channel high-speed data transmission, enhancing system bandwidth and overall response efficiency.

[0012] Preferably, the surface of the copper pillar structure of the vertical line is covered with an organic conductive film, and the line pattern is formed by direct imaging technology.

[0013] Vertical routing optimization: The surface of the copper pillar structure is covered with an organic conductive film. This film provides environmental protection and forms a low-resistance conductive interface, reducing signal transmission loss and attenuation (especially in high-frequency applications). The routing pattern is formed using direct imaging technology, eliminating the need for a mask and allowing for precise pattern definition. This avoids alignment errors or blurring associated with traditional photolithography, ensuring clear routing contours and reducing impedance deviation sources. The synergistic effect of precise LDI patterning and the low-resistance characteristics of the organic conductive film simplifies process steps and significantly improves the high-frequency, low-loss transmission capability, durability, and long-term reliability of vertical routing in high-density cabling.

[0014] Preferably, the surface of the copper pillar structure of the vertical line has a rough texture adapted for the attachment of an organic conductive film.

[0015] Interface reinforcement mechanism: The copper pillar structure surface is designed with an adaptive rough texture, which greatly enhances the adhesion and interfacial bonding strength of the organic conductive film. The added mechanical anchor points (micro-texture) strengthen mechanical engagement, effectively preventing film peeling under thermal cycling or mechanical stress, ensuring a stable and continuous conductive interface, and avoiding signal interruption or impedance increase. The rough texture also improves the wettability of the conductive film, allowing it to cover the copper surface more evenly, reducing bubbles and discontinuities, lowering contact resistance, and improving overall conductivity. This design reduces additional processing requirements during manufacturing, ensuring the long-lasting and efficient conductivity of vertical circuits in harsh environments.

[0016] Preferably, the linewidth uniformity error of the vertical line is no greater than 5%, and the copper layer thickness uniformity error of the copper pillar structure is no greater than 5%. The errors are tested according to the IPC-A-600 standard.

[0017] Precise impedance foundation: Vertical linewidth uniformity error ≤5%, copper layer thickness uniformity error ≤5%. Extremely low linewidth fluctuations avoid local impedance abrupt changes in the path, effectively reducing signal reflection, delay inconsistencies, and bit error rate, improving timing accuracy and eye diagram quality for high-speed data. Highly uniform copper layer thickness ensures consistent conductor conductivity and uniform current distribution, reducing hotspot and electromigration risks, and improving line durability under high power density. High uniformity achieved through direct molding via patterned electroplating eliminates the need for etching compensation, simplifies the process, and makes impedance calculations more accurate and controllable, providing core assurance for stable signal integrity and impedance control.

[0018] Preferably, the high-speed signal line is laid within the core board layer group formed by the current lamination, and adjacent grounding layers are configured in the core board layer group.

[0019] Signal integrity optimization strategy: High-speed signal lines are confined to the core board layers formed during the current lamination process, with adjacent ground planes configured within this layer group. This localized layout creates a ground plane wrapping structure (local shielding environment) during the manufacturing lamination process, effectively suppressing external EMI and interlayer crosstalk / noise coupling. Configuring local ground planes optimizes the signal return path (shortening loop distance), reducing signal reflection and attenuation, and improving high-frequency transmission consistency and efficiency. The defined signal layer group range simplifies impedance control mechanisms, allowing for independent local optimization of this layer group (such as adjusting the dielectric reference) without global adjustments, improving design flexibility and manufacturing efficiency. In AI high-density cabling, this strategy shortens the physical path and reduces parasitic parameters, achieving higher bandwidth utilization across multiple channels.

[0020] Preferably, the dielectric layer thickness of the core board layer is the primary reference layer for impedance control.

[0021] The cornerstone of impedance control reliability: The pre-cured dielectric layer of the core board maintains a constant and uniform thickness during lamination, serving as the primary reference layer for impedance control and providing a stable and reliable calculation benchmark. This eliminates the uncertainty of thickness variation caused by flow shrinkage during lamination of the traditionally relied-upon prepreg, simplifying the control model, enhancing predictability, reducing design iterations, and improving manufacturing yield. The curing stability of this reference layer reduces the formation of interlayer impedance gradients, thereby reducing signal path attenuation and distortion, ensuring stable performance of high-frequency / high-speed signal integrity, enabling more reliable long-distance data transmission under the high-frequency operating conditions of AI servers, and simplifying engineering verification.

[0022] Preferably, in the pattern electroplating process of the vertical lines, the interfacial bonding strength between the copper layer and the organic conductive film is adapted to the signal transmission requirements.

[0023] Electrical connection reliability is ensured: In the pattern plating process, the interfacial bonding strength between the copper layer and the organic conductive film is specifically optimized to meet the demands of high-speed signal transmission. This optimized strength ensures the mechanical stability and electrical continuity of the conductive interface, eliminating the risk of microcracks or interface delamination, and preventing increased resistance, current loss, and signal interruption. This optimization enhances the stability of the interface under thermal shock or power fluctuations. The high-strength bonding achieves uniform distribution of the conductive film and a low-resistance interface, directly improving overall conductivity, reducing power loss, and optimizing high-frequency signal transmission rate and quality (improving eye diagram and SNR). This optimized strength also avoids additional interface processing, simplifying manufacturing and ensuring the long-term efficient operation of vertical lines in multilayer structures.

[0024] Preferably, the sheet resistance of the organic conductive film is adapted to the conductivity requirements of the vertical line, and insulation is formed after the conductive film in the non-line area is removed.

[0025] Synergistic Conductivity and Isolation: The sheet resistance of the organic conductive film is designed to meet the conductivity requirements of vertical lines, providing a low-resistance conductive path to ensure efficient signal current flow and reduce transmission losses and power consumption (maintaining stable high-frequency signal amplitude). During manufacturing, precise removal of the organic conductive film from non-line areas creates the necessary insulating barrier, completely eliminating the risks of potential short circuits, leakage, and signal crosstalk caused by stray capacitance / inductance (especially in high-density layouts). The optimized sheet resistance improves current carrying capacity, while selective removal achieves reliable isolation, providing environmental protection without the need for additional solder mask and simplifying the process. These two factors together ensure signal purity, long-term reliability, and testability of vertical lines in complex signal networks.

[0026] Preferably, the core board layer assembly formed by at least one lamination includes a high-speed signal layer with independently controlled impedance.

[0027] The advantages of this utility model compared to the prior art are: Impedance accuracy improvement: Optimize the core board layer curing process to ensure highly uniform dielectric thickness; combined with an optimized copper pillar tolerance control strategy, significantly narrow the impedance fluctuation range.

[0028] Reduced signal distortion: The double-sided shielding structure of the grounding layer effectively suppresses crosstalk and improves the transmission quality of high-frequency signals.

[0029] Enhanced structural stability: The multi-layer lamination process reduces the risk of single-layer lamination misalignment, achieving lower tolerance requirements and higher overall flatness (less risk of warping).

[0030] Manufacturing cost optimization: The introduction of copper pillar technology replaces part of the etching process, reducing the scrap rate and effectively improving the overall yield.

[0031] The innovation of this invention for an impedance-controlled printed circuit board for AI servers lies in the collaborative design of "solidified core layer dielectric reference + precise interconnection of copper pillars + modularization through phased lamination", which solves the problems of impedance mismatch and signal distortion in high-frequency, multi-channel scenarios of AI server PCBs. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the multi-layered stacked structure in Embodiment 1 of this utility model.

[0034] Labeling explanation: Solder resist layer A1, rigid substrate A2, prepreg A3, electrolytic copper foil L1-L18. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0037] It should be noted that similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship commonly used when the product of this application is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0039] The technical solutions in this application will now be described with reference to the accompanying drawings. Example

[0040] This embodiment provides an impedance-controlled printed circuit board for an AI server, comprising a multi-layered structure formed by three lamination processes: a first lamination forms an intermediate core board layer group containing high-speed signal lines; a second lamination stacks a second outermost core board layer onto the upper and lower surfaces of the intermediate core board layer group; and a third lamination stacks an outermost core board layer onto the upper and lower surfaces of the second outermost core board layer. Through layered lamination, impedance-controlled high-speed signal lines are independently arranged across multiple core board layers. The core board layers remain in a cured state during lamination, and the dielectric layer thickness remains constant. Adjacent core board layers are laminated using prepreg. Vertical lines are arranged between the core board layers; these vertical lines are copper pillar structures formed through a patterned electroplating process. In the combination of core board layers and prepreg, the dielectric layer thickness of the core board layer serves as the primary reference layer for impedance control. Prepreg, abbreviated as PP, also known as film, mostly uses fiberglass cloth as a reinforcing material for interlayer bonding.

[0041] The core advantage of this impedance-controlled printed circuit board stems from its unique structural design and manufacturing process. It employs a multi-layered structure formed by three lamination processes, with each lamination containing at least two pre-cured core layers. These core layers remain cured during lamination, ensuring the stability and consistency of the dielectric layer thickness. Combined with a prepreg as an interlayer adhesive, this design avoids the thermal deformation and stress concentration problems that easily occur in traditional single-lamination processes, improving the overall alignment accuracy and dimensional control. The vertical lines are formed by copper pillar structures using a patterned electroplating process, directly shaping the circuit pattern and eliminating the need for compensation in traditional etching processes. This significantly reduces linewidth tolerance and impedance fluctuations, directly improving the integrity and reliability of signal transmission, especially in high-speed scenarios, reducing the risk of signal distortion and reflection. High-speed signal lines are laid on the core board layer and configured with adjacent grounding layers on both sides, forming an effective electromagnetic shielding structure that effectively suppresses crosstalk and noise interference and optimizes the signal-to-noise ratio of high-frequency signals. At the same time, the dielectric layer of the core board layer serves as the main reference layer for impedance control. Its cured state ensures the uniformity and independence of dielectric thickness. Compared with prepreg, this design reduces impedance deviation caused by changes in material thickness, enhances the accuracy and predictability of overall impedance control, and enables more stable performance output in high-speed communication of AI servers.

[0042] The first lamination used 5 core layers, namely Figure 1 Electrolytic copper foils L5-L6, L7-L8, L9-L10, L11-L12, and L13-L14 are added between adjacent core board layers, forming an intermediate core board layer group containing high-speed signal lines.

[0043] The second lamination used two core layers, namely Figure 1 Electrolytic copper foils L3-L4 and L15-L16 are used in the middle core board layer. Prepreg A3 is added between adjacent core board layers, and the outermost core board layer is stacked on the upper and lower surfaces of the middle core board layer group.

[0044] The third lamination used two core layers, namely Figure 1 Electrolytic copper foils L1-L2 and L17-L18 are used in the core board layer. Prepreg A3 is added between adjacent core board layers. The outermost core board layer is stacked on the upper and lower surfaces of the next outermost core board layer.

[0045] The core board layer includes a rigid substrate A2 and electrolytic copper foil covering the upper and lower surfaces of the rigid substrate A2. In this embodiment, the impedance control printed circuit board for the AI ​​server contains a total of 18 layers of electrolytic copper foil, namely L1-L18, and the surface of the outermost core board layer is a solder resist layer A1. The lamination temperature is 220±10℃ each time, and the lamination time is between 0.5 and 1.5 hours.

[0046] The specific layered lamination mechanism directly brings dual advantages to manufacturing and design. Through three lamination steps, the intermediate core board layer, the second outermost layer, and the outermost layer are formed sequentially. Each lamination focuses on a specific layer group, achieving modular and phased stacking construction. This structure allows for the independent placement of high-speed signal lines in the intermediate core board layer group during the first lamination, and the gradual expansion of the second outermost layer and the outermost layer in subsequent laminations. Impedance control parameters for each layer group can be individually optimized during lamination, avoiding interlayer interference or error accumulation. The independent placement is achieved through the phased lamination design, allowing high-speed signal lines in different layer groups to have their ground planes and dielectric references independently configured in their respective manufacturing stages, reducing the cross-influence of signal layers in the overall board design. This simplifies the high-speed signal routing process and improves manufacturing yield and maintainability. By independently laminating in layers, the geometric deformation of each core board layer is easier to control, ensuring the maintenance of interlayer alignment accuracy and perpendicularity, further reducing impedance fluctuations. This enables multiple high-speed signal lines to achieve highly consistent signal performance in different layers, making it particularly suitable for AI servers that require multi-channel high-speed data transmission, thus enhancing system bandwidth and overall response efficiency.

[0047] In this embodiment, the surface of the copper pillar structure of the vertical line is covered with an organic conductive film, and the line pattern is formed by direct imaging technology.

[0048] The vertical circuit design, combining organic conductive film and direct imaging technology, significantly optimizes the accuracy and stability of signal transmission. The surface of the copper pillar structure is covered with an organic conductive film. This film not only acts as a protective barrier to isolate the copper circuit from external environmental corrosion but also provides an additional low-resistance conductive interface, optimizing the conductivity of the signal path and reducing current loss and attenuation during signal transmission. This allows the vertical circuit to maintain lower insertion loss and signal distortion risk in high-frequency applications. Simultaneously, the circuit pattern is formed using direct imaging technology. This process defines the pattern directly on the substrate without the need for masks or templates, improving pattern resolution and accuracy. It avoids alignment errors or pattern blurring problems in traditional photolithography, ensuring clear circuit outlines and no stray patterns, thereby significantly reducing the sources of impedance deviation during manufacturing. The combination of organic conductive film and LDI creates a highly efficient and collaborative manufacturing environment: LDI ensures the precise formation of the copper pillar structure, while the organic conductive film acts as a conductivity enhancement layer to ensure low-resistance connection of the signal interface; the overall solution simplifies process steps, reduces post-processing requirements, and improves the overall durability and long-term reliability of the circuit, especially in the high-density wiring of AI server scenarios, ensuring low-noise transmission capability and improved repeatability of vertical lines.

[0049] In this embodiment, the surface of the copper pillar structure of the vertical line has a rough texture adapted for the attachment of the organic conductive film.

[0050] The rough texture design on the copper pillar structure provides an ideal physical basis for the adhesion of the organic conductive film, directly improving the reliability and efficiency of the interface bonding. The micro-texture formed by the surface roughness increases mechanical anchoring points, strengthening the mechanical engagement between the organic conductive film and the copper pillar. This prevents the risk of film peeling under high-frequency vibration, thermal cycling, or mechanical stress, maintaining the stable continuity of the conductive interface and thus avoiding signal interruption or impedance increase. The rough texture optimizes the wettability of the organic conductive film, allowing it to cover the copper surface more uniformly and reducing the generation of film bubbles or discontinuous areas. This ensures consistent conductivity, reduces contact resistance, and improves the overall efficiency of signal transmission, especially in high-speed switching scenarios, reducing reflection and insertion losses and enhancing signal integrity. In addition, the adaptable rough surface eliminates the adhesion deficiencies commonly found on smooth copper surfaces, reducing parasitic capacitance or inductance effects caused by interface separation, thereby optimizing the quality of the signal path. This design directly reduces process complexity during manufacturing, achieving reliable long-term electrical performance without additional coating treatment, thus enabling vertical lines to maintain durable and efficient conduction performance in the harsh operating environment of AI servers.

[0051] In this embodiment, the high-speed signal line is laid in the core board layer group formed by the current lamination, and the upper and lower adjacent grounding layers are arranged in the core board layer group.

[0052] This layout optimizes high-speed signal lines locally, significantly improving signal integrity and anti-interference capabilities. High-speed signal lines are laid out within the core board layers formed during lamination, co-designed with adjacent grounding layers above and below. This compact configuration achieves immediate shielding at the manufacturing level, directly forming a grounding layer wrapping structure during lamination, reducing the impact of external electromagnetic interference on the signal path and thus lowering the risk of crosstalk and noise coupling. The configuration of adjacent grounding layers creates a local shielding environment within the layer group, preventing reflections or attenuation of high-speed signals during transmission due to inter-layer switching. This optimizes the signal return path, shortens the loop distance, and improves high-frequency performance consistency and transmission efficiency. Confining high-speed signals within the lamination layer group simplifies the overall impedance control mechanism; the independent configuration of the grounding layer allows for local optimization within that specific layer group without global adjustments, improving design flexibility and manufacturing efficiency. In the high-density cabling scenarios of AI servers, this layout reduces the physical length and parasitic parameters of the signal path, ensuring precise adjustment of impedance parameters in each signal layer group, thereby achieving higher bandwidth utilization and system reliability in multi-channel data transmission and avoiding limitations on overall board performance.

[0053] In this embodiment, the dielectric layer thickness of the core board layer serves as the primary reference layer for impedance control.

[0054] The dielectric layer of the core board, serving as the primary reference layer for impedance control, offers a key advantage: providing a stable and reliable calculation benchmark, thus enhancing the accuracy of the overall design. The core board layer remains in a pre-cured state during lamination, ensuring the constant and uniform thickness of the dielectric layer. This eliminates the risk of thickness variations caused by flow or shrinkage during lamination, as is common with traditional prepreg materials, making impedance calculations more consistent and predictable. Designing the dielectric layer as the primary reference layer simplifies the impedance control model, avoiding reliance on the complex and variable PP layer. Designers can optimize the signal layer based on the fixed parameters of the core board layer, reducing the number of overall design iterations and improving manufacturing yield and scalability. Furthermore, this characteristic strengthens the uniform coupling between the signal layer and the reference layer in high-frequency applications, preventing the formation of impedance gradients. This directly reduces signal path attenuation and distortion, especially in high-speed switching scenarios, ensuring stable signal integrity performance. The overall solution uses a stable core board layer as the main reference, which reduces the impact of environmental factors on impedance and enables more reliable long-distance data transmission under the high-frequency operation of AI servers. At the same time, it simplifies the engineering verification process of layer stacking and improves the repeatability of the product.

[0055] In this embodiment, in the pattern electroplating process of the vertical lines, the interfacial bonding strength between the copper layer and the organic conductive film is adapted to the signal transmission requirements.

[0056] Optimized bonding strength at the interface between the copper layer and the organic conductive film directly contributes to the efficiency and reliability of signal transmission, ensuring long-term stability of electrical performance. Adapted bonding strength eliminates the risk of interface delamination or microcracks, providing a continuous conductive path; it avoids resistance increases or current losses during signal transmission, thereby reducing signal reflection and insertion loss in high-frequency scenarios and improving eye diagram opening and signal-to-noise ratio performance. Optimized interface bonding strength also improves thermomechanical stability, maintaining connection integrity under thermal cycling or power fluctuations; this prevents signal path interruptions caused by delamination, ensuring continuous transmission of high-speed data streams, especially enhancing system response reliability in the intensive computation of AI servers. Customized bonding strength achieved through patterned electroplating processes supports uniform distribution of the conductive film, forming a low-resistance interface with the copper layer and reducing interface contact resistance; this directly improves overall conductivity, reduces signal power loss, and optimizes transmission rates at high frequencies. By controlling the bonding strength to adapt to transmission requirements, unnecessary interface processing is avoided, simplifying manufacturing steps; it ensures seamless collaboration between vertical traces and other components in multilayer structures, thereby achieving higher signal integrity design margins and lifespan in high-speed board designs.

[0057] In this embodiment, the sheet resistance of the organic conductive film is adapted to the conductivity requirements of the vertical line, and insulation is formed after the conductive film in the non-line area is removed.

[0058] The sheet resistance adaptation and selective removal process of the organic conductive film jointly optimize conductivity and isolation, improving the overall circuit efficiency and safety. The adapted sheet resistance of the organic conductive film provides a low-resistance conductive path for vertical lines; this ensures efficient signal current flow, reduces transmission loss and power consumption, maintains signal amplitude stability in high-frequency switching environments, and thus reduces bit error rate and data collision risks. Removing the conductive film from non-line areas forms insulation, directly eliminating the possibility of short circuits or leakage; by removing redundant conductive material, a clear physical isolation band is created between lines, preventing signal crosstalk caused by stray capacitance or inductance, especially in high-density layouts, enhancing the electrical independence of adjacent lines. The adapted sheet resistance optimizes the current carrying capacity of the conductive film, matching the transmission requirements of high-speed signals; while the insulation treatment simplifies subsequent processes, eliminating the need for additional solder mask coating to achieve reliable environmental protection. The overall design achieves efficient separation at the manufacturing level, improving the consistency and testability of the entire board. In the complex signal network of the AI ​​server, this feature ensures the signal purity of the vertical line when running at high speed, avoiding background noise interference, thereby enhancing the overall reliability and response accuracy of the system. Example

[0059] In this embodiment, all organic conductive film-related features from Example 1 are removed because the high-precision copper pillar does not require an additional conductive film, the linewidth uniformity error of the vertical line is no greater than 5%, and the copper layer thickness uniformity error of the copper pillar structure is no greater than 5%.

[0060] The vertical lines exhibit minimal linewidth uniformity error, as does the copper layer thickness uniformity error in the copper pillar structure. This uniformity is the core foundation for impedance control, ensuring the stability and predictability of the signal path. Minimal linewidth uniformity error means minimal dimensional variation along the length of the line, avoiding sudden changes in local impedance caused by linewidth fluctuations. This directly reduces signal reflection and delay inconsistencies, improving timing accuracy and eye diagram quality in high-speed data transmission, thereby reducing bit error rate and noise interference risks in high-frequency applications. Simultaneously, minimal copper layer thickness uniformity error ensures consistent conductor conductance, resulting in uniform current distribution and reducing hotspot formation or electromigration effects. This optimizes overall conductivity efficiency, avoiding heat generation issues caused by uneven thickness in high-power-density AI server scenarios, thus improving line durability and reliability. This high uniformity achieved through patterned electroplating eliminates the need for etching compensation, simplifying the manufacturing process. The directly formed line shape reduces manufacturing fluctuation sources, making impedance calculations more accurate and easier to control. Overall, these uniformity characteristics work together to enhance the design margin of signal integrity, enabling the line to perform well in high-bandwidth data transmission, especially in high-density multilayer stacked structures, ensuring the stability of vertical line impedance, thereby supporting more complex signal network designs.

[0061] Technical Field: Pattern Electroplating for High-Performance Computing Circuit Boards Application scenario: Impedance control of vertical traces on PCBs for AI servers Process combination: LDI direct-write imaging: Employs multi-optical-engine parallel scanning technology to directly generate high-precision circuit patterns on the surface of the core board layer, avoiding the alignment errors of traditional masks.

[0062] Organic conductive film synergy: An organic conductive film with a sheet resistance matching is coated on the surface of the copper pillar structure. After LDI exposure, the film layer in non-circuit areas is selectively removed, forming a synchronous construction of insulation isolation and conductive path.

[0063] Advantages and features: The circuit pattern is formed in one step, significantly improving the edge clarity; the interface strength of the organic conductive film is adapted to the requirements of high-speed signal transmission, reducing the risk of impedance fluctuation; it supports high-precision processing of complex patterns such as blind holes and micro-grooves, meeting the needs of high-density interconnect design.

[0064] Technical Field: Fan-out Panel-Level Package (FOPLP) Redistribution Layer (RDL) Application scenario: High-density copper interconnects in AI chip packaging Process combination: LDI panel-level exposure: On a glass substrate or organic substrate, the circuit pattern transfer of an ultra-large panel (700mm×700mm) is achieved through laser direct writing technology, overcoming the warping alignment problem of traditional photolithography.

[0065] Organic conductive film integration: A low sheet resistance organic conductive film is coated on the electroplating seed layer. After LDI-defined patterning, it serves as a masking layer for copper electroplating, achieving uniform deposition of RDL lines.

[0066] Advantages and features: Highly consistent graphic resolution and alignment accuracy for large-size panels; organic conductive film adapts to electroplating solution environment, suppresses side etching and improves line steepness; supports impedance coordination control in multi-chip integrated packaging.

[0067] Technical Field: Etched Copper Circuit Forming for Flexible Circuit Boards Application scenario: Environmentally friendly manufacturing process for 5G flexible printed circuit board antennas Process combination: LDI replaces photolithography: Direct imaging on polyimide substrates eliminates traditional exposure and development steps, reducing chemical waste.

[0068] Organic conductive film catalysis: A functional organic conductive film is used as the activation layer for electroless copper plating to induce selective deposition of copper ions and form a low-roughness wire.

[0069] Advantages and features: The additive process avoids copper etching contamination and achieves carbon neutrality; the organic conductive film provides uniform nucleation sites, improving the adhesion and conductivity uniformity of the copper layer; it is suitable for precise pattern transfer on curved substrates.

[0070] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An impedance-controlled printed circuit board for an AI server, characterized in that, include: The multilayer stacked structure is formed by three pressings, in which the core board layers are stacked sequentially from the inside to the outside. Each pressing contains at least two pre-cured core board layers. The core board layers remain in a cured state during the pressing process and the dielectric layer thickness remains unchanged. Adjacent core board layers are pressed together by a prepreg. Vertical lines are provided between the core board layers, and the vertical lines are copper pillar structures formed by pattern electroplating. At least one set of high-speed signal lines is laid on the core board layer, and the adjacent layers on both sides of the high-speed signal lines are ground layers; In the combination of the core board layer and the prepreg, the dielectric layer thickness of the core board layer serves as the primary reference layer for impedance control.

2. The printed circuit board according to claim 1, characterized in that, The multilayer stack formed by three pressings includes: The first lamination forms an intermediate core board layer assembly containing high-speed signal lines; The second pressing layer is used to stack the outermost core layer onto the upper and lower surfaces of the intermediate core layer assembly; The outermost core layer is superimposed onto the upper and lower surfaces of the second outermost core layer during the third lamination process. High-speed signal lines with controlled impedance are achieved by independently laying out multiple core board layers through layered lamination.

3. The printed circuit board according to claim 1, characterized in that, The surface of the copper pillar structure of the vertical line is covered with an organic conductive film, and the line pattern is formed by direct imaging technology.

4. The printed circuit board according to claim 3, characterized in that, The surface of the copper pillar structure of the vertical line has a rough texture adapted for the attachment of organic conductive films.

5. The printed circuit board according to claim 1, characterized in that, The uniformity error of the line width of the vertical line is no greater than 5%, and the uniformity error of the copper layer thickness of the copper pillar structure is no greater than 5%.

6. The printed circuit board according to claim 1, characterized in that, The high-speed signal line is laid within the core board layer group formed by the current pressing, and adjacent grounding layers are configured in the core board layer group.

7. The printed circuit board according to claim 1, characterized in that, The dielectric layer thickness of the core board layer serves as the primary reference layer for impedance control.

8. The printed circuit board according to claim 1, characterized in that, In the pattern electroplating process of the vertical lines, the interfacial bonding strength between the copper layer and the organic conductive film is adapted to the signal transmission requirements.

9. The printed circuit board according to claim 4, characterized in that, The sheet resistance of the organic conductive film is adapted to the conductivity requirements of the vertical line, and insulation is formed after the conductive film in the non-line area is removed.

10. The printed circuit board according to claim 1, characterized in that, The core board layer assembly formed by at least one lamination includes a high-speed signal layer with independently controlled impedance.

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