A triode with improved operating frequency and gain factor
By designing an asymmetrical base structure and deep trench electrodes in the transistor, the electric field distribution is optimized, solving the performance improvement problem of traditional transistors in high frequency and high gain, and achieving a significant improvement in frequency and gain coefficient.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YANGZHOU YANGJIE ELECTRONIC TECH CO LTD
- Filing Date
- 2025-08-27
- Publication Date
- 2026-07-21
AI Technical Summary
The performance improvement of existing transistors in high frequency and high gain is limited by the fixed parameters such as base region doping concentration, base region thickness and emitter area, making further optimization difficult.
By setting a first heavily doped base region that is wider at the top and a second heavily doped emitter region that is narrower at the bottom in the transistor, combined with a deep trench electrode, an asymmetric structure is formed, which reduces the distance between the emitter region and the collector region, optimizes the electric field distribution, and reduces the carrier transit time and recombination efficiency.
It increases the transistor's operating frequency by 30% and gain by 1.2 times, while also improving the device's current density, and is compatible with existing processes without adding any extra process steps.
Smart Images
Figure CN224538634U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a transistor that improves operating frequency and gain coefficient. Background Technology
[0002] In the field of power electronic device technology, transistors are a commonly used semiconductor device, often used in switching circuits and amplifier circuits. As the application fields of power electronic devices develop towards high frequency and high power, the development and performance optimization of transistors are also moving towards high frequency and high power.
[0003] Currently, the high-frequency and high-gain characteristics of transistors are mainly optimized and improved through the following methods: 1. Reduce the thickness of the base region to decrease the recombination time of charge carriers in the base region and increase the frequency of the transistor; 2. Reduce base region doping to decrease carrier recombination time in the base region and increase transistor frequency; 3. Increasing the doping concentration of the emitter region, increasing the contact area between the base region and the emitter region per unit area, and increasing the contact area between the base region and the collector region per unit area can all increase the current density per unit area of the device, thereby improving the device gain coefficient.
[0004] However, for traditional transistors, once the application scenario is determined, parameters such as base region doping concentration, base region thickness, and emitter area are basically fixed. Therefore, innovating transistor structures to further improve the application frequency and gain coefficient of transistors is a technical problem that urgently needs to be solved in this case. Utility Model Content
[0005] To address the above problems, this invention provides a transistor that reduces the transit time and recombination efficiency of carriers incident from the emitter region into the base region, improves the transistor's operating frequency and gain coefficient, and simultaneously increases the device current density, thereby improving the transistor's operating frequency and gain coefficient.
[0006] The technical solution of this utility model is: A transistor for improving operating frequency and gain coefficient includes a collector electrode, an epitaxial wafer, and a first isolation layer arranged sequentially from bottom to top; The epitaxial wafer is provided with: The first doped base region is provided with several layers, and after its top surface is connected to the first isolation layer, it extends into the epitaxial wafer; the tops of adjacent first doped base regions are interconnected, and their bottoms are spaced apart from each other; The second doped emitter region is provided in several parts, which extend downward from the top surface of the first doped base region and are located inside the top interconnection of adjacent first doped base regions; The base electrode is provided in several forms, each extending downward from the top surface of the first isolation layer to the first heavily doped base region; The emitter electrode has several portions, which extend downward from the top surface of the first isolation layer and are connected to the top surface of the second heavily doped emitter region.
[0007] Specifically, the first heavily doped base region has a cross-section that is wider at the top and narrower at the bottom.
[0008] Specifically, the bottom surface of the base electrode is located below the bottom surface of the second heavily doped emitter region.
[0009] Specifically, the lateral width of the second heavily doped emitter region is greater than the lateral width of the emitter electrode.
[0010] Specifically, the thickness of the epitaxial wafer is 100-2000 μm.
[0011] Specifically, the thickness of the first heavily doped base region is 1-50 μm.
[0012] Specifically, the thickness of the second heavily doped emitter region is 0.5-49 μm.
[0013] Specifically, the first isolation layer is a SiO2 isolation layer or a Si3N4 isolation layer with a thickness of 10-5000nm.
[0014] To improve the frequency and gain of a transistor, this invention uses spaced base regions to form an asymmetrical structure with interconnected tops and spaced bottoms. By placing the emitter region above the spaced bottom area of the base regions, the distance between the emitter and collector regions is reduced. Simultaneously, deep trench electrodes are placed in the base regions to make the electric field distribution between the emitter and base regions more uniform. Compared to traditional transistor devices, the carriers incident from the emitter region into the base region are generally closer to the collector region, thereby reducing the transit time and recombination efficiency of carriers incident from the emitter region into the base region, improving the transistor's operating frequency and gain, and simultaneously increasing the device's current density. Attached Figure Description
[0015] Figure 1 This is a process flow diagram of this utility model; Figure 2 This is a schematic diagram of the cross-sectional structure of the first mask; Figure 3 This is a schematic diagram of the cross-sectional structure of several first-doped base regions that are connected at the top and spaced at the bottom. Figure 4 This is a schematic diagram of the cross-sectional structure of the second mask; Figure 5 This is a schematic diagram of the cross-sectional structure of the second doped emitter region above the bottom spacer region of the first doped base region; Figure 6 This is a schematic diagram of the fabrication of a deep trench cross-section structure; Figure 7 This is a schematic diagram of the cross-sectional structure of the base electrode. Figure 8 This is a schematic diagram of the fabrication of the emitter electrode cross-section structure; Figure 9 This is a schematic diagram of the cross-sectional structure of the current collector electrode; In the figure, 1 is the epitaxial wafer, 2 is the first mask, 3 is the first heavily doped base region, 4 is the fabrication of the second mask, 5 is the second heavily doped emitter region, 6 is the first isolation layer, 7 is the base electrode, 8 is the emitter electrode, and 9 is the collector electrode. Detailed Implementation
[0016] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.
[0017] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0018] The following is for reference. Figure 1-9 Describe this utility model; A method for fabricating a transistor with improved operating frequency and gain coefficient includes the following steps: Step S100: A first mask 2 is prepared on the epitaxial wafer 1, with windows spaced apart, and several first heavily doped base regions 3 are prepared within the epitaxial wafer 1, connected at the top and spaced at the bottom, as shown in the figure. Figure 2-3 As shown; Step S110: Using photolithography, a mask 2 is used to protect the outer region of the first heavily doped base region 3; through diffusion or ion implantation, several first heavily doped base regions 3 are formed with their tops connected and their bottoms spaced apart. Accordingly, the first and second doped regions are P-regions or N-regions with opposite doping charges. The thickness of epitaxial wafer 1 is 100-2000 μm, the thickness of the first heavily doped base region 3 is set to 1-50 μm, the window width is set to 1-500 μm, the window spacing is set to 1-100 μm, and the N-type doping concentration range is 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device; In this embodiment, the first doped region is a P-region, the second doped region is an N-region, and the thickness of the epitaxial wafer 1 is 350 μm; the thickness of the first heavily doped base region 3 is 8 μm, the window width is 20 μm, the window spacing is 10 μm, and the doping concentration is 1e. 16 .cm -3 A first heavily doped base region 3 with a top connection and a thickness of 3 μm is formed, and a first heavily doped base region 3 with a thickness of 5 μm and an increasing spacing from top to bottom is formed. The first heavily doped base region 3 is prepared using a diffusion process.
[0019] Step S200: A second mask 4 is fabricated on the epitaxial wafer 1. A window is opened above the bottom spacer region of the first heavily doped base region 3, and a second heavily doped emitter region 5 is fabricated within the first heavily doped base region 3, as shown in the reference. Figure 4-5 As shown; Step S210: Using photolithography, a mask 4 is used to protect the outer region of the second heavily doped emitter region 5; the second heavily doped emitter region 5 is prepared at the window above the bottom spacer region of the first heavily doped base region 3 by diffusion or ion implantation.
[0020] Accordingly, the thickness of the second doped emitter region 5 is set to 0.5-49 μm, and the window width is set to 0.5-400 μm; In this embodiment, the thickness of the second doped emitter region 5 is set to 2 μm, the window width is set to 15 μm, and the doping concentration is 1e. 19. cm -3 The second heavily doped emitter region 5 was prepared using an ion implantation process.
[0021] Step S300: A first isolation layer 6 is prepared on the epitaxial wafer 1; a deep trench is prepared by opening a window at the first heavily doped base region 3; and a base electrode 7 is prepared within the deep trench, referring to... Figure 6-7 As shown; In step S310, the first isolation layer 6 is prepared by chemical vapor deposition, and the outer area of the base electrode 7 is protected by a mask through photolithography. A deep trench is prepared by etching to open a window. Step S320: Use a stripping process or an etching process to prepare the base electrode 7 in the deep trench; Correspondingly, the first isolation layer 6 serves a protective function. It is made of SiO2 or Si3N4 and has a thickness of 10-5000nm. Deep trenches are prepared by ICP dry etching to open windows. The windows extend downward from the top surface of the first isolation layer 6 into the interior of the first heavily doped base region 3. The bottom surface of the deep trench is not higher than the bottom surface of the first heavily doped base region 3. The base electrode 7 fills the deep trench and forms an ohmic contact with the first heavily doped base region 3. The relevant parameter settings are related to the electrical design of the device. In this embodiment, Si3N4 is used as the first isolation layer 6 with a thickness of 200nm. Deep trenches are prepared by ICP dry etching with a depth of 2200nm. Ti / Al two-layer metal is prepared as the base electrode 7 by local heavy doping and remetallization process and stripping process.
[0022] Step S400: A window is opened in the second heavily doped emitter region 5 to prepare the emitter electrode 8, as per [reference]. Figure 8 As shown; Step S410: Using photolithography, a mask is used to protect the external area of the emitter electrode 8, and an etching process is used to open a window. Step S420: Using a stripping or etching process, prepare the emitter electrode 8 at the window opening; Accordingly, ICP dry etching is used to create a window that extends downward from the top of the first isolation layer 6 into the interior of the second heavily doped emitter region 5. The emitter electrode 8 contacts the second heavily doped emitter region 5 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, ICP dry etching is used to create a window with a depth of 200 nm. A 200 nm thick Ti / Al double metal layer is then prepared as the emitter electrode 8 using a lift-off process.
[0023] Step S500: Fabricate collector electrode 9 on the back side of the epitaxial wafer, referring to... Figure 9 As shown.
[0024] Correspondingly, the epitaxial wafer 1 is thinned to the corresponding thickness through a thinning process, and the collector electrode 9 is prepared on the back side of the epitaxial wafer using a deposition process or a sputtering process; In this embodiment, a thinning process is used to reduce the thickness of the 350µm epitaxial wafer 1 to 180µm, and a deposition process is used to prepare a 1µm thick Ti / Al as the collector electrode 9.
[0025] A transistor for improving operating frequency and gain coefficient includes a collector electrode 9, an epitaxial wafer 1 and a first isolation layer 6 arranged sequentially from bottom to top; The epitaxial wafer 1 is provided with: The first heavily doped base region 3 is provided in a plurality of such regions, which extend downward from the top surface of the epitaxial wafer 1; the tops of adjacent first heavily doped base regions 3 are interconnected, and the bottoms are spaced apart from each other; The second doped emitter region 5 is provided in several parts, which extend downward from the top surface of the first doped base region 3 and are located inside the top interconnection of adjacent first doped base regions 3. The base electrode 7 is provided in several parts, which extend downward from the top surface of the first isolation layer 6 into the first heavily doped base region 3, and are spaced apart from the bottom surface of the first heavily doped base region 3; the base electrode 7 and the first heavily doped base region 3 form a good ohmic contact. The emitter electrode 8 has several portions, which extend downward from the top surface of the first isolation layer 6 and are connected to the top surface of the second heavily doped emitter region 5, forming a good ohmic contact with the second heavily doped emitter region 5.
[0026] The first doped base region has a cross-section that is wider at the top and narrower at the bottom.
[0027] The bottom surface of the base electrode 7 is located below the bottom surface of the second heavily doped emitter region 5.
[0028] The lateral width of the second-doped emitter region 5 is greater than the lateral width of the emitter electrode 8.
[0029] This invention addresses the improvement of transistor frequency and gain by employing an innovative method to fabricate the transistor base region with asymmetrical widths, interconnected at the top and spaced at the bottom. By placing the emitter region above the spaced area at the bottom of the base region, the distance between the emitter and collector regions is reduced. Simultaneously, deep trench electrodes are incorporated into the base region, resulting in a more uniform electric field distribution between the emitter and base regions. Compared to traditional transistor devices, the carriers incident from the emitter region into the base region are closer to the collector region, thereby reducing the transit time and recombination efficiency of carriers. Under the same process and testing conditions, this invention increases the transistor's operating frequency by 30%, the gain by 1.2 times, and the current density. Furthermore, this invention does not require additional process steps compared to commercially available products and processes, and is fully compatible with existing transistor fabrication processes.
[0030] Regarding the information disclosed in this case, the following points need to be clarified: The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case; other structures can be referred to with ordinary designs. Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A transistor for improving operating frequency and gain coefficient, characterized in that, It includes a collector electrode (9), an epitaxial wafer (1) and a first isolation layer (6) arranged sequentially from bottom to top; The epitaxial wafer (1) is provided with: The first heavily doped base region (3) is provided with several, and after its top surface is connected to the first isolation layer (6), it extends into the epitaxial wafer (1); the tops of adjacent first heavily doped base regions (3) are interconnected, and their bottoms are spaced apart from each other; The second doped emitter region (5) is provided in several parts, which extend downward from the top surface of the first doped base region (3) and are located inside the top interconnection of adjacent first doped base regions (3); The base electrode (7) is provided with several electrodes, which extend downward from the top surface of the first isolation layer (6) to the first heavily doped base region (3); The emitter electrode (8) has several portions, which extend downward from the top surface of the first isolation layer (6) and are connected to the top surface of the second heavily doped emitter region (5).
2. The transistor for improving operating frequency and gain coefficient according to claim 1, characterized in that, The first heavily doped base region (3) has a cross-section that is wider at the top and narrower at the bottom.
3. A transistor for improving operating frequency and gain coefficient according to claim 1, characterized in that, The bottom surface of the base electrode (7) is located below the bottom surface of the second heavily doped emitter region (5).
4. A transistor for improving operating frequency and gain coefficient according to claim 1, characterized in that, The lateral width of the second heavily doped emitter region (5) is greater than the lateral width of the emitter electrode (8).
5. A transistor for improving operating frequency and gain coefficient according to claim 1, characterized in that, The thickness of the epitaxial wafer (1) is 100-2000um.
6. A transistor for improving operating frequency and gain coefficient according to claim 1, characterized in that, The thickness of the first heavily doped base region (3) is 1-50 μm.
7. A transistor for improving operating frequency and gain coefficient according to claim 1, characterized in that, The thickness of the second heavily doped emission region (5) is 0.5-49 μm.
8. A transistor for improving operating frequency and gain coefficient according to claim 1, characterized in that, The first isolation layer (6) is a SiO2 isolation layer or a Si3N4 isolation layer with a thickness of 10-5000nm.