IGBT with a distributed double-layer backside buffer structure

Abstract

The utility model discloses a kind of IGBT of distributed double-layer back buffering structure, IGBT includes lightly doped N type base area, superimposed on the front IGBT trench structure layer of lightly doped N type base area, superimposed below deep N+ buffer layer of lightly doped N type base area, collector layer formed in deep N+ buffer layer lower layer and superimposed below back metal layer of collector layer.Among them, multiple shallow N+ buffer layers are spaced apart in deep N+ buffer layer along a first direction, and the shallow N+ buffer layers are formed by distributing ion implantation upward on the lower surface of the deep N+ buffer layer;The first direction is parallel to the lower surface of the deep N+ buffer layer.The structure of the contact area between the deep N+ buffer layer and the shallow N+ buffer layer and the collector layer is distributed, which improves the injection efficiency of the back collector layer.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor devices, specifically relating to an IGBT with a distributed double-layer back buffer structure. Background Technology

[0002] From an energy-saving perspective, insulated-gate bipolar transistors (IGBTs) and fast recovery diodes (FRDs) are widely used in circuit modules such as frequency converters, AC servo systems, and three-phase motor speed control. To reduce frequency converter losses, minimizing the switching losses and forward voltage of IGBTs and FRDs is particularly important.

[0003] To meet specified withstand voltage requirements, IGBT devices require a relatively thick n-type drift layer. During conduction, the main conduction loss originates from this n-type drift layer. To reduce conduction loss, the resistance of the n-type drift layer needs to be reduced; currently, the most effective method is to thin the n-type drift layer. However, if the IGBT is thinned by reducing the thickness of the n-type drift layer, when a voltage is applied to the collector, the depletion layer will reach the back of the chip, i.e., the collector side, leading to a decrease in breakdown voltage and an increase in leakage current. Therefore, current mainstream IGBTs form an n+ buffer layer on the collector side with a higher impurity concentration than the substrate, hereinafter referred to as a "shallow N+ buffer layer," to prevent the depletion layer from reaching the collector layer.

[0004] With advancements in wafer thinning technology, the thickness of IGBT chips can now be reduced to near-limit levels, ensuring the required breakdown voltage is achieved. When the IGBT is in switching mode and a supply voltage and surge voltage are applied between the collector and emitter, a depletion layer reaches the back side of the IGBT. When the depletion layer reaches the back side and is blocked by a shallow N+ buffer layer, carriers are depleted, causing voltage and current oscillations.

[0005] As a countermeasure, a deep N+ buffer layer can be added to the back of the chip. This deep N+ buffer layer has a lower impurity concentration than the shallow N+ buffer layer and is located at a greater depth from the back of the chip, for example, 10 μm or more. By providing a deep N+ buffer layer, the diffusion of the depletion layer can be more gently prevented, even when a high voltage is applied to the collector during switching operations. Therefore, sudden depletion of carriers on the back of the chip can be prevented, and a sharp voltage rise can be prevented by retaining carriers.

[0006] However, for IGBTs using a deep N+ buffer layer structure, to retain carriers to a certain extent within the deep N+ buffer layer during turn-off, precise control of the impurity concentration and depth of the deep N+ buffer layer is required. If the impurity concentration is affected by the amount of injected impurities or subsequent thermal processing, voltage oscillations during turn-off may be exacerbated. Alternatively, when a high voltage is applied to the collector, the depletion layer may reach the collector on the back of the chip, leading to increased leakage current.

[0007] To address the aforementioned issues, existing technologies have proposed a dual-layer back-side buffer structure for IGBTs, featuring shallow and deep N+ buffer layers. While this dual-layer back-side buffer structure can reduce leakage current to some extent, it also leads to a decrease in injection efficiency on the back of the IGBT chip, thereby reducing its breakdown capability during short-circuit operation. Utility Model Content

[0008] To address the aforementioned problems in the existing technology, this utility model provides an IGBT with a distributed double-layer back-side buffer structure.

[0009] The technical problem to be solved by this utility model is achieved through the following technical solution:

[0010] This invention provides an IGBT with a distributed double-layer back-side buffer structure, the IGBT comprising:

[0011] Lightly doped N-type base region;

[0012] A front-side IGBT trench structure layer superimposed on the lightly doped N-type base region; the front-side IGBT trench structure layer is used to form the IGBT emitter and IGBT gate;

[0013] A deep N+ buffer layer superimposed beneath the lightly doped N-type base region;

[0014] The collector layer is formed beneath the deep N+ buffer layer;

[0015] A back metal layer superimposed beneath the current collector layer;

[0016] In the deep N+ buffer layer, a plurality of shallow N+ buffer layers are spaced apart along a first direction; the upper end of the shallow N+ buffer layer is located in the deep N+ buffer layer, and the lower end of the shallow N+ buffer layer is in contact with the collector layer; the first direction is parallel to the lower surface of the deep N+ buffer layer.

[0017] Optionally, the front-side IGBT trench structure layer includes:

[0018] The lightly doped N-type base region superimposed on the lightly doped N-type base region;

[0019] A lightly doped P region superimposed on the lightly doped N region;

[0020] Along the first direction, a plurality of gate regions are spaced apart in the lightly doped N-region and the lightly doped P-region; wherein, the gate regions extend downward from the upper surface of the lightly doped P-region into the lightly doped N-region;

[0021] An interlayer dielectric layer superimposed on the upper surface of each gate region and a gate oxide layer superimposed on the sides and lower surface of each gate region;

[0022] Heavily doped N regions are located on both sides of each gate region and in contact with the interlayer dielectric layer above the gate region;

[0023] A front metal layer covering the lightly doped P-region, the interlayer dielectric layer, and the heavily doped N-region.

[0024] Optionally, the thickness of the lightly doped N-type base region is 50 μm to 300 μm; the thickness of the lightly doped N-region is 5 μm to 20 μm; the thickness of the lightly doped P-region is 2 μm to 10 μm; the thickness of the gate region is 500 Å to 10000 Å; the thickness of the gate oxide layer is 50 Å to 1000 Å; the thickness of the interlayer dielectric layer is 500 Å to 30000 Å; the thickness of the heavily doped N-region is 0.2 μm to 5 μm; and the thickness of the front metal layer is 1 μm to 10 μm.

[0025] Optionally, the material of the lightly doped N-type base region is N-type silicon; the material of the lightly doped N-region is silicon; the material of the lightly doped P-region is silicon; the material of the gate region is polycrystalline silicon; the material of the gate oxide layer is silicon oxide; the material of the interlayer dielectric layer is silicon oxide doped with boron or phosphorus; the material of the heavily doped N-region is silicon; and the material of the front metal layer is aluminum.

[0026] Optionally, the thickness of the lightly doped N-type base region is 50 μm to 300 μm; the thickness of the deep N+ buffer layer is 3 μm to 10 μm; the thickness of the shallow N+ buffer layer is 0.5 μm to 5 μm; the thickness of the collector layer is 0.2 μm to 1 μm; and the thickness of the back metal layer is 0.5 μm to 3 μm.

[0027] Optionally, the material of the lightly doped N-type base region is N-type silicon; the material of the deep N+ buffer layer is silicon; the material of the shallow N+ buffer layer is silicon; the material of the collector layer is silicon; and the material of the back metal layer is silver.

[0028] Optionally, the doping concentration of the deep N+ buffer layer is... ~ The doping concentration of the shallow N+ buffer layer is: ~ .

[0029] This invention provides an IGBT with a distributed double-layer back-side buffer structure. A deep N+ buffer layer is superimposed beneath the lightly doped N-type base region. Multiple shallow N+ buffer layers are spaced apart along a first direction within the deep N+ buffer layer. These shallow N+ buffer layers are formed by distributed ion implantation upwards from the lower surface of the deep N+ buffer layer, meaning the lower end of each shallow N+ buffer layer contacts the collector layer, thus forming a distributed double-buffer layer structure. The first direction is parallel to the lower surface of the deep N+ buffer layer. This distributed double-buffer layer structure facilitates electric field cutoff when the IGBT is in the off state, preventing an increase in leakage current and voltage oscillations during turn-off.

[0030] The collector layer is formed beneath the deep N+ buffer layer. The structure of the contact area between the deep N+ buffer layer and multiple shallow N+ buffer layers with the collector layer is distributed. The deep N+ buffer layer provides a certain field cutoff effect. Due to its lower concentration compared to the shallow N+ layers, it improves the carrier injection efficiency of the back collector, effectively improving the device's conduction characteristics. The multiple shallow N+ buffer layers have a higher doping concentration, enabling rapid electric field cutoff and increasing the device's breakdown voltage. This deep-shallow distribution of cutoff layers effectively improves the electric field distribution and increases the injection efficiency of the back collector layer, thereby improving the chip's forward conduction performance and achieving the goal of reducing leakage current and increasing breakdown voltage.

[0031] The present invention will be further described in detail below with reference to the accompanying drawings. Attached Figure Description

[0032] Figure 1 This is a cross-sectional view of the first distributed double-layer back buffer structure IGBT provided in this embodiment of the utility model;

[0033] Figure 2 This is a cross-sectional view of the second type of distributed double-layer back-side buffer structure IGBT provided in this embodiment of the present invention;

[0034] Figure 3 This is a cross-sectional view of the third type of distributed double-layer back buffer structure IGBT provided in this utility model embodiment;

[0035] Figure 4 This is a cross-sectional view of the fourth distributed double-layer back-side buffer structure IGBT provided in this embodiment of the utility model;

[0036] Figure 5 This is a cross-sectional view of the fifth distributed double-layer back-side buffer structure IGBT provided in this embodiment of the present invention;

[0037] Figure 6 This is a schematic flowchart of a method for fabricating a distributed double-layer back-side buffer structure IGBT according to an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of the preparation of the front IGBT trench structure layer provided in this embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of the preparation of a lightly doped N-type base region provided in an embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram of the preparation of a deep N+ buffer layer provided in an embodiment of this utility model;

[0041] Figure 10 This is a schematic diagram of the preparation of a shallow N+ buffer layer provided in an embodiment of this utility model;

[0042] Figure 11 This is a schematic diagram of the fabrication of the current collector layer provided in an embodiment of the present invention.

[0043] Figure reference numerals: 1. Lightly doped N-type base region; 2. Deep N+ buffer layer; 3. Shallow N+ buffer layer; 4. Collector layer; 5. Back metal layer; 6. Lightly doped N region; 7. Lightly doped P region; 8. Heavyly doped N region; 9. Front metal layer; 10. Interlayer dielectric layer; 11. Gate region; 12. Gate oxide layer. Detailed Implementation

[0044] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0045] To address the low injection efficiency at the back of the chip in existing IGBTs with dual-layer back-side buffer structures, this invention provides an IGBT with a distributed dual-layer back-side buffer structure. (See attached document.) Figure 1 , Figure 1 This is a cross-sectional view of an IGBT with a distributed double-layer back buffer structure provided in an embodiment of the present invention. The IGBT includes a lightly doped N-type base region 1, a front IGBT trench structure layer, a deep N+ buffer layer 2, multiple shallow N+ buffer layers 3, a collector layer 4, and a back metal layer 5.

[0046] In this embodiment of the invention, the lightly doped N-type base region 1 is the substrate of the IGBT. The substrate is the underlying material used to support other materials or structures during the semiconductor device manufacturing process.

[0047] Specifically, the material for the lightly doped N-type base region 1 can be an N-type Si (silicon) material.

[0048] In this embodiment of the invention, the front IGBT trench structure layer is superimposed on the lightly doped N-type base region 1.

[0049] In this embodiment of the invention, the front IGBT trench layer structure includes a lightly doped N region 6, a lightly doped P region 7, a gate region 11, an interlayer dielectric layer 10, a gate oxide layer 12, a heavily doped N region 8, and a front metal layer 9.

[0050] In this embodiment of the invention, a lightly doped N-region 6 is superimposed on a lightly doped N-type base region 1. The lightly doped N-region 6 can achieve non-volatile storage and also reduce carrier loss at the interface.

[0051] In this embodiment of the invention, the lightly doped P region 7 is superimposed on the lightly doped N region 6.

[0052] The lightly doped P-region 7, also known as the P-well region, can isolate N-regions with different functions, thus avoiding mutual interference between N-regions.

[0053] In this embodiment of the invention, a plurality of gate regions 11 are spaced apart in the lightly doped N-region 6 and the lightly doped P-region 7 along a first direction. The first direction is parallel to the lower surface of the deep N+ buffer layer 2.

[0054] Gate region 11 is used to control the current. Specifically, each gate region 11 extends downward from the upper surface of the lightly doped P region 7 into the lightly doped N region 6. By controlling the voltage applied to the gate region 11, the IGBT current flow can be flexibly adjusted to achieve precise current control.

[0055] Furthermore, each gate region 11 extends downward from the upper surface of the lightly doped P region 7 into the lightly doped N region 6, including the upper half of each gate region 11 extending downward from the upper surface of the lightly doped P region 7 into the lightly doped N region 6.

[0056] In this embodiment of the present invention, an interlayer dielectric layer 10 is superimposed on the upper surface of each gate region 11, and a gate oxide layer 12 is superimposed on both sides and the lower surface of each gate region 11.

[0057] In this embodiment of the present invention, the interlayer dielectric layer 10 is superimposed on the upper surface of the gate region 11, and the gate oxide layer 12 is superimposed on both sides and the lower surface of the gate region 11. Both the gate oxide layer 12 and the interlayer dielectric layer 10 serve to provide insulation and protection, and can prevent current leakage.

[0058] In this embodiment of the invention, heavily doped N-regions 8 are located on both sides of each gate region 11 and are in contact with the interlayer dielectric layer 10 above the gate region 11. The doping concentration of the heavily doped P-regions is higher than that of the lightly doped P-regions 7. This difference in doping concentration creates a potential gradient, which is more conducive to controlling the flow of charge carriers.

[0059] Specifically, the heavily doped N-region 8 can be square or stepped, and there is no restriction here.

[0060] In this embodiment of the invention, the front metal layer 9 covers the lightly doped P region 7, the interlayer dielectric layer 10, and the heavily doped N region 8.

[0061] Considering that Al (aluminum) has good electrical conductivity, thermal conductivity and processability, Al is selected as the material of the front metal layer 9 in this embodiment of the utility model.

[0062] The back structure of the IGBT provided in the present invention will be described below. The back structure of the IGBT includes a deep N+ buffer layer 2, a shallow N+ buffer layer 3, a collector layer 4, and a back metal layer 5.

[0063] In this embodiment of the invention, both the deep N+ buffer layer 2 and the shallow N+ buffer layer 3 are buffer layers, which can be used to reduce compatibility issues between materials. Specifically, the buffer layer can provide an intermediate layer between two different materials to improve their interface characteristics, reduce defects caused by differences in thermal expansion coefficients or lattice mismatch, thereby improving the overall stability and performance of the device.

[0064] A distributed double buffer layer structure is formed by superimposing a deep N+ buffer layer 2 under the lightly doped N-type base region 1 and multiple shallow N+ buffer layers 3 spaced apart along the first direction in the deep N+ buffer layer 2.

[0065] The collector layer 4 is formed below the deep N+ buffer layer 2. The shallow N+ buffer layer is formed by distributed ion implantation upward from the lower surface of the deep N+ buffer layer. The lower end of the shallow N+ buffer layer 3 is in contact with the collector layer 4. That is, the structure of the contact area between the deep N+ buffer layer 2 and multiple shallow N+ buffer layers 3 and the collector layer 4 is distributed, which can ensure the implantation efficiency of the back collector layer 4, thereby improving the chip performance.

[0066] Specifically, the multiple shallow N+ buffer layers 3 are spaced evenly. Compared to a non-uniformly spaced arrangement, this evenly spaced arrangement further improves the injection efficiency of the back collector layer 4. The spacing between the shallow N+ buffer layers 3 can be set by technicians according to their needs and is not limited here.

[0067] In this embodiment of the invention, the doping concentration of the deep N+ buffer layer 2 is: ~ The doping concentration of the shallow N+ buffer layer 3 is: ~ The spacing of the shallow N+ buffer layer 3 should be maintained between 2µm and 10µm, and should not exceed 10µm. The minimum spacing should be adjusted according to factors such as substrate concentration and electric field strength at the cutoff location. Designers can also adjust the spacing according to voltage requirements. The depth of the shallow N+ buffer layer 3 can be the same as or shallower than that of the deep N+ buffer layer 2. The specific doping concentration can be set by technicians according to actual needs.

[0068] In this embodiment of the invention, since the doping concentration of the deep N+ buffer layer 2 is relatively low, it can effectively improve the electric field distribution, increase the back collector injection efficiency, and optimize the device conduction characteristics. The shallow N+ layer has a higher concentration, so the electric field can be quickly cut off, which can improve the reverse withstand voltage characteristics of the device and reduce leakage current, ultimately achieving an improvement in the overall device characteristics.

[0069] In one implementation, the lower surface of the shallow N+ buffer layer 3 is in contact with the upper surface of the collector layer 4, and the upper surface of the shallow N+ buffer layer 3 is in contact with the lower surface of the lightly doped N-type base region 1. (See also...) Figure 2 , Figure 2 This is a cross-sectional view of the second type of distributed double-layer back buffer structure IGBT provided in this embodiment of the present invention.

[0070] See Figure 3 , Figure 3 This is a cross-sectional view of the third distributed double-layer back buffer structure IGBT provided in this embodiment of the present invention. The lower surface of the shallow N+ buffer layer 3 is in contact with the upper surface of the collector layer 4, and the upper surface of the shallow N+ buffer layer 3 extends into the lightly doped N-type base region 1.

[0071] See Figure 4 , Figure 4 This is a cross-sectional view of the fourth distributed double-layer back buffer structure IGBT provided in this utility model embodiment. The lower surface of the shallow N+ buffer layer 3 is in contact with the upper surface of the collector layer 4. The upper surface of the shallow N+ buffer layer 3 is located in the deep N+ buffer layer 2, and the upper surface is arc-shaped.

[0072] See Figure 5 , Figure 5 This is a cross-sectional view of the fifth distributed double-layer back buffer structure IGBT provided in this utility model embodiment. The lower surface of the shallow N+ buffer layer 3 is in contact with the lower surface of the collector layer 4, and the upper surface of the shallow N+ buffer layer 3 is in contact with the lower surface of the lightly doped N-type base region 1. The shallow N+ buffer layer 3 is T-shaped.

[0073] In this embodiment of the invention, the back metal layer 5 is superimposed on the collector layer 4.

[0074] Considering that Ag (silver) has good electrical conductivity, thermal conductivity and ductility, Ag is selected as the material of the back metal layer 5 in this embodiment of the utility model.

[0075] In this embodiment of the invention, a deep N+ buffer layer 2 is superimposed beneath the lightly doped N-type base region 1. Multiple shallow N+ buffer layers 3 are spaced apart along a first direction within the deep N+ buffer layer 2, and the lower ends of the shallow N+ buffer layers 3 contact the collector layer 4, thus forming a distributed double-buffer layer structure. The first direction is parallel to the lower surface of the deep N+ buffer layer 2. This distributed double-buffer layer structure facilitates electric field cutoff when the IGBT is in the off state, preventing an increase in leakage current and voltage oscillations during turn-off.

[0076] The collector layer 4 is formed beneath the deep N+ buffer layer 2. The shallow N+ buffer layers are formed by upward distributed ion implantation from the lower surface of the deep N+ buffer layer. The lower end of the shallow N+ buffer layer 3 contacts the collector layer 4. Therefore, the structure of the contact area between the deep N+ buffer layer 2, the multiple shallow N+ buffer layers 3, and the collector layer 4 is distributed. The deep N+ buffer layer 2 provides a certain field cutoff effect. The multiple shallow N+ buffer layers 3 increase the carrier concentration near the collector region, enabling rapid electric field cutoff, increasing the electric field slope, and improving the device's breakdown voltage. This improves the implantation efficiency of the back-side collector layer 4, thereby enhancing the chip's forward conduction performance.

[0077] In one implementation, the thickness of the lightly doped N-type base region 1 is 50 μm to 300 μm; the thickness of the lightly doped N-region 6 is 5 μm to 20 μm; the thickness of the lightly doped P-region 7 is 2 μm to 10 μm; the thickness of the gate region 11 is 500 Å to 10000 Å; the thickness of the gate oxide layer 12 is 50 Å to 1000 Å; the thickness of the interlayer dielectric layer 10 is 500 Å to 30000 Å; the thickness of the heavily doped N-region 8 is 0.2 μm to 5 μm; and the thickness of the front metal layer 9 is 1 μm to 10 μm.

[0078] In one implementation, the thickness of the lightly doped N-type base region 1 is 50 μm to 300 μm; the thickness of the deep N+ buffer layer 2 is 3 μm to 10 μm; the thickness of the shallow N+ buffer layer 3 is 0.5 μm to 5 μm; the thickness of the collector layer 4 is 0.2 μm to 1 μm; and the thickness of the back metal layer 5 is 0.5 μm to 3 μm.

[0079] The specific thickness of each structure can be set by technicians according to actual needs.

[0080] In one implementation, the material of the lightly doped N-type base region 1 is N-type silicon; the material of the lightly doped N-type region 6 is silicon; the material of the lightly doped P-type region 7 is silicon; the material of the gate region 11 is polysilicon; the material of the gate oxide layer 12 is silicon oxide; the material of the interlayer dielectric layer 10 is silicon oxide doped with boron or phosphorus; the material of the heavily doped N-type region 8 is silicon; and the material of the front metal layer 9 is aluminum.

[0081] In one implementation, the material of the lightly doped N-type base region 1 is N-type silicon; the material of the deep N+ buffer layer 2 is silicon; the material of the shallow N+ buffer layer 3 is silicon; the material of the collector layer 4 is silicon; and the material of the back metal layer 5 is silver.

[0082] In this embodiment of the invention, a method for fabricating an IGBT with a distributed double-layer back-side buffer structure is also provided, see [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for fabricating a distributed double-layer back-side buffer structure IGBT according to an embodiment of the present invention. The fabrication method specifically includes the following steps:

[0083] Step S601: Select N-type silicon material as the lightly doped N-type base region 1.

[0084] In this embodiment of the invention, N-type silicon material refers to silicon material whose doping elements are mainly phosphorus, arsenic, antimony, etc.

[0085] Step S602: Prepare a front-side IGBT trench structure layer on the upper surface of the lightly doped N-type base region 1; the front-side IGBT trench structure layer is used to form the IGBT emitter and IGBT gate.

[0086] See Figure 7 , Figure 7 This is a schematic diagram of the fabrication of the front IGBT trench structure layer according to an embodiment of the present invention. The specific steps for fabricating the front IGBT trench structure are as follows:

[0087] a) N-type implantation is performed on the upper surface of the lightly doped N-type base region 1 to form a carrier storage layer, with an implantation concentration of [missing information]. ~ The injection energy requirement is 30keV~2000keV, see [link / reference] Figure 7 Subgraph (a) in the diagram.

[0088] b) See Figure 7 In sub-figure (b), a dry etching process is used to etch trenches downwards on the upper surface of the carrier storage layer for subsequent gate region 11 definition, forming IGBT trenches. The etching depth is 1μm ~ 10μm, and the width is 0.1μm ~ 10μm.

[0089] c) Perform polycrystalline silicon filling, see [link / reference] Figure 7 In sub-figure (c), the polysilicon filling thickness is between 500 Å and 10000 Å, and the polysilicon needs to be N-type doped with a resistivity requirement of 1. ~100 .

[0090] d) After polysilicon deposition, the polysilicon etching region is defined by photolithography, and the polysilicon in the designated region is etched away. After etching, the thickness of the polysilicon is 50 Å to 1000 Å. Then, P-well implantation is performed with an implantation dose of [missing value]. ~ The implantation energy requirement is 30 keV to 200 keV. After implantation, the P-well ions are activated at an activation temperature of 950℃ to 1300℃. This forms the lightly doped P-region 7, the lightly doped N-region 6, the gate region 11, and the gate oxide layer 12. See [link to documentation]. Figure 7 Sub-image (d) is shown in the figure. The thickness of the lightly doped P-region 7 is 2 μm to 10 μm.

[0091] e) Formation of the heavily doped N-region 8: N-well implantation is performed by defining the N-type heavily doped region through photolithography, i.e., N+ implantation is then carried out to form the emitter region of the IGBT. See [link to documentation]. Figure 7 Subgraph (e) in the diagram. The injected dose is... ~ The required injection energy is 30keV~200keV.

[0092] f) Next, interlayer dielectric layer 10 is deposited, wherein the thickness of interlayer dielectric layer 10 is 500 Å to 30000 Å, and the deposition material is silicon oxide doped with boron or phosphorus. After deposition, the hole etching area is defined by photolithography, and plasma etching is performed to etch away the interlayer dielectric in the fixed area to form IGBT contact holes. Then, surface metal Al is deposited with a deposition thickness of 1 μm to 10 μm. After Al deposition, surface metal etching is performed again to form the front metal layer 9, see [link to relevant documentation]. Figure 7 The sub-figure (f) shows the front IGBT trench structure of the chip, which is now complete.

[0093] Step S603: The lower surface of the lightly doped N-type base region 1 is subjected to wafer thinning and high-energy hydrogen ion implantation to form a deep N+ buffer layer 2.

[0094] In this embodiment of the invention, after the front-side IGBT trench structure is fabricated, the back-side IGBT process is performed. First, the lower surface of the lightly doped N-type base region 1 is thinned on a wafer. The thickness of the lightly doped N-type base region 1 after the process is 50 μm to 300 μm. See [link to relevant documentation]. Figure 8 , Figure 8This is a schematic diagram of the preparation of a lightly doped N-type base region 1 provided in an embodiment of this utility model.

[0095] After high-energy hydrogen (H) ion implantation onto the lower surface of the lightly doped N-type base region 1, an annealing process is performed to form a deep N+ buffer layer 2. See [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram illustrating the preparation of the deep N+ buffer layer 2 according to an embodiment of the present invention. The injection concentration is... ~ The required injection energy is 20keV to 1000keV.

[0096] Step S604: Phosphorus (P) or arsenic (As) ions are implanted onto the lower surface of the deep N+ buffer layer 2 to form a plurality of shallow N+ buffer layers 3 spaced apart along a first direction; the first direction is parallel to the lower surface of the deep N+ buffer layer 2.

[0097] In this embodiment of the invention, a second N-type buffer layer is implanted along a first direction in multiple regions with a distribution interval defined by photolithography to form multiple shallow N+ buffer layers 3 with intervals. See [link to previous embodiment]. Figure 10 , Figure 10 This is a schematic diagram illustrating the preparation of the shallow N+ buffer layer 3 according to an embodiment of the present invention. The injection concentration is... ~ The energy requirement is 20keV to 500keV. The first direction is parallel to the lower surface of the deep N+ buffer layer 2.

[0098] Step S605: Perform full-surface boron (B) ion implantation on the lower surface of the deep N+ buffer layer 2 to form the current collector layer 4.

[0099] In this embodiment of the invention, boron (B) ion implantation is performed on the lower surface of the deep N+ buffer layer 2, followed by annealing to form the collector layer 4 of the IGBT. See [link to relevant documentation]. Figure 11 , Figure 11 This is a schematic diagram of the fabrication of the current collector layer provided in an embodiment of this utility model. The implantation concentration is... ~ The injection energy requirement is 20keV~200keV, the annealing temperature is 200℃~600℃, and the annealing time is controlled between 30min and 600min.

[0100] In step S606, a metal deposition operation is performed on the lower surface of the collector layer 4 to form the back metal layer 5.

[0101] In this embodiment of the invention, a 0.5μm to 3μm layer of silver (Ag) metal is deposited on the lower surface of the collector layer 4 to form the back metal layer 5. This completes the fabrication of the IGBT with the distributed double-layer back buffer structure provided in this embodiment of the invention. (See also...) Figure 1 .

[0102] In this embodiment of the invention, a deep N+ buffer layer 2 is superimposed beneath the lightly doped N-type base region 1. Multiple shallow N+ buffer layers 3 are spaced apart along a first direction within the deep N+ buffer layer 2. These shallow N+ buffer layers are formed by distributed ion implantation upwards from the lower surface of the deep N+ buffer layer, meaning the lower end of each shallow N+ buffer layer 3 contacts the collector layer 4, thus forming a distributed double-buffer layer structure. The first direction is parallel to the lower surface of the deep N+ buffer layer 2. This distributed double-buffer layer structure facilitates electric field cutoff when the IGBT is in the off state, preventing an increase in leakage current and voltage oscillations during turn-off.

[0103] The collector layer 4 is formed under the deep N+ buffer layer 2, and the lower end of the shallow N+ buffer layer 3 is in contact with the collector layer 4. That is, the structure of the contact area between the deep N+ buffer layer 2 and the multiple shallow N+ buffer layers 3 and the collector layer 4 is distributed, thereby improving the injection efficiency of the back collector layer 4 and improving the forward conduction performance of the chip.

[0104] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present invention.

[0105] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0106] Although the present invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the description of the present invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0107] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0108] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0109] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the protection scope of the present invention.

Claims

1. An IGBT with a distributed double-layer back-side buffer structure, characterized in that, The IGBT includes: Lightly doped N-type base region; A front-side IGBT trench structure layer superimposed on the lightly doped N-type base region; the front-side IGBT trench structure layer is used to form the IGBT emitter and IGBT gate; A deep N+ buffer layer superimposed beneath the lightly doped N-type base region; The collector layer is formed beneath the deep N+ buffer layer; A back metal layer superimposed beneath the current collector layer; The deep N+ buffer layer is provided with a plurality of shallow N+ buffer layers at intervals along a first direction; the shallow N+ buffer layers are formed by distributing ion implantation upward on the lower surface of the deep N+ buffer layer; the first direction is parallel to the lower surface of the deep N+ buffer layer.

2. The IGBT according to claim 1, characterized in that, The front IGBT trench structure layer includes: The lightly doped N-type base region superimposed on the lightly doped N-type base region; A lightly doped P region superimposed on the lightly doped N region; Along the first direction, a plurality of gate regions are spaced apart in the lightly doped N-region and the lightly doped P-region; wherein, the gate regions extend downward from the upper surface of the lightly doped P-region into the lightly doped N-region; An interlayer dielectric layer superimposed on the upper surface of each gate region and a gate oxide layer superimposed on the sides and lower surface of each gate region; Heavily doped N regions are located on both sides of each gate region and in contact with the interlayer dielectric layer above the gate region; A front metal layer covering the lightly doped P-region, the interlayer dielectric layer, and the heavily doped N-region.

3. The IGBT according to claim 2, characterized in that, The thickness of the lightly doped N-type base region is 50 μm to 300 μm; the thickness of the lightly doped N-region is 5 μm to 20 μm; the thickness of the lightly doped P-region is 2 μm to 10 μm; the thickness of the gate region is 500 Å to 10000 Å; the thickness of the gate oxide layer is 50 Å to 1000 Å; the thickness of the interlayer dielectric layer is 500 Å to 30000 Å; the thickness of the heavily doped N-region is 0.2 μm to 5 μm; and the thickness of the front metal layer is 1 μm to 10 μm.

4. The IGBT according to claim 2, characterized in that, The material of the lightly doped N-type base region is N-type silicon; the material of the lightly doped N-region is silicon; the material of the lightly doped P-region is silicon; the material of the gate region is polycrystalline silicon; the material of the gate oxide layer is silicon oxide; the material of the heavily doped N-region is silicon; and the material of the front metal layer is aluminum.

5. The IGBT according to claim 1, characterized in that, The thickness of the lightly doped N-type base region is 50 μm to 300 μm; the thickness of the deep N+ buffer layer is 3 μm to 10 μm; the thickness of the shallow N+ buffer layer is 0.5 μm to 5 μm; the thickness of the collector layer is 0.2 μm to 1 μm; and the thickness of the back metal layer is 0.5 μm to 3 μm.

6. The IGBT according to claim 1, characterized in that, The material of the lightly doped N-type base region is N-type silicon; the material of the deep N+ buffer layer is silicon; the material of the shallow N+ buffer layer is silicon; the material of the collector layer is silicon; and the material of the back metal layer is silver.

Images