A semiconductor structure
By forming a sidewall layer with a cantilever structure at the corner between the gate top surface and the sidewall, the damage caused by dry etching and ion implantation is solved, the performance of semiconductor devices is improved, and the hot carrier injection effect is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2025-07-21
- Publication Date
- 2026-07-21
AI Technical Summary
In integrated circuits, the hot carrier injection (HCI) effect leads to a decline in device performance. Existing sidewalls and polysilicon gates are damaged during dry etching, and the resistance of lightly doped regions decreases, making it impossible to effectively reduce the peak electric field.
A first sidewall layer with a cantilever structure is formed at the corner between the top surface of the gate and the sidewall. The thickness difference and etching rate difference are controlled by chemical vapor deposition process to protect the sidewall from plasma bombardment and protect the lightly doped region during ion implantation.
It effectively avoids sidewall and gate damage, improves the performance of semiconductor devices, reduces hot carrier injection effects, and improves the electrical characteristics of devices.
Smart Images
Figure CN224538637U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Technology
[0002] In current integrated circuits, the strong lateral electric field in the device channel causes collisional ionization of charge carriers during transport, generating additional electron-hole pairs. Some hot carriers are injected into the gate oxide layer, leading to an increase in the device threshold voltage, a decrease in saturation current and carrier mobility. This phenomenon is called the hot carrier injection (HCI) effect, which severely affects device performance. To improve the HCI effect, light doping (LDD) technology is commonly used to reduce the peak electric field near the gate to drain. The lightly doped (LDD) region acts as a transition region, introducing a gradual change in the electric field, weakening the peak electric field intensity, and thus mitigating the HCI effect.
[0003] The spacer is an essential structure in semiconductor devices, typically surrounding the polysilicon gate to protect it. However, when dry etching sidewalls, plasma bombardment can damage both the spacers and the polysilicon gate. When ion implantation is performed on the source / drain (S / D) region with damaged spacers and polysilicon gate, the lightly doped (LDD) region shrinks while the ion concentration increases. This results in lower resistance in the LDD region, failing to reduce the peak electric field and leading to a severe HCl effect. Utility Model Content
[0004] Therefore, it is necessary to provide a semiconductor structure that can at least avoid the hot carrier injection (HCI) effect and improve the performance of semiconductor devices, addressing the problems mentioned above in the background art.
[0005] To achieve the above and other related objectives, one aspect of this application provides a semiconductor structure, comprising:
[0006] Substrate;
[0007] The gate is located on one side of the substrate and includes a gate top surface facing away from the substrate and gate sidewalls located on both sides of the gate.
[0008] The first sidewall layer covers at least the top surface of the gate and the gate sidewall, and the first sidewall layer forms a cantilever structure at the corner between the top surface of the gate and the gate sidewall.
[0009] In one embodiment, the overhang structure has a first thickness in a first direction perpendicular to the gate sidewall, and the first sidewall layer covering the gate sidewall has a second thickness, wherein the first thickness is greater than the second thickness.
[0010] In one embodiment, the ratio of the first thickness of the overhanging structure to the second thickness of the first sidewall layer ranges from 1.5:1 to 2.5:1.
[0011] In one embodiment, the overhang structure has a third thickness in a second direction perpendicular to the top surface of the gate, and the first sidewall layer covering the top surface of the gate has a fourth thickness, the third thickness being greater than the fourth thickness.
[0012] In one embodiment, the first thickness of the cantilever structure is equal to the third thickness, and the second thickness of the first sidewall layer is equal to the fourth thickness.
[0013] In one embodiment, the angle at the corner between the top surface of the gate and the sidewall of the gate is 270°.
[0014] In one embodiment, the growth rate of the first sidewall layer at the corner between the gate top surface and the gate sidewall is greater than the growth rate of the first sidewall layer on the gate sidewall.
[0015] In one embodiment, the semiconductor structure further includes:
[0016] The second sidewall layer is located between the gate and the first sidewall layer, and the second sidewall layer covers at least the top surface of the gate and the gate sidewall.
[0017] In one embodiment, the etching rate of the first sidewall layer is greater than the etching rate of the second sidewall layer.
[0018] In one embodiment, the ratio of the etching rate of the first sidewall layer to the etching rate of the second sidewall layer ranges from 1.5:1 to 2.5:1.
[0019] According to the semiconductor structure provided by this utility model, a protrusion structure is formed at the corner between the top surface of the gate and the sidewall. The protrusion structure is used to block the sidewall from being etched by plasma during the etching process, thereby avoiding damage to the sidewall and the gate. This avoids the hot carrier injection (HCI) effect caused by the increase in the concentration of the lightly doped (LDD) region during the ion implantation process, and improves the performance of the semiconductor device. Attached Figure Description
[0020] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.
[0021] Figure 1 This is a schematic diagram of the morphology of a semiconductor structure provided in the prior art after plasma etching.
[0022] Figure 2 This is a schematic cross-sectional view of a semiconductor structure provided in one embodiment;
[0023] Figure 3 This is a schematic diagram of the morphology of a semiconductor structure after plasma etching, as provided in one embodiment.
[0024] Explanation of reference numerals in the attached figures:
[0025] 50. Lightly doped region; 100. Substrate; 110. Gate; 111. Gate oxide layer; 120. First sidewall layer; 121. Overhang structure; 130. Second sidewall layer; 140. Gate sidewall; 141. First gate sidewall; 142. Second gate sidewall; 143. Third gate sidewall; 144. Fourth gate sidewall; 150. Lightly doped (LDD) region. Detailed Implementation
[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0031] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.
[0032] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation, the form, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0033] In existing technologies, when dry etching is used to form gate sidewalls, plasma bombardment causes damage to the gate and gate sidewalls, resulting in a top slope of approximately 45° and sidewall erosion. Figure 1As shown, when ion implantation (IMP) is performed to form source / drain (S / D) regions with damage to the gate and gate sidewalls, the lateral size of the lightly doped (LDD) region 50 decreases and the ion concentration increases, resulting in a decrease in the resistance of the lightly doped region, which fails to reduce the peak electric field and causes a severe hot carrier injection (HCI) effect.
[0034] To address the above problems, this utility model provides a semiconductor structure, such as... Figure 2 As shown, it includes:
[0035] Substrate 100;
[0036] Gate 110 is located on one side of substrate 100. Gate 110 includes a gate top surface opposite to the substrate and gate sidewalls located on both sides of the gate.
[0037] The first sidewall layer 120 covers at least the top surface of the gate and the gate sidewall, and the first sidewall layer 120 forms a cantilever structure 121 at the corner between the top surface of the gate and the gate sidewall.
[0038] In one embodiment, such as Figure 2 As shown, substrate 100 can provide an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth process. Specifically, substrate 100 can be at least one of the following materials: silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), etc.
[0039] In one embodiment, the gate 110 may be a polysilicon gate or a metal gate. Furthermore, a gate oxide layer 111 is typically disposed between the gate 110 and the substrate 100, the gate oxide layer 111 including but not limited to silicon oxide (SiO2).
[0040] In one embodiment, a method for forming a gate 110 on a substrate 100 includes: firstly forming a silicon oxide (SiO2) as a gate oxide layer 111 on the surface of the substrate 100 using a process familiar to those skilled in the art, such as thermal oxidation or chemical vapor deposition; then forming a gate material layer, for example using polysilicon as the gate material, on the gate oxide layer 111; and then performing photolithography and etching processes to form the gate 110 from the gate material layer. The formed gate 110 includes a first surface and a second surface disposed opposite to each other, wherein the first surface is a gate bottom surface in contact with the gate oxide layer 111, and the second surface is a gate top surface facing away from the substrate 100. Two gate sidewalls disposed opposite to each other are also included on both sides of the gate 110. Optionally, the gate sidewalls and the gate top surface are disposed perpendicular to each other.
[0041] In one embodiment, the first sidewall layer 120 at least covers the top surface of the gate and the gate sidewall, and a second sidewall layer 130 is further disposed between the gate 110 and the first sidewall layer 120, the second sidewall layer 130 at least covering the top surface of the gate and the gate sidewall. (Refer to...) Figure 2 and Figure 3 As shown, the first sidewall layer 120 forms a portion of the gate sidewall 140, specifically, the first sidewall layer 120 forms the first gate sidewall 141. Similarly, the second sidewall layer 130 forms a portion of the gate sidewall 140, specifically, the second sidewall layer 130 forms the second gate sidewall 142. The first sidewall layer 120 and the second sidewall layer 130 are made of different sidewall materials to form multiple sidewalls on both sides of the gate 110. Furthermore, more gate sidewalls can be disposed between the gate 110 and the second sidewall layer 130, as shown in the figure. Figure 2 As shown, a third gate sidewall 143 and a fourth gate sidewall 144 are further disposed between the gate 110 and the second sidewall layer 130. Therefore, in Figure 3 In the example shown, after dry etching of the first sidewall layer 120 and the second sidewall layer 130, the gate sidewall 140 of the gate 110 formed includes, from the inside to the outside, a fourth gate sidewall 144, a third gate sidewall 143, a second gate sidewall 142 and a first gate sidewall 141.
[0042] In one embodiment, after forming the gate 110, a fourth gate sidewall 144 is first formed on both sides of the gate 110, followed by a third gate sidewall 143 being formed on both sides of the fourth gate sidewall. Then, a second sidewall layer 130 is formed covering the gate top surface and the gate sidewalls, with the second sidewall layer 130 covering the gate 110, the fourth gate sidewall 144, and the third gate sidewall 143. Next, a first sidewall layer 120 is formed covering the gate top surface and the gate sidewalls, with the first sidewall layer 120 covering the gate 110, the fourth gate sidewall 144, the third gate sidewall 143, and the second sidewall layer 130.
[0043] In one embodiment, when the gate sidewall 140 comprises multiple sidewalls, adjacent sidewalls use different sidewall materials. These sidewall materials include, but are not limited to, silicon oxide (SiO2), silicon nitride (SiN), and silicon carbonitride (SiC). x N y ) layer, silicon oxynitride (SiO) x N y Alternatively, the multilayer sidewalls are formed by overlapping two sidewall materials, for example, the first gate sidewall 141 and the third gate sidewall 143 are made of silicon nitride (SiN), and the second gate sidewall 142 and the fourth gate sidewall 144 are made of silicon oxide (SiO2).
[0044] In one embodiment, a chemical vapor deposition (CVD) process can be used to form the gate sidewall. Due to the characteristic that CVD has different growth rates at different angles, with larger angles resulting in relatively faster growth rates, and the angle at the corner between the gate top surface and the gate sidewall being 270°, and both the gate top surface and the gate sidewall being planar (i.e., 180°), the first growth rate of the first sidewall layer 120 at the corner between the gate top surface and the gate sidewall is greater than the second growth rate of the first sidewall layer 120 on the gate sidewall. Similarly, the first growth rate of the first sidewall layer 120 at the corner between the gate top surface and the gate sidewall is also greater than the third growth rate of the first sidewall layer on the gate top surface. Therefore, the first sidewall layer 120 forms a cantilever structure 121 at the corner between the gate top surface and the gate sidewall, such as... Figure 2 As shown.
[0045] In one embodiment, in a first direction perpendicular to the gate sidewall, the overhang structure 121 has a first thickness 'a', and the first sidewall layer 120 covering the gate sidewall has a second thickness 'b', where the first thickness 'a' is greater than the second thickness 'b'. In a second direction perpendicular to the gate top surface, the overhang structure 121 has a third thickness 'c', and the first sidewall layer 120 covering the gate top surface has a fourth thickness 'd', where the third thickness 'c' is greater than the fourth thickness 'd'. Further, the first thickness 'a' and the third thickness 'c' of the overhang structure 121 are equal, and the second thickness 'b' and the fourth thickness 'd' of the first sidewall layer 120 are equal.
[0046] In one embodiment, the ratio of the first growth rate at a 270° receiving angle to the second growth rate at a 180° receiving angle in chemical vapor deposition (CVD) ranges from 1.5:1 to 2.5:1, for example, 1.5:1, 2:1, 2.5:1, etc. Therefore, the ratio of the first thickness a of the overhang structure 121 to the second thickness b of the first sidewall layer 120 covering the gate sidewall ranges from 1.5:1 to 2.5:1, for example, 1.5:1, 2:1, 2.5:1, etc. The ratio of the third thickness c of the overhang structure 121 to the fourth thickness d of the first sidewall layer 120 covering the gate top surface ranges from 1.5:1 to 2.5:1, for example, 1.5:1, 2:1, 2.5:1, etc. Specifically, taking the formation of a silicon nitride (SiN) layer as the first sidewall layer 120 using plasma-enhanced chemical vapor deposition (PECVD) as an example, the ratio of the growth rate at a 270° receiving angle to the growth rate at a 180° receiving angle is approximately 2:1. Based on the above growth rate ratio, the ratio of the first thickness a of the protrusion structure 121 to the second thickness b of the first sidewall layer covering the gate sidewall is approximately 2:1, and the ratio of the third thickness c of the protrusion structure 121 to the fourth thickness d of the first sidewall layer covering the top surface of the gate is approximately 2:1. At this time, the difference between the first thickness a of the protrusion structure 121 and the second thickness b of the first sidewall layer covering the gate sidewall, that is, the portion of the protrusion structure 121 extending beyond the first sidewall layer covering the gate sidewall, is the same as or close to the second thickness b of the first sidewall layer covering the gate sidewall. The protrusion structure 121 can play a role in shielding and protecting the first sidewall layer 120 covering the gate sidewall.
[0047] In one embodiment, the etching rate of the first sidewall layer 120 is greater than the etching rate of the second sidewall layer 130. Taking plasma etching as an example, the etching rate of plasma on silicon nitride (SiN) is greater than that on silicon oxide (SiO2). Therefore, the etching rate of plasma on the first sidewall layer 120 is greater than that of plasma on the second sidewall layer 130. By adjusting the parameters of plasma etching, the ratio of the first etching rate of plasma on the first sidewall layer 120 to the second etching rate of plasma on the second sidewall layer 130 is made to be the same as the ratio of the first growth rate of chemical vapor deposition (CVD) at a 270° receiving angle to the second growth rate at a 180° receiving angle. It is also the same as the ratio of the first thickness a of the overhanging structure 121 to the second thickness b of the first sidewall layer covering the gate sidewall, and the ratio of the third thickness c of the overhanging structure 121 to the fourth thickness d of the first sidewall layer covering the top surface of the gate. At this time, the ratio of the first etching rate of the plasma on the first sidewall layer 120 to the second etching rate on the second sidewall layer 130 ranges from 1.5:1 to 2.5:1, for example, 1.5:1, 2:1, 2.5:1, etc.
[0048] In one embodiment, since the growth rate at a 270° receiving angle to the growth rate at a 180° receiving angle is approximately 2:1 when the silicon nitride (SiN) layer is formed as the first sidewall layer 120 using plasma-enhanced chemical vapor deposition (PECVD), and the ratio of the first thickness a of the formed overhang structure 121 to the second thickness b of the first sidewall layer covering the gate sidewall is also approximately 2:1, the ratio of the plasma etching rate on the first sidewall layer 120 to the etching rate on the second sidewall layer 130 can be adjusted by regulating the plasma etching parameters, such as adjusting the CH3 / CF4 / O2 ratio in the plasma, so that the plasma etching rate on the first sidewall layer 120 is adjusted to the ratio of the etching rate on the second sidewall layer 130. The ratio of the first etch rate of the first sidewall layer 120 to the second etch rate of the second sidewall layer 130 is approximately 2:1. In the vertical direction, the etch rate of silicon nitride (SiN) is twice that of silicon oxide (SiO2). Therefore, plasma etching can effectively remove the portion of the first sidewall layer 120 located on the top surface of the gate and the overhang structure 121, as well as the portion of the second sidewall layer 130 located on the top surface of the gate. The remaining etched portion of the second sidewall layer 130 forms the third gate sidewall 143, and the remaining etched portion of the first sidewall layer 120 forms the fourth gate sidewall 144. The third gate sidewall 143 and the fourth gate sidewall 144 formed at this time are flush with the top surface of the gate 110. Figure 3 As shown.
[0049] Reference Figure 1 and Figure 3 As shown, when no overhang structure is formed at the corner between the top surface of the gate and the sidewall of the gate, the plasma bombardment during the etching process will cause damage to the gate and the sidewall of the gate, resulting in structures such as... Figure 1 The slope shown is approximately 45°. When a cantilever structure 121 is formed at the corner between the gate top surface and the gate sidewall, the resulting semiconductor structure is as follows: Figure 2 As shown, when Figure 2 When the semiconductor structure shown is bombarded by plasma, due to the difference in thickness between the overhang structure and the first sidewall layer, and the difference in etching rate between the first and second sidewall layers, the overhang structure 121 is removed precisely when the first sidewall layer 120 and the second sidewall layer 130 located on top of the gate are removed by dry etching, forming a gate sidewall flush with the top surface of the gate. Figure 3 As shown.
[0050] In one embodiment, since the overhang structure 121 can shield and protect the first sidewall layer 120 covering the gate sidewall, the second thickness b of the first sidewall layer 120 covering the gate sidewall remains unchanged before and after plasma etching.
[0051] Reference Figure 1 and Figure 3As shown, when no overhang structure is formed at the corner between the gate top surface and the gate sidewall, the plasma bombardment during the etching process will cause lateral erosion of the gate sidewall, i.e., the thickness of the gate sidewall will decrease. Therefore, when forming the source / drain (S / D) region using the ion implantation process, the lightly doped (LDD) region 50 formed is as follows: Figure 1 As shown. By forming a cantilever structure 121 at the corner between the top surface of the gate and the sidewall of the gate, a semiconductor structure is formed as follows. Figure 2 As shown, when Figure 2 When the semiconductor structure shown is bombarded by plasma, the first sidewall layer 120 covering the gate sidewall is shielded below the cantilever structure 121 due to the difference in thickness between the cantilever structure and the first sidewall layer 120 covering the gate sidewall. This provides protection for the first sidewall layer 120 covering the gate sidewall. The thickness b of the gate sidewall remains unchanged. Therefore, when forming the source / drain (S / D) region using ion implantation, the formed lightly doped (LDD) region 150 is as follows: Figure 3 As shown, with Figure 1 Compared to the lightly doped (LDD) region 50 shown, its lateral width is increased to improve the hot carrier injection (HCI) effect.
[0052] According to the semiconductor structure provided by this utility model, a protrusion structure is formed at the corner between the top surface of the gate and the sidewall. The protrusion structure is used to block the sidewall from being etched by plasma during the etching process, thereby avoiding damage to the sidewall and the gate. This avoids the hot carrier injection (HCI) effect caused by the increase in the concentration of the lightly doped (LDD) region during the ion implantation process, and improves the performance of the semiconductor device.
[0053] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.
[0054] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0055] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0056] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A gate is located on one side of the substrate, and the gate includes a gate top surface opposite to the substrate and gate sidewalls located on both sides of the gate; A first sidewall layer covers at least the top surface of the gate and the sidewall of the gate, wherein the first sidewall layer forms a cantilever structure at the corner between the top surface of the gate and the sidewall of the gate.
2. The semiconductor structure according to claim 1, characterized in that, In a first direction perpendicular to the gate sidewall, the overhang structure has a first thickness, and the first sidewall layer covering the gate sidewall has a second thickness, wherein the first thickness is greater than the second thickness.
3. The semiconductor structure according to claim 2, characterized in that, The ratio of the first thickness of the cantilever structure to the second thickness of the first sidewall layer ranges from 1.5:1 to 2.5:
1.
4. The semiconductor structure according to claim 2, characterized in that, In a second direction perpendicular to the top surface of the gate, the overhang structure has a third thickness, and the first sidewall layer covering the top surface of the gate has a fourth thickness, the third thickness being greater than the fourth thickness.
5. The semiconductor structure according to claim 4, characterized in that, The first thickness of the cantilever structure is equal to the third thickness, and the second thickness of the first sidewall layer is equal to the fourth thickness.
6. The semiconductor structure according to claim 1, characterized in that, The angle between the top surface of the gate and the corner of the gate sidewall is 270°.
7. The semiconductor structure according to claim 6, characterized in that, The growth rate of the first sidewall layer at the corner between the top surface of the gate and the gate sidewall is greater than the growth rate of the first sidewall layer on the gate sidewall.
8. The semiconductor structure according to claim 3, characterized in that, Also includes: A second sidewall layer is located between the gate and the first sidewall layer, and the second sidewall layer at least covers the top surface of the gate and the gate sidewall.
9. The semiconductor structure according to claim 8, characterized in that, The etching rate of the first sidewall layer is greater than that of the second sidewall layer.
10. The semiconductor structure according to claim 9, characterized in that, The ratio of the etching rate of the first sidewall layer to the etching rate of the second sidewall layer ranges from 1.5:1 to 2.5:1.