Semiconductor structure

Abstract

A semiconductor structure includes a substrate and a p-type doped structure formed in the substrate. The semiconductor device structure also includes an n-type doped structure formed in the substrate. The semiconductor device structure also includes a photoreceptive epitaxial structure partially or completely surrounded by the substrate. Portions of the photoreceptive epitaxial structure are between the p-type doped structure and the n-type doped structure, and the photoreceptive epitaxial structure includes germanium and tin.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures, and more particularly to semiconductor structures having photosensitive epitaxial structures. Background Technology

[0002] The semiconductor integrated circuit industry has experienced rapid growth. During the evolution of integrated circuits, functional density (that is, the number of interconnects per unit chip area) typically increases while geometric dimensions (that is, the smallest components (or lines) that can be manufactured using the technology) decrease. This miniaturization process usually benefits by increasing production efficiency and reducing associated costs.

[0003] Silicon photonic devices can be fabricated using existing semiconductor manufacturing technologies. This allows for the creation of hybrid devices that integrate optical and electronic components onto a single semiconductor chip. Silicon photonic devices are being actively researched and developed to provide faster data transmission between and within semiconductor chips through the use of optical interconnects. Utility Model Content

[0004] The purpose of this invention is to propose a semiconductor structure to solve at least one of the above-mentioned problems.

[0005] This disclosure provides a semiconductor structure comprising: a substrate; a p-type doped structure formed therein; an n-type doped structure formed therein; and a photosensitive epitaxial structure at least partially surrounded by the substrate, wherein a portion of the photosensitive epitaxial structure is located between the p-type doped structure and the n-type doped structure, and the photosensitive epitaxial structure contains germanium and tin.

[0006] According to one embodiment of this disclosure, it further includes: a germanium buffer layer, located between the photosensitive epitaxial structure and the substrate.

[0007] According to one embodiment of this disclosure, it further includes: a silicon-germanium buffer layer, disposed between the germanium buffer layer and the substrate.

[0008] According to one embodiment of this disclosure, it further includes: a silicon-germanium capping layer located on the photosensitive epitaxial structure, wherein the silicon-germanium capping layer is in direct contact with the photosensitive epitaxial structure.

[0009] According to one embodiment of this disclosure, it further includes: a silicon capping layer located on the silicon-germanium capping layer, wherein the silicon capping layer is separated from the photosensitive epitaxial structure by the silicon-germanium capping layer.

[0010] According to one embodiment of this disclosure, it further includes: a silicon capping layer located on the photosensitive epitaxial structure, wherein the silicon capping layer is in direct contact with the photosensitive epitaxial structure.

[0011] According to one embodiment of this disclosure, an upper portion of the photosensitive epitaxial structure protrudes from a top surface of the substrate.

[0012] This disclosure provides a semiconductor structure comprising: a photosensitive epitaxial structure containing tin; a p-type doped structure and an n-type doped structure disposed on opposite sides of the photosensitive epitaxial structure; and a buffer layer surrounding the bottom and sidewalls of the photosensitive epitaxial structure, wherein the buffer layer is located between the photosensitive epitaxial structure and the p-type doped structure, and the buffer layer is located between the photosensitive epitaxial structure and the n-type doped structure.

[0013] According to one embodiment of this disclosure, it further includes: a germanium-containing capping layer located on the photosensitive epitaxial structure, wherein the germanium-containing capping layer is in direct contact with the photosensitive epitaxial structure; and a silicon-containing capping layer located on the germanium-containing capping layer.

[0014] According to one embodiment of this disclosure, a bottom surface of the photosensitive epitaxial structure is higher than the bottom surface of the p-type doped structure and the bottom surface of the n-type doped structure.

[0015] This disclosure provides a method for forming a semiconductor structure, comprising: forming a p-type doped region and an n-type doped region in a semiconductor substrate; partially removing the semiconductor substrate to form a groove exposing portions of the p-type doped region and the n-type doped region; forming a buffer layer along the sidewalls and bottom of the groove; and epitaxially growing a photosensitive structure on the buffer layer, wherein the photosensitive structure contains germanium and tin. Attached Figure Description

[0016] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0017] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G This is a cross-sectional view of a process for forming a portion of a semiconductor device structure, as shown in some embodiments.

[0018] Figure 2 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments.

[0019] Figure 3 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments.

[0020] Figure 4This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments.

[0021] Figure 5 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments.

[0022] Figure 6 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments.

[0023] Figure 7 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments.

[0024] Figure 8 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments.

[0025] Figure 9 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments.

[0026] Figure 10 As shown in some embodiments, this is a portion of a processing cavity used to form a portion of a semiconductor device structure.

[0027] The attached figures are labeled as follows:

[0028] 100:Support substrate

[0029] 101: Semiconductor substrate

[0030] 102: Insulation layer

[0031] 104: Device Layer

[0032] 106: Isolation Structure

[0033] 108N, 108P, 110N, 110P: Doped Structures

[0034] 112: Patterned mask elements

[0035] 114: Groove

[0036] 116: Buffer layer

[0037] 118: Photosensitive Structure

[0038] 120, 122: Germanium-containing caprock

[0039] 124: Protective Components

[0040] 126: Dielectric layer

[0041] 128A, 128B: Semiconductor-metal compound structure

[0042] 130A, 130B, 132A, 132B: Conductive components

[0043] 202: Waveguide Structure

[0044] 502: Buffer layer

[0045] 702: Germanium capping layer

[0046] 902a, 902b, 902c, 902d: Partial

[0047] 1000: Processing cavity

[0048] 1002:Substrate holder

[0049] II: Section

[0050] X, Y: Proportion Detailed Implementation

[0051] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of the invention. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0052] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0053] Embodiments of this disclosure relate to semiconductor device structures having one or more photodetectors. A photodetector is an optoelectronic device configured to absorb photons of incident radiation and convert them into electrical signals. Photodetectors can have many applications, such as optical detection devices, lidar devices, optical communication devices, photosensitive element devices, and the like.

[0054] Figures 1A-1GThis is a cross-sectional view of the process used to form a portion of a semiconductor device structure, as shown in some embodiments. Figure 1A As shown, a semiconductor substrate 101 is received or provided. In some embodiments, the semiconductor substrate 101 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 101 may contain silicon or other elemental semiconductor materials, such as germanium. In some embodiments, the semiconductor substrate 101 includes a semiconductor layer epitaxially grown on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon-germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0055] In some other embodiments, the semiconductor substrate 101 comprises a compound semiconductor. For example, the compound semiconductor comprises one or more group III-V semiconductor materials, the composition of which is based on the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 Defined as follows, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of X1, X2, X3, Y1, Y2, Y3, and Y4 is greater than or equal to zero, and all of them add up to one. The compound semiconductor may comprise silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable substrates comprising group II-VI compound semiconductors may also be used.

[0056] In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SOI) substrate. In some embodiments, such as... Figure 1A As shown, the semiconductor substrate 101 includes a support substrate 100, an insulating layer 102, and a device layer 104. The support substrate 100 may be made of a semiconductor material, such as silicon. The insulating layer 102 may be made of an oxide material, such as silicon oxide. The device layer 104 may contain a semiconductor material, such as silicon. The SOI substrate can be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other applicable methods, or combinations thereof.

[0057] like Figure 1AAs shown, according to some embodiments, a plurality of isolation structures 106 are formed in the device layer 104 of the semiconductor substrate 101. The isolation structures 106 can be used to define various active regions located within the semiconductor substrate 101 and electrically isolate adjacent elements (e.g., n-type doped regions and p-type doped regions) from each other. The isolation structures 106 may comprise or be made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, other suitable materials, or combinations thereof. The isolation structures 106 can be formed using isolation techniques, such as local oxidation of semiconductor (LOCOS), shallow trench isolation (STI), or the like.

[0058] In some embodiments, the formation of the isolation structure 106 includes patterning the device layer 104 of the semiconductor substrate 101 using a photolithography process, etching trenches in the semiconductor substrate 101 (for example, using dry etching, wet etching, plasma etching processes, or combinations thereof), and filling the trenches with one or more dielectric materials (for example, using a chemical vapor deposition (CVD) process). In some embodiments, the filled trenches may have a multi-layer structure, such as a thermal oxide liner filled with silicon nitride or silicon oxide.

[0059] like Figure 1B As shown, according to some embodiments, doped structures 108P, 110P, 108N, and 110N are formed in the device layer 104 of the semiconductor substrate 101. In some embodiments, doped structures 108P and 110P are p-type doped regions formed in the device layer 104. Doped structures 108P and 110P contain p-type impurities, such as boron, gallium, indium, and / or other suitable impurities. In some embodiments, the impurity concentration of doped structure 110P is higher than that of doped structure 108P.

[0060] In some embodiments, doped structures 108N and 110N are n-type doped regions formed in device layer 104. Doped structures 108N and 110N contain n-type impurities, such as phosphorus, antimony, arsenic, and / or other suitable impurities. In some embodiments, the impurity concentration of doped structure 110N is higher than that of doped structure 108N.

[0061] In some embodiments, multiple ion implantation processes are sequentially performed to sequentially form doped structures 108P, 110P, 108N, and 110N. Multiple mask elements are used during the ion implantation process to selectively implant impurities into selective regions. Thus, doped structures 108P, 110P, 108N, and 110N are formed. One or more annealing processes can be used to activate the impurities. For example, a rapid thermal annealing process is used.

[0062] like Figure 1C As shown, according to some embodiments, the device layer 104 of the semiconductor substrate 101 is partially removed to form a trench 114. The trench 114 exposes portions of a p-type doped structure 108P and portions of an n-type doped structure 108N. In some embodiments, the doped structures 108P and 108N are partially removed during the formation of the trench 114. Therefore, the trench 114 extends into the doped structures 108P and 108N. The trench 114 can be formed using one or more photolithography processes and one or more etching processes.

[0063] In some embodiments, a patterned mask element 112 is formed on a semiconductor substrate 101 to facilitate the formation of a recess 114. The semiconductor substrate 101 is then partially removed using one or more etching processes. Thus, the recess 114 is formed. The patterned mask element 112 may be made of or contain an oxide material, such as silicon oxide.

[0064] like Figure 1D As shown, according to some embodiments, a buffer layer 116, a photosensitive structure 118, a germanium-containing capping layer 120, and a silicon-containing capping layer 122 are sequentially formed to fill the groove 114. In some embodiments, the buffer layer 116, the photosensitive structure 118, the germanium-containing capping layer 120, and the silicon-containing capping layer 122 are epitaxially grown. In some embodiments, the buffer layer 116, the photosensitive structure 118, the germanium-containing capping layer 120, and the silicon-containing capping layer 122 are epitaxially grown in situ within the same process chamber.

[0065] According to some embodiments, Figure 10 This image shows a portion of a processing cavity 1000 used in a process for forming a portion of a semiconductor device structure. In some embodiments, the processing cavity 1000 includes a substrate holder 1002. The substrate holder 1002 is used to hold and secure a substrate, such as a wafer. For example, it can hold a substrate containing... Figure 1CThe wafer with the structure shown is held on the substrate holder 1002. Then, multiple processes can be performed on the wafer within the processing cavity 1000.

[0066] In some embodiments, the buffer layer 116, the photosensitive structure 118, the germanium-containing capping layer 120, and the silicon-containing capping layer 122 are sequentially epitaxially grown in situ within the processing cavity. Each of the buffer layer 116, the photosensitive structure 118, the germanium-containing capping layer 120, and the silicon-containing capping layer 122 may be formed using selective epitaxial growth (SEG), CVD processes (e.g., vapor-phase epitaxy (VPE), low-pressure CVD (LPCVD), ultra-high vacuum CVD (UHC-CVD), molecular beam epitaxy (MBE), one or more other applicable processes, or combinations thereof.

[0067] In some embodiments, the processing cavity 1000 does not break the vacuum during the epitaxial growth of the buffer layer 116, photosensitive structure 118, germanium-containing capping layer 120, and silicon-containing capping layer 122. This prevents the formation of the buffer layer 116, photosensitive structure 118, germanium-containing capping layer 120, and silicon-containing capping layer 122 from being negatively affected by the environment outside the processing cavity. For example, it prevents the surfaces of these components from being oxidized by moisture outside the processing cavity 1000. The interfaces between adjacent components can thus achieve good quality and low defect density, improving the reliability and quality of these components.

[0068] In some embodiments, a buffer layer 116 is epitaxially grown over the sidewalls and bottom of the recess 114. In some embodiments, the buffer layer 116 is made of germanium or contains germanium. In some embodiments, the buffer layer 116 does not contain tin. In some embodiments, the buffer layer 116 extends conformally along the sidewalls and bottom of the recess 114. In some embodiments, the buffer layer 116 directly contacts the device layer 104, the doped structure 108P, and the doped structure 108N. The thickness of the buffer layer 116 may be between 10 nm and 100 nm.

[0069] Then, the photosensitive structure 118 is epitaxially grown on the buffer layer 116. In some embodiments, the photosensitive structure 118 is a photosensitive epitaxial structure. In some embodiments, the photosensitive structure 118 is a tin-containing germanium-based epitaxial structure. In some embodiments, the photosensitive structure 118 does not contain p-type impurities or n-type impurities included in the doped structures 108P, 108N, 110P, and 110N. In some embodiments, the photosensitive structure 118 is intrinsic and is not doped with any p-type or n-type impurities. The thickness of the photosensitive structure 118 can be between 100 nm and 2 μm.

[0070] like Figure 1D As shown, in some embodiments, the upper portion of the photosensitive structure 118 protrudes from the top surface of the semiconductor substrate 101. In some embodiments, the photosensitive structure 118 has a curved top surface. In some embodiments, the center of curvature of the curved top surface of the photosensitive structure 118 is located between the curved top surface and the bottom surface of the semiconductor substrate 101. In some embodiments, the center of curvature of the curved top surface of the photosensitive structure 118 is located within the photosensitive structure 118. Figure 1D As shown, in some embodiments, the bottom surface of the photosensitive structure 118 is located at a higher level than the doped structures 108P, 110P, 108N, and 110N.

[0071] In some cases, pure germanium can be used as the photosensitive structure for silicon photonic photodetectors in the O-band (approximately 1310 nm). However, due to material limitations, the absorption coefficient of pure germanium epitaxial structures in the C-band (approximately 1550 nm) can decrease by more than 20 times compared to the O-band, limiting the application of germanium-based photodetectors. In some embodiments, the absorption coefficient of epitaxial structures containing both germanium and tin can be improved in the C-band by adding tin. The addition of tin can induce tensile strain in the photosensitive structure 118, which can help reduce the energy bandgap. Therefore, incident light of longer wavelengths (e.g., approximately in the C-band) can have sufficient energy to create electron-hole pairs in the photosensitive structure 118, which can be detected as current or voltage.

[0072] The amount of tin in the photosensitive structure 118 needs to be carefully adjusted to ensure its performance. In some embodiments, the tin atom concentration of the photosensitive structure 118 is between about 1% and about 15%. In some other embodiments, the tin atom concentration of the photosensitive structure 118 is between about 2% and about 4%.

[0073] In some cases, if the tin atom concentration of the photosensitive structure 118 is less than about 1%, the amount of tin may be too low to maintain a high bandgap. The absorption coefficient in the C-band may not be sufficient. In other cases, if the tin atom concentration of the photosensitive structure 118 is higher than about 15%, the amount of tin may be excessive, which can induce defect formation and may increase undesirable dark current.

[0074] In some embodiments, the photosensitive structure 118 is epitaxially grown in situ within a processing cavity in which the buffer layer 116 is grown. The processing cavity is not subjected to vacuum during the epitaxial growth of the buffer layer 116 and the photosensitive structure 118. The photosensitive structure 118 is epitaxially grown in situ within the processing cavity 100 immediately after the formation of the buffer layer 116. This prevents oxidation of the surface of the buffer layer 116 prior to the subsequent growth of the photosensitive structure 118 without removing it from the processing cavity 1000.

[0075] In some embodiments, no oxide layer or oxide elements are formed between the buffer layer 116 and the photosensitive structure 118. This ensures the interface quality between the buffer layer 116 and the photosensitive structure 118, which can significantly reduce the number of defects. This greatly improves the performance and reliability of the photosensitive structure 118.

[0076] The lattice mismatch between the buffer layer 116 and the device layer 104 of the semiconductor substrate 101 is less than the lattice mismatch between the photosensitive structure 118 and the device layer 104 of the semiconductor substrate 101. Using the buffer layer 116 can significantly reduce defects caused by lattice mismatch, further improving the performance and reliability of the photosensitive structure 118.

[0077] Then, as Figure 1D As shown, according to some embodiments, a germanium-containing capping layer 120 is epitaxially grown on the photosensitive structure 118. The germanium-containing capping layer 120 may be made of germanium or contain germanium. The germanium-containing capping layer 120 may contain or be made of pure germanium, silicon-germanium, other suitable germanium-containing materials, or combinations thereof. In some embodiments, the germanium-containing capping layer 120 is made of silicon-germanium, which has a silicon-germanium structure having the chemical formula Si. (1-X) Ge X The defined composition, where (1-X) and X represent relative proportions. Both are greater than zero and add up to one. The proportion X can range from approximately 10% to approximately 80%. The thickness of the germanium capping layer 120 can range from approximately 5 nm to approximately 50 nm.

[0078] In some embodiments, the germanium-containing capping layer 120 directly contacts the photosensitive structure 118. In some embodiments, the germanium-containing capping layer 120 extends conformally along the curved top surface of the photosensitive structure. In some embodiments, the germanium-containing capping layer 120 may also have a curved top surface.

[0079] In some embodiments, the germanium capping layer 120 is epitaxially grown in situ within the processing cavity 1000 where the buffer layer 116 and the photosensitive structure 118 are grown. The processing cavity 100 is not subjected to vacuum during the epitaxial growth of the buffer layer 116, the photosensitive structure 118, and the germanium capping layer 120. The germanium capping layer 120 is epitaxially grown in situ immediately after the growth of the photosensitive structure 118 within the processing cavity 1000. This prevents oxidation of the surface of the photosensitive structure 118 prior to the subsequent growth of the germanium capping layer 120 without removing it from the processing cavity 1000.

[0080] In some embodiments, no oxide layer or oxide elements are formed between the germanium-containing capping layer 120 and the photosensitive structure 118. This ensures the interface quality between the germanium-containing capping layer 120 and the photosensitive structure 118, which significantly reduces the number of defects. This greatly improves the performance and reliability of the photosensitive structure 118.

[0081] like Figure 1D As shown, according to some embodiments, a silicon-containing capping layer 122 is epitaxially grown over a germanium-containing capping layer 120. The silicon-containing capping layer 122 may be made of silicon or contain silicon. The silicon-containing capping layer 122 may contain or be made of pure silicon, silicon-germanium, other suitable silicon-containing materials, or combinations thereof. In some embodiments, the silicon-containing capping layer 122 has a higher silicon atom concentration than the germanium-containing capping layer 120. The thickness of the silicon-containing capping layer 122 may be between approximately 5 nm and approximately 50 nm.

[0082] In some embodiments, the silicon-containing capping layer 122 directly contacts the germanium-containing capping layer 120. In some embodiments, the silicon-containing capping layer 122 is spaced apart from the photosensitive structure 180 by the germanium-containing capping layer 120. In some embodiments, the silicon-containing capping layer 122 extends conformally along the curved top surface of the germanium-containing capping layer 120. In some embodiments, the silicon-containing capping layer 122 also has a curved top surface.

[0083] In some embodiments, the silicon-containing capping layer 122 is epitaxially grown in situ within a processing cavity 1000 where the buffer layer 116, photosensitive structure 118, and germanium-containing capping layer 120 are grown. The processing cavity 1000 is not subjected to vacuum during the epitaxial growth of the buffer layer 116, photosensitive structure 118, germanium-containing capping layer 120, and silicon-containing capping layer 122. The silicon-containing capping layer 122 is epitaxially grown in situ immediately after the growth of the germanium-containing capping layer 120 within the processing cavity 1000. Without removing it from the processing cavity 1000, oxidation of the surface of the germanium-containing capping layer 120 before the subsequent growth of the silicon-containing capping layer 122 can be prevented.

[0084] In some embodiments, no oxide layer or oxide element is formed between the germanium capping layer 120 and the silicon capping layer 122. The silicon capping layer 122 can be used to prevent germanium in the germanium capping layer 120 and the photosensitive structure 118 from diffusing into the elements surrounding the photosensitive structure 118. Therefore, the performance and reliability of the semiconductor device structure are greatly improved.

[0085] The lattice mismatch between the silicon capping layer 122 and the germanium capping layer 120 is less than that between the photosensitive structure 118 and the silicon capping layer 122. The buffering effect of the germanium capping layer 120 significantly reduces defects caused by lattice mismatch, further improving the performance and reliability of the photosensitive structure 118.

[0086] In some embodiments, the operating temperature of the processing cavity 1000 can be maintained at a high temperature between approximately 300°C and approximately 600°C. In some embodiments, the photosensitive structure 118 has a higher coefficient of thermal expansion than the semiconductor substrate 101. After being removed from the processing cavity 1000, the photosensitive structure 118 can shrink more than the semiconductor substrate 101. Therefore, tensile strain can be generated within the photosensitive structure 118, which can help reduce the band gap of the photosensitive structure 118. Therefore, incident light of a longer wavelength (e.g., approximately in the C-band) can have sufficient energy to create electron-hole pairs in the photosensitive structure 118, which can be detected as current or voltage. This can improve the responsivity of the photosensitive structure 118.

[0087] like Figure 1E As shown, according to some embodiments, a protective element 124 is formed on a silicon-containing capping layer 122. In some embodiments, the protective element 124 extends laterally beyond the opposite edges of the photosensitive structure 118.

[0088] The protective element 124 may comprise or be made of oxide materials, nitride materials, other suitable materials, or combinations thereof. The protective element 124 may comprise or be made of silicon oxide, silicon nitride, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, or combinations thereof. A protective material layer may be deposited and then patterned to form the protective element 124.

[0089] In some embodiments, the protective element 124 is made of a nitrogen-containing material, such as silicon nitride, silicon oxynitride, and the like. The protective element 124 can also act as a stressor, inducing tensile strain in the photosensitive structure 118. This can thereby improve the performance of the photosensitive structure 118.

[0090] like Figure 1FAs shown, according to some embodiments, a dielectric layer 126 is deposited on a semiconductor substrate 101 and a photosensitive structure 118. The dielectric layer 126 may comprise or be made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low dielectric constant material, a porous dielectric material, other suitable materials, or combinations thereof. The dielectric layer 126 may be deposited using CVD processes, atomic layer deposition (ALD) processes, flowable CVD (FCVD) processes, other applicable processes, or combinations thereof.

[0091] In some embodiments, a contact etch stop layer (CESL) is deposited on the semiconductor substrate 101 and the protective element 124 prior to the formation of the dielectric layer 126. The contact etch stop layer may comprise or be made of silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, other suitable materials, or combinations thereof.

[0092] like Figure 1G As shown, according to some embodiments, conductive components 130A, 130B, 132A, and 132B are formed. Conductive components 130A and 132A are electrically connected to doped structure 108P via doped structure 110P. Conductive components 130B and 132B are electrically connected to doped structure 108N via doped structure 110N. In some embodiments, conductive components 130A and 130B are conductive contacts respectively provided with electrical connections to doped structures 110P and 110N. In some embodiments, conductive components 132A and 132B are conductive wires. Conductive components 130A, 130B, 132A, and 132B may comprise or be made of copper, aluminum, tungsten, cobalt, other suitable materials, or combinations thereof.

[0093] In some embodiments, such as Figure 1GAs shown, a semiconductor-metal compound structure 128A is formed between the conductive component 130A and the doped structure 110P. A semiconductor-metal compound structure 128B is formed between the conductive component 130B and the doped structure 110N. In some embodiments, the semiconductor-metal compound structures 128A and 128B may comprise or be made of a metal silicide material. The semiconductor-metal compound structures 128A and 128B may comprise titanium silicide, nickel silicide, cobalt silicide, tungsten silicide, other suitable materials, or combinations thereof.

[0094] In some embodiments, the semiconductor-metal compound structure 128A further includes a p-type impurity. In some embodiments, the p-type impurity in the semiconductor-metal compound structure 128A is the same as the p-type impurity in the doped structure 110P. In some embodiments, the semiconductor-metal compound structure 128B further includes an n-type impurity. In some embodiments, the n-type impurity in the semiconductor-metal compound structure 128N is the same as the n-type impurity in the doped structure 110N.

[0095] In some embodiments, one or more photolithography processes and one or more etching processes are used to form openings for accommodating conductive components 130A, 130B, 132A, 132B, semiconductor-metal compound structure 128A, and semiconductor-metal compound structure 128B. These openings expose doped structures 110P and 110N.

[0096] Then, a metal layer is deposited over the exposed portions of doped structure 110P and doped structure 110N. A heating operation is used to initiate a reaction between the metal layer and doped structures 110P and 110N. Thus, semiconductor-metal compound structures 128A and 128B are formed. In some embodiments, the heating operation is performed after the metal layer is formed. In some other embodiments, the heating operation is performed during the metal layer formation. In some embodiments, portions of the metal layer not formed as semiconductor-metal compound structures 128A and 128B are subsequently removed or formed as barrier layers. Then, one or more conductive material layers are formed to overfill the openings. A planarization process is used to remove portions of the conductive material layers outside the openings. Thus, the remaining portions of the conductive material layers form conductive components 130A, 130B, 132A, and 132B.

[0097] Figure 2 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments. In some embodiments, Figure 2This shows a horizontal cross-sectional view of a portion of a semiconductor device structure. In some embodiments, Figure 1D The structure shown in the image is along Figure 2 The image is taken from section II. For clarity, some components, such as the germanium capping layer 120, the silicon capping layer 122, the patterned mask element 112, and the isolation structure 106, are not shown. Figure 2 In some embodiments, portions of the device layer 104 serve as the core of the waveguide structure 202. The waveguide structure 202 may also include an insulating layer 102 and a dielectric layer 126 formed subsequently.

[0098] In some embodiments, the core of the waveguide structure 202 has a first refractive index, while the structure surrounding the core has a second refractive index. The first refractive index is higher than the second refractive index. Therefore, when a light beam is guided into the waveguide structure 202, as the beam propagates along the length of the waveguide structure 202, it is confined within the core due to total internal reflection.

[0099] In some embodiments, the doped structure 108P, the photosensitive structure 118, and the doped structure 108N together form a pin diode. In some embodiments, the pin diode is reverse biased. In some embodiments, the doped structure 108P is negatively charged, while the doped structure 108N is positively charged.

[0100] In some embodiments, light is guided by waveguide structure 202 and incident on photosensitive structure 118. Electron-hole pairs are thus generated due to photon absorption. The electron-hole pairs are separated by an electric field between the reverse-biased doped structures 108P and 108N, generating a current. The magnitude of the current is proportional to the intensity of the incident light.

[0101] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 3 This is a cross-sectional view of a portion of a semiconductor device structure according to some embodiments. In some embodiments, a germanium-containing capping layer 120 is not formed. In some embodiments, a silicon-containing capping layer 122 directly contacts the photosensitive structure 118.

[0102] In some embodiments, the bottom surface of the photosensitive structure 118 is higher than the bottom surface of the doped structure 108P and the bottom surface of the doped structure 108N. However, the embodiments of this disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of this disclosure.

[0103] Figure 4This is a cross-sectional view of a portion of a semiconductor device structure according to some embodiments. In some embodiments, a recess 114 is formed for receiving a photosensitive structure 118 to penetrate the bottom surface of both the doped structure 108P and the bottom surface of the doped structure 108N. In some embodiments, the photosensitive structure 118 penetrates the opposite surface of the doped structure 108N. In some embodiments, the photosensitive structure 118 penetrates the opposite surface of the doped structure 108P. In some embodiments, due to the increased overlap area between the photosensitive structure 118 and the doped structures 108P and 108N, the electric field between the doped structures 108P and 108N more easily separates electron-hole pairs generated by the absorption of photons.

[0104] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 5 This is a cross-sectional view of a portion of a semiconductor device structure according to some embodiments. In some embodiments, buffer layer 502 is epitaxially grown on the sidewalls and bottom of recess 114 prior to the formation of buffer layer 116. In some embodiments, buffer layer 502 may comprise or be made of silicon-germanium. In some embodiments, buffer layer 502 does not contain tin. In some embodiments, buffer layer 502 and buffer layer 116 are epitaxially grown in situ within processing cavity 1000.

[0105] In some embodiments, the buffer layer 502 extends conformally along the sidewalls and bottom of the groove 114. In some embodiments, the buffer layer 502 directly contacts the device layer 104, the doped structure 108P, and the doped structure 108N. The thickness of the buffer layer 502 may be between approximately 10 nm and approximately 100 nm.

[0106] In some embodiments, the lattice mismatch between the buffer layer 502 and the device layer 104 of the semiconductor substrate 101 is less than the lattice mismatch between the buffer layer 116 and the device layer 104 of the semiconductor substrate 101. Using the buffer layer 502 can further reduce defects caused by lattice mismatch.

[0107] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 6 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments. Similar to... Figure 4 as well as Figure 5 As shown in the structure, a buffer layer 502 is formed between the buffer layer 116 and the semiconductor substrate 101. In some embodiments, the photosensitive structure 118 penetrates the opposite surface of the doped structure 108N. In some embodiments, the photosensitive structure 118 penetrates the opposite surface of the doped structure 108P.

[0108] In some embodiments, the photosensitive structure 118 directly contacts the germanium-containing capping layer 120. However, the embodiments of this disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of this disclosure.

[0109] Figure 7 This is a cross-sectional view of a portion of a semiconductor device structure according to some embodiments. In some embodiments, a germanium capping layer 702 is epitaxially grown on a photosensitive structure 118 prior to the formation of a germanium-containing capping layer 120. In some embodiments, the germanium capping layer 702 is in direct contact with the photosensitive structure 118. In some embodiments, the germanium capping layer 702 is made of pure germanium. In some embodiments, the germanium atom concentration of the germanium capping layer 702 is higher than the germanium atom concentration of the germanium-containing capping layer 120. In some embodiments, the germanium capping layer 702 and the photosensitive structure 118 are epitaxially grown in situ within a processing cavity 1000.

[0110] In some embodiments, the lattice mismatch between the germanium capping layer 120 and the germanium capping layer 702 is lower than the lattice mismatch between the photosensitive structure 118 and the germanium capping layer 120. Using the germanium capping layer 702 significantly reduces defects caused by lattice mismatch, further improving the performance and reliability of the photosensitive structure 118.

[0111] Many variations and / or modifications can be made to the embodiments of this disclosure. Figure 8 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments. Similar to... Figure 7 as well as Figure 5 The structure shown in the figure has a germanium capping layer 702 formed between the germanium capping layer 120 and the photosensitive structure 118. In some embodiments, the photosensitive structure 118 penetrates the opposite surface of the doped structure 108N. In some embodiments, the photosensitive structure 118 penetrates the opposite surface of the doped structure 108P.

[0112] In some embodiments, the tin atom concentration is substantially the same in different portions of the photosensitive structure 118. However, the embodiments of this disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of this disclosure.

[0113] Figure 9 This is a cross-sectional view of a portion of a semiconductor device structure, as shown in some embodiments. In some embodiments, the reactive gas mixture used to grow the photosensitive structure 118 can be adjusted during the growth of the photosensitive structure 118. Therefore, the tin atom concentrations are different in different portions of the photosensitive structure 118.

[0114] In some embodiments, the photosensitive structure 118 has multiple portions: portion 902a, portion 902b, portion 902c, and portion 902d. In some embodiments, the tin atom concentration inside the photosensitive structure 118 (e.g., portion 902c) is higher than the tin atom concentration on the outside of the photosensitive structure 118 (e.g., portion 902b or portion 902d). In some embodiments, the tin atom concentration in portion 902b is higher than the tin atom concentration in portion 902a.

[0115] Because the photosensitive structure 118 has a low tin atom concentration on its exterior, mismatches between the photosensitive structure 118 and surrounding components can be reduced. This further reduces defects caused by lattice mismatches, which can improve the performance and reliability of the photosensitive structure 118.

[0116] Embodiments of this disclosure include a semiconductor device structure with a photodetector. The photodetector comprises a germanium-based photosensitive structure. Adding tin to the germanium-based photosensitive structure can significantly increase the absorption coefficient of the germanium-based photosensitive structure in the C-band. One or more buffer layers and / or one or more protective capping layers are formed to surround and protect the germanium-based photosensitive structure to reduce the formation of defects in the photosensitive structure. This results in a photodetector with high responsivity, low dark current density, and high bandwidth. The performance and reliability of the semiconductor device structure are greatly improved.

[0117] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate and a p-type doped structure formed therein. The semiconductor device structure further includes an n-type doped structure formed therein. The semiconductor device structure further includes a photosensitive epitaxial structure partially or completely surrounded by the substrate. A portion of the photosensitive epitaxial structure is located between the p-type doped structure and the n-type doped structure, and the photosensitive epitaxial structure contains germanium and tin. In some embodiments, the semiconductor device structure includes a tin atom concentration of about 1% to about 15%. In some embodiments, the semiconductor device structure further includes a germanium buffer layer located between the photosensitive epitaxial structure and the substrate. In some embodiments, the semiconductor device structure further includes a silicon-germanium buffer layer located between the germanium buffer layer and the substrate. In some embodiments, the semiconductor device structure includes a p-type doped structure comprising silicon and p-type impurities, an n-type doped structure comprising silicon and n-type impurities, and a photosensitive epitaxial structure not containing p-type or n-type impurities. In some embodiments, the semiconductor device structure further includes a silicon-germanium capping layer located above the photosensitive epitaxial structure, wherein the silicon-germanium capping layer is in direct contact with the photosensitive epitaxial structure. In some embodiments, the semiconductor device structure further includes a silicon capping layer located above a silicon-germanium capping layer, wherein the silicon capping layer is separated from the photosensitive epitaxial structure by the silicon-germanium capping layer. In some embodiments, the semiconductor device structure includes an upper portion of the photosensitive epitaxial structure protruding from the top surface of a substrate. In some embodiments, the semiconductor device structure includes an interior and an exterior, the interior having a first tin atom concentration and the exterior having a second tin atom concentration, wherein the first tin atom concentration is higher than the second tin atom concentration.

[0118] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a tin-containing photosensitive epitaxial structure. The semiconductor device structure includes a p-type doped structure and an n-type doped structure disposed on opposite sides of the photosensitive epitaxial structure. The semiconductor device structure further includes a buffer layer surrounding the bottom and sidewalls of the photosensitive epitaxial structure. The buffer layer is located between the photosensitive epitaxial structure and the p-type doped structure. The buffer layer is located between the photosensitive epitaxial structure and the n-type doped structure. In some embodiments, the semiconductor device structure further includes a germanium-containing capping layer located on the photosensitive epitaxial structure, wherein the germanium-containing capping layer is in direct contact with the photosensitive epitaxial structure; and a silicon-containing capping layer located on the germanium-containing capping layer. In some embodiments, the semiconductor device structure further includes a first conductive component electrically connected to the p-type doped structure; a second conductive component electrically connected to the n-type doped structure; a first semiconductor-metal compound structure located between the first conductive component and the p-type doped structure, wherein the first semiconductor-metal compound structure contains a p-type impurity; and a second semiconductor-metal compound structure located between the second conductive component and the n-type doped structure, wherein the second semiconductor-metal compound structure contains an n-type impurity. In some embodiments, the semiconductor device structure has a bottom surface of the photosensitive epitaxial structure that is higher than both the bottom surface of the p-type doped structure and the bottom surface of the n-type doped structure. In some embodiments, the semiconductor device structure further contains germanium in the photosensitive epitaxial structure, while the buffer layer is substantially free of tin.

[0119] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming p-type doped regions and n-type doped regions in a semiconductor substrate. The method further includes partially removing the semiconductor substrate to form a recess exposing portions of the p-type doped regions and the n-type doped regions. The method also includes forming a buffer layer along the sidewalls and bottom of the recess. Furthermore, the method includes epitaxially growing a photosensitive structure on the buffer layer. The photosensitive structure contains germanium and tin. In some embodiments, the method includes epitaxially growing the buffer layer and the photosensitive structure in an in-situ processing cavity, and the processing cavity is not vacuumed during the growth of the buffer layer and the photosensitive structure. In some embodiments, the method further includes directly forming a silicon-germanium capping layer on the photosensitive structure. In some embodiments, the method includes epitaxially growing the silicon-germanium capping layer in an in-situ processing cavity, and the processing cavity is not vacuumed during the growth of the buffer layer and the photosensitive structure. In some embodiments, the method of forming a semiconductor device structure further includes forming a nitrogen-containing stress layer on a silicon-germanium capping layer.

[0120] The foregoing outlines components of several embodiments to facilitate a better understanding of the embodiments of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: One substrate; A p-type doped structure is formed in the substrate; An n-type doped structure is formed in the substrate; A tin-germanium-based photosensitive epitaxial structure is at least partially surrounded by the substrate, wherein a portion of the tin-germanium-based photosensitive epitaxial structure is located between the p-type doped structure and the n-type doped structure; A germanium buffer layer is disposed between the tin-germanium-based photosensitive epitaxial structure and the substrate; and A silicon-germanium capping layer is located on the tin-germanium-based photosensitive epitaxial structure.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A silicon-germanium buffer layer is disposed between the germanium buffer layer and the substrate.

3. The semiconductor structure as described in claim 1, characterized in that, The silicon-germanium capping layer is in direct contact with the tin-germanium-based photosensitive epitaxial structure.

4. The semiconductor structure as described in claim 3, characterized in that, Also includes: A silicon capping layer is located on top of the silicon-germanium capping layer, wherein the silicon capping layer is separated from the tin-germanium-based photosensitive epitaxial structure by the silicon-germanium capping layer.

5. The semiconductor structure as described in claim 1, characterized in that, The upper part of the tin-germanium-based photosensitive epitaxial structure protrudes from the top surface of the substrate.

6. A semiconductor structure, characterized in that, include: A tin-germanium-based photosensitive epitaxial structure; A p-type doped structure and an n-type doped structure are disposed on opposite sides of the tin-germanium-based photosensitive epitaxial structure; A buffer layer surrounds a bottom and multiple sidewalls of the tin-germanium-based photosensitive epitaxial structure, wherein the buffer layer is located between the tin-germanium-based photosensitive epitaxial structure and the p-type doped structure, and between the tin-germanium-based photosensitive epitaxial structure and the n-type doped structure; and A silicon-germanium capping layer is located on the tin-germanium-based photosensitive epitaxial structure, wherein the silicon-germanium capping layer is in direct contact with the tin-germanium-based photosensitive epitaxial structure.

7. The semiconductor structure as described in claim 6, characterized in that, Also includes: A silicon-containing capping layer is located on top of the silicon-germanium capping layer.

8. The semiconductor structure as described in claim 6, characterized in that, The bottom surface of the tin-germanium-based photosensitive epitaxial structure is higher than the bottom surface of the p-type doped structure and the bottom surface of the n-type doped structure.

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