Battery sheet, solar cell, and photovoltaic module
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- RISEN ENERGY CO LTD
- Filing Date
- 2025-08-07
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, the area of the transparent conductive layer on the back of the battery cell is limited, which affects the efficiency of carrier collection and transport, leading to a decrease in battery performance.
A discontinuous transparent conductive layer is deposited on the side of the solar cell to prevent the side transparent conductive layer from conducting between the front and back layers, thereby reducing or eliminating the back isolation area and increasing the coverage area of the back transparent conductive layer.
This improves carrier collection efficiency and enhances the photoelectric conversion efficiency of solar cells and solar cells.
Smart Images
Figure CN224538655U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of photovoltaic technology, and more specifically, to a battery cell, a solar cell, and a photovoltaic module. Background Technology
[0002] The transparent conductive oxide (TCO) layer in a solar cell is a material located on the surface of the cell. It must ensure sufficient light transmittance to allow as much light as possible to reach the cell, while also possessing good conductivity to effectively collect the generated current. Since the front and back sides of the cell have different polarities (collecting electrons and holes respectively), the TCO layers on the front and back sides cannot be directly conductive to avoid short circuits. The TCO layer is often fabricated using a vapor deposition process. In related technologies, a carrier plate is used to support the edges of the cell during TCO deposition before the layer is formed. The TCO layer is distributed on the front, back, and sides of the cell. The areas of the cell supported by the carrier plate cannot have the TCO layer deposited, forming isolation regions. In related technologies, the isolation region on the back side of the cell needs to be arranged along the edge of the back side to form a closed structure to ensure that the TCO layers on the front and back sides are not conductive. Therefore, the isolation region area is relatively large, limiting the area of the TCO layer on the back side. This affects the collection and transport efficiency of charge carriers, thus impacting cell performance. Utility Model Content
[0003] The purpose of this application is to provide a battery cell, a solar cell, and a photovoltaic module that improves the carrier collection efficiency of the battery cell and enhances battery performance.
[0004] The embodiments of this application can be implemented as follows: In a first aspect, this application provides a solar cell including a silicon substrate and a transparent conductive layer. The silicon substrate has a first surface and a second surface opposite to each other, and a side surface located between the edge of the first surface and the edge of the second surface. The transparent conductive layer includes a first transparent conductive layer, a second transparent conductive layer and a third transparent conductive layer. The first transparent conductive layer is disposed on the first surface, the second transparent conductive layer is disposed on the second surface, and the third transparent conductive layer is disposed on the side surface. The third transparent conductive layer is discontinuous in the thickness direction of the silicon substrate.
[0005] In an optional embodiment, a plurality of pyramid structures are formed on the first surface, the second surface, and the side surface, and the pyramid structure on the side surface has a slope near the first surface and a slope near the second surface. On at least part of the pyramid structure on the side, the slope near the first surface is covered with a third transparent conductive layer, while the slope near the second surface is not covered with the third transparent conductive layer.
[0006] In an optional embodiment, the silicon substrate further has a transition slope connecting the second surface and the side surface, and the transparent conductive layer further includes a fourth transparent conductive layer, which is disposed on the transition slope and connected to the second transparent conductive layer, and the thickness of the fourth transparent conductive layer gradually decreases from the side closer to the second surface to the side closer to the side surface.
[0007] In an optional embodiment, the thickness of the fourth transparent conductive layer gradually decreases from 30~90nm to 0nm.
[0008] In an optional embodiment, the silicon substrate includes a first doped silicon layer, a first intrinsic silicon layer, a substrate layer, a second intrinsic silicon layer, and a second doped silicon layer stacked sequentially along the thickness direction. The first doped silicon layer forms a first surface, and the second doped silicon layer forms a second surface. The surface of the substrate layer is textured.
[0009] In an optional embodiment, the thickness of the first intrinsic silicon layer and the second intrinsic silicon layer is 1~10nm, and the thickness of the first doped silicon layer and the second doped silicon layer is 5~25nm.
[0010] In an optional embodiment, the maximum distance between the edge of the second transparent conductive layer and the edge of the second surface is less than 0.2 mm.
[0011] In an optional embodiment, the second surface of the silicon substrate has a plurality of support regions, which are spaced apart along the edge of the second surface. The second transparent conductive layer covers the other areas of the second surface except for the support regions. The width of the support regions is less than 0.2 mm, wherein the width direction of the support regions is perpendicular to the edge of the adjacent second surface.
[0012] Secondly, this application provides a solar cell, including a first electrode, a second electrode, and a cell according to any of the foregoing embodiments, wherein the first electrode is disposed on a first transparent conductive layer and the second electrode is disposed on a second transparent conductive layer.
[0013] Thirdly, this application provides a photovoltaic module, including the solar cell of the aforementioned embodiments.
[0014] The beneficial effects of the battery cells, solar cells, and photovoltaic modules provided in this application include: The solar cell provided in this application embodiment includes a silicon substrate and a transparent conductive layer. The silicon substrate has a first surface and a second surface opposite to each other, and a side surface located between the edge of the first surface and the edge of the second surface. The transparent conductive layer includes a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer. The first transparent conductive layer is disposed on the first surface, the second transparent conductive layer is disposed on the second surface, and the third transparent conductive layer is disposed on the side surface. The third transparent conductive layer is discontinuous in the thickness direction of the silicon substrate. Because the third transparent conductive layer on the side surface is discontinuous in the thickness direction of the silicon substrate, the first transparent conductive layer cannot conduct electricity with the second transparent conductive layer through the third transparent conductive layer on the side surface. Since the third transparent conductive layer itself cannot form a conductive path, there is no need to form a closed isolation region at the edge of the second surface to create a barrier. The second transparent conductive layer can cover a larger area on the second surface, even extending to the side surface of the solar cell. A larger area of the second transparent conductive layer can better collect charge carriers, thus improving battery performance.
[0015] The solar cell provided in this application includes a first electrode, a second electrode, and the aforementioned solar cell. The first electrode is disposed on a first transparent conductive layer, and the second electrode is disposed on a second transparent conductive layer. This solar cell has a high photoelectric conversion efficiency.
[0016] The photovoltaic module provided in this application includes the aforementioned solar cell, and therefore also has a high photoelectric conversion efficiency. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a first schematic diagram of a battery cell in the related technology; Figure 2 This is a schematic diagram of the back side of a solar cell in a related technology; Figure 3 This is a schematic diagram of a battery cell in one embodiment of this application; Figure 4 This is a scanning electron microscope image of the third transparent conductive layer on the side surface in one embodiment of this application; Figure 5 This is a schematic diagram showing the distribution of the second transparent conductive layer of the battery cell in one embodiment of this application; Figure 6 Please provide a cross-sectional view of the silicon substrate in one embodiment. Figure 7 This is a schematic diagram of a carrier device in one embodiment of this application; Figure 8 This is a schematic diagram of a carrier device supporting a silicon substrate in one embodiment of this application.
[0019] Icons: 100-Silicon substrate; 101-First surface; 102-Second surface; 103-Side surface; 104-Transition slope; 105-Pyramid structure; 106-Isolation region; 107-Support region; 110-First doped silicon layer; 120-First intrinsic silicon layer; 130-Substrate layer; 140-Second intrinsic silicon layer; 150-Second doped silicon layer; 200-Transparent conductive layer; 210-First transparent conductive layer; 220-Second transparent conductive layer; 230-Third transparent conductive layer; 240-Fourth transparent conductive layer; 300-Supporting device; 310-Frame; 311-Inner sidewall; 312-Long side beam; 313-Short side beam; 320-Enclosure part; 321-Shielding surface; 322-Guide slope; 323-End face; 330-Support part; 331-Support surface. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0023] In the description of this application, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the utility model product is usually placed in during use, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0024] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0025] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0026] In related technologies, a carrier device is used to support the entire edge of the silicon substrate, and then a transparent conductive layer is deposited on the front, back and side of the silicon substrate. Figure 1 This is a first schematic diagram of a battery cell in the related technology; Figure 2 This is a schematic diagram of the back side of a solar cell in a related technology. For example... Figure 1 and Figure 2 As shown, the edge of the back side (lower surface during thin film deposition) of the silicon substrate 100 is supported by the support device, preventing the deposition of the transparent conductive layer 200. Therefore, the supported area on the silicon substrate 100 forms an isolation region 106. The isolation region 106 extends along the edge to form a closed structure, thus ensuring that the transparent conductive layers 200 on the front and back sides are not conductive. It should be understood that, for ease of reading, Figure 2 The pyramid structure on the solar cell is omitted in this design. In related technologies, the way the carrier device supports the silicon substrate 100 results in a smaller coverage area of the transparent conductive layer 200 on the back of the solar cell. This affects the collection and transport efficiency of charge carriers, thus impacting battery performance.
[0027] To address the issue of insufficient coverage area of the transparent conductive layer 200 on the back of the solar cell, this application provides a solar cell that deposits a discontinuous transparent conductive layer 200 on the side of a silicon substrate 100, preventing the transparent conductive layers 200 on the front and back of the silicon substrate 100 from conducting through the side transparent conductive layers 200. Therefore, without relying on forming a large-area isolation region 106 on the back of the silicon substrate 100, the coverage area of the transparent conductive layer 200 on the back of the silicon substrate 100 is larger, which is beneficial for improving cell performance. Furthermore, this application also provides a solar cell and a photovoltaic module, including the aforementioned solar cell. This application further provides a support device for fabricating the aforementioned solar cell.
[0028] Figure 3 This is a schematic diagram of a battery cell in one embodiment of this application. Figure 3As shown, the solar cell provided in this embodiment includes a silicon substrate 100 and a transparent conductive layer 200. The silicon substrate 100 has a first surface 101 (e.g., the front surface) and a second surface 102 (e.g., the back surface) facing each other, and a side surface 103 located between the edge of the first surface 101 and the edge of the second surface 102. The transparent conductive layer 200 includes a first transparent conductive layer 210, a second transparent conductive layer 220, and a third transparent conductive layer 230; wherein, the first transparent conductive layer 210 is disposed on the first surface 101, the second transparent conductive layer 220 is disposed on the second surface 102, and the third transparent conductive layer 230 is disposed on the side surface 103. The third transparent conductive layer 230 is discontinuous in the thickness direction of the silicon substrate 100. It can be seen that, because the third transparent conductive layer 230 is discontinuous in the thickness direction of the silicon substrate 100, the first transparent conductive layer 210 and the second transparent conductive layer 220 cannot conduct through the third transparent conductive layer 230. In this case, the second transparent conductive layer 220 can cover as much of the second surface 102 of the silicon substrate 100 as possible, without needing to... Figure 1 In the related technologies shown, a large-area isolation region 106 is intentionally formed on the silicon substrate 100. Therefore, the solar cell of this application can increase the carrier collection efficiency of the second transparent conductive layer 220, thereby improving the battery performance.
[0029] Optionally, the first surface 101 and the second surface 102 are parallel to each other. In this embodiment, a plurality of pyramid structures 105 are formed on the first surface 101, the second surface 102, and the side surface 103. The pyramid structures 105 on the side surface 103 have a slope near the first surface 101 and a slope near the second surface 102. At least a portion of the pyramid structures 105 on the side surface 103 are covered with a third transparent conductive layer 230 on the slope near the first surface 101, but not on the slope near the second surface 102. It can be understood that when the third transparent conductive layer 230 is not covered on the slope of the pyramid structure 105 near the second surface 102, the third transparent conductive layer 230 is broken in the thickness direction of the silicon substrate 100, i.e., discontinuously distributed, so that the first transparent conductive layer 210 and the second transparent conductive layer 220 cannot conduct through the third transparent conductive layer 230. Figure 4 This is a scanning electron microscope (SEM) image of the third transparent conductive layer 230 on the side surface 103 in one embodiment of this application. Figure 4 As can be seen, the upward-facing slope of the pyramid structure 105 (towards the second surface 102) is covered with a third transparent conductive layer 230, while the downward-facing slope (towards the first surface 101) exposes the silicon substrate 100.
[0030] It should be noted that, for ease of reference, Figure 3 The pyramid structure 105 was enlarged in the image. Figure 3The ratio of the pyramid structure 105 to the silicon substrate 100 in the figure is not the same as the actual ratio.
[0031] Optionally, the silicon substrate 100 further includes a transition slope 104 connecting the second surface 102 and the side surface 103. The transparent conductive layer 200 also includes a fourth transparent conductive layer 240, which is disposed on the transition slope 104. The thickness of the fourth transparent conductive layer 240 gradually decreases from the side closer to the second surface 102 to the side surface 103. The fourth transparent conductive layer 240 is conductive to the second transparent conductive layer 220 and also functions to collect charge carriers. Therefore, it can improve the overall charge carrier collection efficiency of the solar cell to a certain extent, thereby improving the battery performance.
[0032] Optionally, the thickness of the fourth transparent conductive layer 240 gradually decreases from 30 to 90 nm to 0 nm, for example, from 80 nm to 0 nm. That is, the fourth transparent conductive layer 240 gradually thins from the end connected to the second transparent conductive layer 220 toward the end closer to the side 103.
[0033] In this embodiment, since the silicon substrate 100 needs to be supported on the second surface 102 when depositing the transparent conductive layer 200, there may still be areas at the edge of the second surface 102 of the silicon substrate 100 that are not covered by the second transparent conductive layer 220. Figure 5 This is a schematic diagram showing the distribution of the second transparent conductive layer 220 of the battery cell in one embodiment of this application. Figure 5 As shown, optionally, the maximum distance between the edge of the second transparent conductive layer 220 and the edge of its adjacent second surface 102 is less than 0.2 mm. It should be understood that the distance between the edge of the second transparent conductive layer 220 and the edge of its adjacent second surface 102 is the width of the area (or mask area) at the edge of the second surface 102 not covered by the second transparent conductive layer 220. Limiting the maximum distance between the edge of the second transparent conductive layer 220 and the edge of the second surface 102, i.e. limiting the width of the area on the second surface 102 not covered by the second transparent conductive layer 220, and controlling this width to less than 0.2 mm, ensures that the second transparent conductive layer 220 has a large coverage area.
[0034] Specifically, the second surface 102 of the silicon substrate 100 has multiple support regions 107, which are spaced apart along the edge of the second surface 102. The second transparent conductive layer 220 covers the other areas of the second surface 102 except for the support regions 107. The width W1 of each support region 107 is less than 0.2 mm, and the width direction of each support region 107 is perpendicular to the edge of its adjacent second surface 102. In this embodiment, by providing multiple support regions 107, the total support area 331 can be reduced, allowing the second transparent conductive layer 220 to cover a larger area and improving the carrier collection efficiency of the second transparent conductive layer 220. In this embodiment, the silicon substrate 100 is a rectangular sheet with two support regions 107 on each short side and four support regions 107 on each long side, thus ensuring the stability of the support.
[0035] Figure 6 Please provide a cross-sectional view of the silicon substrate 100 in one embodiment. For example... Figure 6 As shown, the solar cell in this embodiment is a heterojunction solar cell. The silicon substrate 100 includes a first doped silicon layer 110, a first intrinsic silicon layer 120, a substrate layer 130, a second intrinsic silicon layer 140, and a second doped silicon layer 150, which are sequentially stacked along the thickness direction. The first doped silicon layer 110 forms a first surface 101, and the second doped silicon layer 150 forms a second surface 102. The surface of the substrate layer 130 is textured, and the film covering the substrate layer 130 forms a pyramid structure 105 following the undulations of the textured surface. For easier viewing, Figure 6 The pyramid structure 105 is omitted from the text.
[0036] Optionally, the thickness of the first intrinsic silicon layer 120 and the second intrinsic silicon layer 140 is 1~10nm, and the thickness of the first doped silicon layer 110 and the second doped silicon layer 150 is 5~25nm.
[0037] This application also provides a solar cell (not shown in the figure), including a first electrode, a second electrode, and a cell of any of the foregoing embodiments. The first electrode is disposed on a first transparent conductive layer 210, and the second electrode is disposed on a second transparent conductive layer 220.
[0038] This application also provides a photovoltaic module (not shown in the figure), which includes the solar cell provided in the above embodiment, and multiple solar cells can be connected in series or in parallel.
[0039] Figure 7 This is a schematic diagram of the support device 300 in one embodiment of this application; Figure 8 This is a schematic diagram of a carrier device 300 supporting a silicon substrate 100 in one embodiment of this application. Figure 7 and Figure 8As shown, using the support device 300 provided in this embodiment, a structure can be formed as follows: Figure 3 The embodiment features a discontinuous third transparent conductive layer 230. The carrier device 300 provided in this application embodiment is used to carry the silicon substrate 100 to be coated. The carrier device 300 includes a frame 310, a blocking portion 320, and a support portion 330. The blocking portion 320 is disposed on the frame 310 and protrudes from the inner sidewall 311 of the frame 310, extending along the frame 310 to form a closed structure. Multiple support portions 330 are disposed on the blocking portion 320 and spaced apart along the blocking portion 320. The support portions 330 protrude away from the inner sidewall 311, and are used to collectively support the edge of the silicon substrate 100 along a first direction perpendicular to the plane of the frame 310. The blocking portion 320 is used to cover the gap between the edge of the silicon substrate 100 and the frame 310. Figure 7 In the middle, the first direction is perpendicular to the display plane; in Figure 8 In this context, the first direction refers to the vertical direction. When the supporting device 300 supports the silicon substrate 100, the first direction is the thickness direction of the silicon substrate 100.
[0040] When the support device 300 supports the silicon substrate 100, the support portion 330 supports the edge of the second surface 102 of the silicon substrate 100, and a gap is formed between the side surface 103 of the silicon substrate 100 and the inner sidewall 311 of the frame 310. The enclosure portion 320 blocks the lower opening of the gap, preventing the process gas from entering the gap from bottom to top for deposition. The process gas can only enter the gap from top to bottom through the upper opening. Since the process gas tends to move in a single direction from top to bottom within the gap, the third transparent conductive layer 230 is deposited only on the slope near the first surface 101 (i.e., the upward slope) of at least a portion of the pyramid structure 105 of the side surface 103, while no transparent conductive layer is deposited on the slope near the second surface 102 (i.e., the downward slope). This makes the third transparent conductive layer 230 discontinuous in the thickness direction of the silicon substrate 100, and the transparent conductive layers 200 on the first surface 101 and the second surface 102 of the silicon substrate 100 cannot conduct through the transparent conductive layer 200 on the side 103.
[0041] In this embodiment, the frame 310 includes two long side beams 312 and two short side beams 313, which together form a rectangular frame 310. Since the enclosure portion 320 extends along the frame 310, it also forms a rectangular frame shape. In this embodiment, each long side beam 312 and each short side beam 313 is provided with at least one support portion 330; specifically, each long side beam 312 has four support portions 330 on its enclosure portion 320, and each short side beam 313 has two support portions 330 on its enclosure portion 320. The number and distribution of the support portions 330 can be increased or decreased as needed.
[0042] In this embodiment, the support portion 330 has a support surface 331 for supporting the silicon substrate 100, the support surface 331 being perpendicular to the first direction. The enclosure portion 320 has a guide slope 322, the guide slope 322 having a first end near the inner sidewall 311 and a second end away from the inner sidewall 311. The first end is flush with the support surface 331 in the first direction, and the second end is lower than the support surface 331 in the first direction. In this embodiment, since the enclosure portion 320 may block the gap and potentially also block part of the second surface 102 of the silicon substrate 100, the guide slope 322 allows process gas to enter the second surface 102 above the guide slope 322 for deposition, thereby increasing the coverage area of the second transparent conductive layer 220 and improving battery performance.
[0043] Optionally, the included angle A between the support surface 331 and the guide slope 322 is 1° to 89°. Further, the included angle A can be selected as 30° to 60°. It can be understood that the larger the included angle A, the easier it is for process gas to enter between the guide slope 322 and the second surface 102, and the larger the coverage area of the second transparent conductive layer 220. However, the risk of process gas entering the gap from the lower end of the gap is also greater.
[0044] Furthermore, the enclosure portion 320 has a shielding surface 321, which is in the same spatial plane as the support surface 331. One end of the shielding surface 321 is connected to the inner sidewall 311, and the other end is connected to the first end of the guide slope 322. The shielding surface 321 is used to face the gap between the silicon substrate 100 and the frame 310. It can be understood that if the first end of the guide slope 322 extends to the inner sidewall 311 of the frame 310, process gas may enter the gap from the lower end of the gap. By providing the shielding surface 321 and covering the lower opening of the gap, process gas will not enter the gap from the lower end of the gap, reducing the risk of the third transparent conductive layer 230 being deposited on the downward slope of the pyramid structure 105, that is, reducing the risk of the third transparent conductive layer 230 being continuous in the thickness direction of the silicon substrate 100.
[0045] Furthermore, the end of the enclosure portion 320 away from the frame 310 has an end face 323, which is parallel to the first direction, and one end of the end face 323 in the first direction is connected to the second end of the guide slope 322.
[0046] In an optional embodiment, the width of the support surface 331 is 0.1~0.2mm, wherein the width direction of the support surface 331 is perpendicular to the first direction and the extension direction of the frame 310. Figure 8 In the middle, the width direction of the support surface 331 is the left and right direction. The smaller the width of the support surface 331, the smaller the area, and the larger the coverage area of the second transparent conductive layer 220, and the stronger the ability to collect charge carriers. However, if the width of the support surface 331 is too small, it may lead to a decrease in the reliability of the support.
[0047] In this embodiment, the inner sidewall 311 has a top edge and a bottom edge opposite each other in a first direction. The bottom edge of the inner sidewall 311 is connected to the enclosure portion 320, and the distance L between the top edge and the bottom edge in the first direction is 0.7~1.5mm. This allows the top edge of the inner sidewall 311 to be higher than the first surface 101 of the silicon substrate 100. The upper end of the inner sidewall 311 can guide the process gas, allowing the process gas to enter the gap downwards and deposit downwards in the gap to form a discontinuous third transparent conductive layer 230. If the height of the inner sidewall 311 is too low, the process gas may be deposited at other angles on the side surface 103, increasing the risk of discontinuity of the third transparent conductive layer 230.
[0048] It is understandable that when depositing the transparent conductive layer 200 on the silicon substrate 100, the width of the gap between the side surface 103 of the silicon substrate 100 and the frame 310 needs to be small. This ensures that the process gas entering the gap moves and deposits from top to bottom, which in turn ensures that the third transparent conductive layer 230 is deposited on the upward slope of the pyramid structure 105 of the side surface 103, while the downward slope does not have the third transparent conductive layer 230 deposited. Optionally, the width W2 of the gap between the side surface 103 of the silicon substrate 100 and the frame 310 is less than 0.1 mm.
[0049] In summary, embodiments of this application provide a battery cell, a solar cell, and a photovoltaic module. The battery cell includes a silicon substrate 100 and a transparent conductive layer 200. The silicon substrate 100 has a first surface 101 and a second surface 102 opposite to each other, and a side surface 103 located between the edge of the first surface 101 and the edge of the second surface 102. The transparent conductive layer 200 includes a first transparent conductive layer 210, a second transparent conductive layer 220, and a third transparent conductive layer 230. The first transparent conductive layer 210 is disposed on the first surface 101, the second transparent conductive layer 220 is disposed on the second surface 102, and the third transparent conductive layer 230 is disposed on the side surface 103. The third transparent conductive layer 230 is discontinuous in the thickness direction of the silicon substrate 100. Because the third transparent conductive layer 230 located on the side surface 103 is discontinuous in the thickness direction of the silicon substrate 100, the first transparent conductive layer 210 cannot conduct electricity with the second transparent conductive layer 220 through the third transparent conductive layer 230 on the side surface 103. Since the third transparent conductive layer 230 itself cannot form a conductor, there is no need to form a closed isolation region 106 at the edge of the second surface 102 to create a barrier. The second transparent conductive layer 220 can cover a larger area of the second surface 102, and even extend to the side 103 of the cell. The larger area of the second transparent conductive layer 220 can better collect charge carriers, thus improving cell performance.
[0050] The solar cell provided in this application includes a first electrode, a second electrode, and the aforementioned solar cell. The first electrode is disposed on a first transparent conductive layer 210, and the second electrode is disposed on a second transparent conductive layer 220. This solar cell has a high photoelectric conversion efficiency.
[0051] The photovoltaic module provided in this application includes the aforementioned solar cell, and therefore also has a high photoelectric conversion efficiency.
[0052] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A battery cell, characterized in that, The device includes a silicon substrate and a transparent conductive layer. The silicon substrate has opposing first and second surfaces, and a side surface located between the edge of the first surface and the edge of the second surface. The transparent conductive layer includes a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer. The first transparent conductive layer is disposed on the first surface, the second transparent conductive layer is disposed on the second surface, and the third transparent conductive layer is disposed on the side surface. The third transparent conductive layer is discontinuous in the thickness direction of the silicon substrate.
2. The battery cell according to claim 1, characterized in that, A plurality of pyramid structures are formed on the first surface, the second surface, and the side surface, and the pyramid structure on the side surface has a slope near the first surface and a slope near the second surface; At least a portion of the pyramid structure on the side surface is covered with the third transparent conductive layer on the slope near the first surface, while the slope near the second surface is not covered with the third transparent conductive layer.
3. The battery cell according to claim 1, characterized in that, The silicon substrate also has a transition slope connecting the second surface and the side surface. The transparent conductive layer further includes a fourth transparent conductive layer, which is disposed on the transition slope and connected to the second transparent conductive layer. The thickness of the fourth transparent conductive layer gradually decreases from the side closer to the second surface to the side closer to the side surface.
4. The battery cell according to claim 3, characterized in that, The thickness of the fourth transparent conductive layer gradually decreases from 30~90nm to 0nm.
5. The battery cell according to claim 1, characterized in that, The silicon substrate includes a first doped silicon layer, a first intrinsic silicon layer, a substrate layer, a second intrinsic silicon layer, and a second doped silicon layer stacked sequentially along the thickness direction. The first doped silicon layer forms the first surface, and the second doped silicon layer forms the second surface. The surface of the substrate layer is textured.
6. The battery cell according to claim 5, characterized in that, The thickness of the first intrinsic silicon layer and the second intrinsic silicon layer is 1~10nm, and the thickness of the first doped silicon layer and the second doped silicon layer is 5~25nm.
7. The battery cell according to claim 1, characterized in that, The maximum distance between the edge of the second transparent conductive layer and the edge of the adjacent second surface is less than 0.2 mm.
8. The battery cell according to claim 7, characterized in that, The second surface of the silicon substrate has a plurality of support regions, which are spaced apart along the edge of the second surface. The second transparent conductive layer covers the other areas of the second surface except for the support regions. The width of the support regions is less than 0.2 mm, and the width direction of the support regions is perpendicular to the edge of the adjacent second surface.
9. A solar cell, characterized in that, It includes a first electrode, a second electrode, and a battery cell according to any one of claims 1-8, wherein the first electrode is disposed on the first transparent conductive layer, and the second electrode is disposed on the second transparent conductive layer.
10. A photovoltaic module, characterized in that, Includes the solar cell as described in claim 9.