Display substrate and display device

Abstract

A display substrate and a display device. The display substrate has a plurality of pixel units, each of the plurality of pixel units includes a plurality of sub-pixels, and the display substrate includes a substrate substrate, a pixel definition layer, and a spacer layer; the pixel definition layer is located on one side of the substrate substrate and includes a plurality of sub-pixel openings for the plurality of sub-pixels and a plurality of isolation grooves between the plurality of sub-pixel openings; the spacer layer is located on the side of the pixel definition layer away from the substrate substrate and includes a plurality of spacers; wherein in a direction perpendicular to the substrate substrate, the plurality of spacers do not overlap the plurality of isolation grooves. The display substrate has a higher production yield and better display effect.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0002] In the field of organic light-emitting diode (OLED) displays, Tandem OLED technology is used to extend the standby time and lifespan of display screens. The core principle of this technology is to connect multiple light-emitting units in series through a charge generation layer (CGL) to form a stacked device. Compared to traditional single-layer OLEDs, Tandem technology can significantly improve display brightness, extend lifespan, and reduce power consumption. Utility Model Content

[0003] At least one embodiment of this disclosure provides a display substrate having a plurality of pixel units, wherein each of the plurality of pixel units includes a plurality of sub-pixels, the display substrate including a substrate, a pixel defining layer, and a spacer layer; the pixel defining layer is located on one side of the substrate and includes a plurality of sub-pixel openings for the plurality of sub-pixels and a plurality of isolation grooves located between the plurality of sub-pixel openings; the spacer layer is located on the side of the pixel defining layer away from the substrate and includes a plurality of spacers; wherein, in a direction perpendicular to the substrate, the plurality of spacers and the plurality of isolation grooves do not overlap.

[0004] For example, in a display substrate provided in at least one embodiment of this disclosure, at least one spacer is provided for every two pixel units in the plurality of pixel units.

[0005] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a pixel circuit layer, a planarization layer, and a plurality of first electrodes; the pixel circuit layer is disposed on the substrate and includes a plurality of pixel circuits; the planarization layer is disposed on the side of the pixel circuit layer away from the substrate and includes a plurality of vias that expose the plurality of pixel circuits; the plurality of first electrodes are disposed on the side of the planarization layer away from the substrate; wherein the pixel defining layer is disposed on the side of the plurality of first electrodes away from the substrate; the plurality of sub-pixel openings expose the plurality of first electrodes; the plurality of first electrodes are electrically connected to the plurality of pixel circuits through the plurality of vias; the plurality of spacers includes a first spacer, and in a direction perpendicular to the substrate, the first spacer does not overlap with the plurality of vias.

[0006] For example, in a display substrate provided in at least one embodiment of the present disclosure, each of the plurality of pixel units includes a plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel and two third color sub-pixels, and the first spacer is disposed at least between a first color sub-pixel and a second color sub-pixel adjacent along a first direction and between two third color sub-pixels adjacent along a second direction, wherein the first direction is perpendicular to the second direction.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of spacers further includes a second spacer, which overlaps at least partially with the plurality of vias in a direction perpendicular to the substrate, and the planar dimension of the second spacer is larger than the planar dimension of the first spacer.

[0008] For example, in at least one embodiment of the display substrate provided in this disclosure, the aspect ratio of the planar shape of the second spacer is greater than the aspect ratio of the planar shape of the first spacer.

[0009] For example, in a display substrate provided in at least one embodiment of the present disclosure, each of the plurality of pixel units includes a plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel and two third color sub-pixels, and the second spacer is disposed at least between two adjacent third color sub-pixels along a first direction and between a first color sub-pixel and a second color sub-pixel along a second direction, wherein the first direction is perpendicular to the second direction.

[0010] For example, in at least one embodiment of the display substrate provided in this disclosure, the longitudinal direction of the planar shape of the second spacer is along the first direction.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of spacers further includes a second spacer, which overlaps at least partially with the plurality of vias in a direction perpendicular to the substrate, and the plurality of spacers further includes a third spacer disposed adjacent to the second spacer.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, each of the plurality of pixel units includes a plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels. The second spacer and the third spacer are at least disposed between two adjacent third color sub-pixels along a first direction and between a first color sub-pixel and a second color sub-pixel along a second direction. The first direction is perpendicular to the second direction, and the second spacer and the third spacer are arranged along the first direction.

[0013] For example, in at least one embodiment of the display substrate provided in this disclosure, the second spacer and the third spacer have the same planar shape and planar dimensions.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels includes a first color sub-pixel, and the plurality of isolation trenches include a first isolation trench and a second isolation trench that partially surround the sub-pixel opening of the first color sub-pixel, wherein the first isolation trench and the second isolation trench are spaced apart.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels includes a third color sub-pixel adjacent to the first color sub-pixel, the first isolation groove and the second isolation groove have a first interval, and the first interval is configured as a sub-pixel opening facing the third color sub-pixel.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, the subpixel opening of the third color subpixel includes a long side and a short side, and the plurality of isolation grooves further includes a third isolation groove adjacent to the short side.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel defining layer further includes a plurality of isolation openings located between the plurality of sub-pixel openings. In a direction perpendicular to the substrate, the plurality of spacers do not overlap with the plurality of isolation openings. The sidewalls of the plurality of isolation trenches have a first slope angle, and the sidewalls of the plurality of isolation openings have a second slope angle. The first slope angle is greater than the second slope angle.

[0018] For example, in at least one embodiment of the display substrate provided in this disclosure, the minimum distance between the plurality of isolation openings and the plurality of spacers is greater than the minimum distance between the plurality of isolation grooves and the plurality of spacers.

[0019] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a planarization layer and an inorganic insulating layer. The planarization layer is disposed on the side of the pixel circuit layer away from the substrate and includes a plurality of vias that expose the plurality of pixel circuits and an undercut groove disposed between the plurality of vias. The inorganic insulating layer is disposed on the side of the planarization layer away from the substrate and includes an inorganic groove that communicates with the undercut groove to form an undercut groove structure. At least a portion of the plurality of isolation grooves or at least a portion of the plurality of isolation openings exposes the undercut groove structure.

[0020] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels includes a second color sub-pixel, and the plurality of isolation openings includes a first isolation opening and a second isolation opening that partially surrounds the sub-pixel opening of the second color sub-pixel, wherein the first isolation opening and the second isolation opening are spaced apart.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels further includes a third color sub-pixel adjacent to the second color sub-pixel, the sub-pixel opening of the third color sub-pixel includes a long side and a short side, and the plurality of isolation openings further includes a third isolation opening adjacent to the long side.

[0022] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels further includes a first color sub-pixel adjacent to the third color sub-pixel, and the plurality of isolation slots include a first isolation slot and a second isolation slot that partially surround the sub-pixel opening of the first color sub-pixel, the first isolation slot and the second isolation slot having a first interval, the first interval being configured to face the third isolation opening.

[0023] For example, in a display substrate provided in at least one embodiment of this disclosure, for the isolation opening provided between adjacent second color sub-pixels and third color sub-pixels, the isolation opening is closer to the sub-pixel opening of the second color sub-pixel than the sub-pixel opening of the third color sub-pixel.

[0024] For example, in a display substrate provided in at least one embodiment of this disclosure, for the isolation opening provided between adjacent first color sub-pixels and third color sub-pixels, the isolation opening is closer to the sub-pixel opening of the third color sub-pixel than the sub-pixel opening of the first color sub-pixel.

[0025] For example, in a display substrate provided in at least one embodiment of this disclosure, the first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a green sub-pixel.

[0026] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1 This is a partial planar schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0029] Figure 2 This is a partial cross-sectional schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0030] Figure 3 This is a partial planar schematic diagram of another display substrate provided in at least one embodiment of the present disclosure;

[0031] Figure 4 for Figure 3 An enlarged schematic diagram of the display substrate at the dashed frame C1;

[0032] Figure 5 for Figure 3 An enlarged schematic diagram of the display substrate at the dashed box C2;

[0033] Figure 6 This is a partial cross-sectional schematic diagram of another display substrate provided in at least one embodiment of the present disclosure;

[0034] Figure 7 This is a partial planar schematic diagram of another display substrate provided in at least one embodiment of the present disclosure;

[0035] Figure 8 A partial plan view of another display substrate provided for at least one embodiment of the present disclosure;

[0036] Figure 9 for Figure 8 An enlarged schematic diagram of the display substrate at the dashed box B1;

[0037] Figure 10 for Figure 8 An enlarged schematic diagram of the display substrate at the dashed box B2;

[0038] Figure 11 for Figure 8 An enlarged schematic diagram of the display substrate at the dashed box B3;

[0039] Figure 12 for Figure 8 An enlarged view of the display substrate at the dashed box B4;

[0040] Figure 13 A cross-sectional schematic diagram of an isolation trench and an isolation opening in a display substrate provided in at least one embodiment of this disclosure; and

[0041] Figure 14 and Figure 15 This is a partial planar schematic diagram of different display substrates provided for at least one embodiment of the present disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0044] As mentioned earlier, tandem technology can significantly improve display brightness, extend lifespan, and reduce power consumption because tandem devices draw less current at the same brightness. However, the inventors of this disclosure discovered in their research that tandem devices are more sensitive at low grayscale levels, making them more prone to problems such as bright and dark spots. Traditional spacer settings cannot achieve sufficient support, resulting in a higher probability of dark or bright spots being formed due to scratches during the fabrication process, damaging the devices and affecting the display effect of the display substrate.

[0045] At least one embodiment of this disclosure provides a display substrate having a plurality of pixel units, wherein each of the plurality of pixel units includes a plurality of sub-pixels, and the display substrate includes a substrate, a pixel defining layer, and a spacer layer; the pixel defining layer is located on one side of the substrate and includes a plurality of sub-pixel openings for the plurality of sub-pixels and a plurality of isolation grooves located between the plurality of sub-pixel openings; the spacer layer is located on the side of the pixel defining layer away from the substrate and includes a plurality of spacers; wherein, in a direction perpendicular to the substrate, the plurality of spacers and the plurality of isolation grooves do not overlap.

[0046] In the embodiments of this disclosure, by setting the multiple spacers to not overlap with the multiple isolation grooves, it can be ensured that the multiple spacers have sufficient support height, preventing the multiple spacers from collapsing or other defects, thereby preventing defects such as film layer scratches from occurring during the fabrication of the display substrate, ensuring the structural integrity of the display substrate, and improving the fabrication yield and display effect of the display substrate.

[0047] The display substrate and display device provided in this disclosure will be described below through several specific embodiments.

[0048] This disclosure provides a display substrate in at least one embodiment. Figure 1 A partial planar schematic diagram of the display substrate is shown. Figure 2 A partial cross-sectional schematic diagram of the display substrate is shown, as follows: Figure 1 As shown, the display substrate has multiple pixel units P, and each pixel unit P includes multiple sub-pixels SP, such as multiple sub-pixels with different emission colors, such as red sub-pixels, blue sub-pixels, and green sub-pixels. Figure 2 As shown, the display substrate includes a substrate 110, a pixel defining layer 120, and a spacer layer 130, among other structures.

[0049] like Figure 1 and Figure 2 As shown, the pixel defining layer 120 is located on one side of the substrate 110 and includes a plurality of sub-pixel openings 121 for a plurality of sub-pixels SP and a plurality of isolation trenches 122 located between the plurality of sub-pixel openings 121; the plurality of sub-pixel openings 121 are used to define the light-emitting areas of the plurality of sub-pixels SP, and the plurality of isolation trenches 122 can block or even isolate the light-emitting materials of adjacent sub-pixels SP to avoid crosstalk between adjacent sub-pixels SP.

[0050] The spacer layer 130 is located on the side of the pixel defining layer 120 away from the substrate 110, and includes a plurality of spacers 131. The plurality of spacers 131 can serve as supports and protects. For example, during the fabrication of the display substrate, the plurality of spacers 131 can support the mask required for fabrication, thereby separating the mask from other structures on the display substrate and protecting the functional structures already formed on the display substrate.

[0051] In the direction perpendicular to the substrate 110, the multiple spacers 131 and the multiple isolation grooves 122 do not overlap. As a result, the multiple spacers 131 can have sufficient support height, preventing defects such as collapse of the multiple spacers 131, thereby preventing defects such as film layer scratches during the fabrication of the display substrate, ensuring the structural integrity of the display substrate, and improving the fabrication yield and display effect of the display substrate.

[0052] For example, in some embodiments, at least one spacer 131 is provided for every two pixel units P. For example, one spacer 131, two spacers 131, or more spacers 131 are provided for every two pixel units P. Thus, the density of the spacers 131 on the display substrate is sufficiently high to ensure adequate support.

[0053] For example, in some embodiments, such as Figure 2 As shown, the display substrate also includes a pixel circuit layer 140, a planarization layer 150, and multiple first electrodes E1, etc. The pixel circuit layer 140 is disposed on the substrate 110 and includes multiple pixel circuits 141. For example, each sub-pixel SP includes one pixel circuit 141 and one light-emitting device EM, and the pixel circuit 141 can drive the light-emitting device EM to emit light. For example, each pixel circuit 141 may include multiple transistors and at least one storage capacitor (not shown), and can be formed as a 2T1C (i.e., including two transistors and one storage capacitor), 3T1C (i.e., including three transistors and one storage capacitor), 7T1C (i.e., including seven transistors and one storage capacitor), 8T1C (i.e., including eight transistors and one storage capacitor), or 8T2C (i.e., including eight transistors and two storage capacitors), etc. For specific details, please refer to related technologies. The embodiments disclosed herein do not specifically limit the scope of the invention.

[0054] For example, such as Figure 2 As shown, a planarization layer 150 is disposed on the side of the pixel circuit layer 140 away from the substrate 110, for planarizing the pixel circuit layer 140 and providing a flat surface. The planarization layer 150 includes a plurality of vias 151 that expose a plurality of pixel circuits 141 respectively. A plurality of first electrodes E1 are disposed on the side of the planarization layer 150 away from the substrate 110. The plurality of first electrodes E1 are electrically connected to the plurality of pixel circuits 141 through the plurality of vias 151, for example, electrically connected to the output terminals of the plurality of pixel circuits 141, so as to connect the light-emitting device EM to the pixel circuit 141.

[0055] For example, such as Figure 2 As shown, the pixel limiting layer 120 is disposed on the side of the plurality of first electrodes E1 away from the substrate 110, and the plurality of sub-pixel openings 121 of the pixel limiting layer 120 expose the plurality of first electrodes E1 respectively. The light-emitting device EM also includes a light-emitting material layer E2 and a second electrode E3, and the light-emitting material layer E2 and the second electrode E3 are disposed at least in the sub-pixel openings 121.

[0056] For example, the first electrode E1 can be an anode, used to transmit pixel voltage, such as a high-level voltage. For example, depending on the color emitted by each sub-pixel SP, the light-emitting material layer E2 can include a red, green, or blue light-emitting layer, etc., and may also include auxiliary light-emitting layers, such as one or more of electron transport layers, electron injection layers, hole blocking layers, and charge generation layers. For example, in some embodiments, the light-emitting material layer E2 of each sub-pixel SP can include multiple light-emitting layers connected in series using charge generation layers, thereby forming a series-connected light-emitting device to improve the device's brightness, reduce power consumption, extend the device's lifespan, and extend the standby time of the display substrate. For example, the second electrode E3 can be a cathode, and the cathodes of multiple sub-pixels SP can be integrally connected to transmit a common voltage, such as a low-level voltage; thus, a voltage difference is generated between the first electrode E1 and the second electrode E2 to drive the light-emitting material layer E2 to emit light.

[0057] For example, in some embodiments, multiple isolation slots 122 can block or even isolate the light-emitting material layer E2 of adjacent sub-pixels SP, such as blocking or even isolating at least a portion of the light-emitting material layer E2, such as the charge generation layer, to avoid crosstalk between adjacent sub-pixels SP.

[0058] For example, in some embodiments, such as Figure 1 As shown, the plurality of spacers 131 include a first spacer 1311, which does not overlap with the plurality of vias 151 in a direction perpendicular to the substrate 110. For example, the plurality of spacers 131 may include a plurality of first spacers 1311, in which case the plurality of first spacers 1311 may have sufficient height to achieve a better support effect.

[0059] For example, in Figure 1 In this embodiment, a spacer 131 is provided for every two pixel units P. In this case, all spacers 131 can be implemented as first spacers 1311, that is, in the direction perpendicular to the substrate 110, each spacer 131 on the display substrate does not overlap with the multiple vias 151. Thus, the multiple spacers 131 on the display substrate have sufficient density and support height to achieve better support effect.

[0060] For example, in some embodiments, such as Figure 2As shown, each pixel unit P includes multiple sub-pixels SP, which may include a first color sub-pixel SP1, a second color sub-pixel SP2, and two third color sub-pixels SP3. A first spacer 1311 is at least disposed between one adjacent first color sub-pixel SP1 and one adjacent second color sub-pixel SP2 along the first direction R1 and between two adjacent third color sub-pixels SP3 along the second direction R2. The first direction R1 is perpendicular to the second direction R2. For example, in... Figure 2 In the diagram, the first direction R1 is shown as the column direction, and the second direction R2 is shown as the row direction. In other embodiments, the column direction and the row direction can be interchanged.

[0061] For example, in other embodiments, each pixel unit P may include a first color sub-pixel SP1, a second color sub-pixel SP2, and a third color sub-pixel SP3. The embodiments of this disclosure do not specifically limit the division / composition of pixel units P.

[0062] For example, in some embodiments, the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 are respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel; for example, the first color sub-pixel SP1 is a blue sub-pixel, the second color sub-pixel SP2 is a red sub-pixel, and the third color sub-pixel SP3 is a green sub-pixel; or, the first color sub-pixel SP1 is a red sub-pixel, the second color sub-pixel SP2 is a blue sub-pixel, and the third color sub-pixel SP3 is a green sub-pixel, and so on.

[0063] For example, such as Figure 2 As shown, multiple vias 151 are respectively disposed between two adjacent third-color sub-pixels SP3 along the first direction R1 and between one adjacent first-color sub-pixel SP1 and one adjacent second-color sub-pixel SP2 along the second direction R2. For example, every two vias 151 are disposed between two adjacent third-color sub-pixels SP3 along the first direction R1 and between one adjacent first-color sub-pixel SP1 and one adjacent second-color sub-pixel SP2 along the second direction R2. Thus, the placement positions of the multiple vias 151 are different from the placement positions of the multiple first spacers 1311 to avoid overlap between the first spacers 1311 and the vias 151.

[0064] For example, in some embodiments, such as Figure 2As shown, the pixel defining layer 120 may further include a plurality of isolation openings 123 located between the plurality of sub-pixel openings 121. In the direction perpendicular to the substrate 110, the plurality of spacers 131 and the plurality of isolation openings 123 do not overlap. The plurality of isolation openings 123 can also serve to block the light-emitting material layer E2. Thus, a plurality of isolation openings 123 and a plurality of isolation grooves 122 are simultaneously provided between the plurality of sub-pixels SP to fully realize the blocking effect and better reduce or even avoid crosstalk between the plurality of sub-pixels SP.

[0065] For example, Figure 13 A cross-sectional schematic diagram of the isolation groove 122 and the isolation opening 123 is shown, as follows. Figure 13 As shown, the sidewalls of the plurality of isolation grooves 122 have a first slope angle a1, and the sidewalls of the plurality of isolation openings 123 have a second slope angle a2, wherein the first slope angle a1 is greater than the second slope angle a2. Therefore, the plurality of isolation grooves 122 are steeper, which can significantly thin the light-emitting material layer E2, or even disconnect the light-emitting material layer E2, for example, disconnecting at least a portion of the light-emitting material layer E2, such as the charge-generating layer, to reduce crosstalk between adjacent sub-pixels; the plurality of isolation openings 123 can extend the extension distance of the light-emitting material layer E2 between adjacent sub-pixels to reduce crosstalk.

[0066] For example, in some embodiments, the first slope angle a1 can be 65°~80°, such as 65°, 70°, 75° or 80°, and the second slope angle a2 can be 15°~35°, such as 15°, 20°, 25° or 30°.

[0067] For example, such as Figure 13 As shown, in the direction perpendicular to the substrate 110, the depth L1 of the isolation trench 122 is less than the depth L2 of the isolation opening 123. During the fabrication of the display substrate, the isolation opening 123 can be formed using the same process as the sub-pixel opening 121, and the isolation trench 122 can be formed using an additional dry etching process, thereby forming isolation trenches 122 and isolation openings 123 with different morphologies.

[0068] For example, in some embodiments, the depth L1 of the isolation trench 122 can be 400nm to 750nm, such as 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm or 750nm, and the depth L2 of the isolation opening 123 can be 500nm to 1500nm, such as 700nm, 900nm, 1000nm, 1200nm or 1500nm.

[0069] For example, Figure 3 A cross-sectional schematic diagram of another display substrate provided in at least one embodiment of this disclosure is shown, such as... Figure 3As shown, in some embodiments, the plurality of spacers 131 include a first spacer 1311, which does not overlap with the plurality of vias 151 in a direction perpendicular to the substrate 110. In addition, the plurality of spacers 131 may also include a second spacer 1312, which at least partially overlaps with the plurality of vias 151 in a direction perpendicular to the substrate 110. In this case, the planar dimension of the second spacer 1312 is larger than the planar dimension of the first spacer 1321, that is, the area occupied by the second spacer 1312 on the display substrate is larger than the area occupied by the first spacer 1321 on the display substrate.

[0070] Since the second spacer 1312 at least partially overlaps with the plurality of through holes 151, the second spacer 1312 may sink at the overlapping position, resulting in insufficient height and difficulty in achieving a sufficient support effect. By designing the planar dimensions of the second spacer 1312 to be larger, at least part (e.g., most) of the second spacer 1312 can be prevented from overlapping with the through holes 151, thereby maintaining sufficient height and achieving a sufficient support effect.

[0071] For example, in some examples, such as Figure 3 As shown, the aspect ratio of the planar shape of the second spacer 1312 is greater than that of the planar shape of the first spacer 1321.

[0072] In the embodiments of this disclosure, the aspect ratio of a planar shape refers to the ratio of the dimension of the planar shape in the length direction to the dimension in the width direction (e.g., perpendicular to the length direction). The larger the aspect ratio of a planar shape, the more obvious the elongated characteristics of the shape.

[0073] By setting the aspect ratio of the planar shape of the second spacer 1312 to be greater than that of the planar shape of the first spacer 1321, the second spacer 1312 can extend over a larger range, thereby avoiding excessive overlap between the second spacer 1312 and the through hole 151. This ensures that most of the second spacer 1312 does not overlap with the through hole 151, thus maintaining sufficient height and achieving sufficient support.

[0074] For example, in some embodiments, such as Figure 3 As shown, the planar shape of the via 151 is dot-shaped, such as a circle or a square, and the aspect ratio of the via 151 is 1.

[0075] For example, the planar shape of the first spacer 1311 is dot-shaped, such as a circle or a square, and the aspect ratio of the first spacer 1311 is 1; the diameter / side length of the first spacer 1311 can be 8μm-12μm, such as 8μm, 9μm, 10μm, 11μm or 12μm.

[0076] For example, the planar shape of the second spacer 1312 is elongated, such as racetrack-shaped, elliptical, rounded rectangle, or rectangular. In this case, the aspect ratio of the planar shape of the second spacer 1312 is greater than 1, for example, 1.5, 2.0, 2.5, or 3.0. For example, the dimension of the second spacer 1312 along the width direction can be 8μm-12μm, for example, 8μm, 9μm, 10μm, 11μm, or 12μm. A portion of the second spacer 1312 overlaps with the via 151, while another portion does not overlap with the via 151. For example, the area occupied by the non-overlapping portion on the display substrate can be greater than or equal to or slightly smaller than the area occupied by the first spacer 1311 on the display substrate, so that the second spacer 1312 can achieve sufficient support.

[0077] For example, in Figure 3 In this embodiment, a spacer 131 is provided for every three pixel units P. The first spacer 1311 is positioned between a first-color sub-pixel SP1 and a second-color sub-pixel SP2 adjacent along the first direction R1, and between two third-color sub-pixels SP3 adjacent along the second direction R2. The second spacer 1312 is positioned between two third-color sub-pixels SP3 adjacent along the first direction R1, and between a first-color sub-pixel SP1 and a second-color sub-pixel SP2 adjacent along the second direction R2. Since multiple vias 151 are also respectively positioned between two third-color sub-pixels SP3 adjacent along the first direction R1 and between a first-color sub-pixel SP1 and a second-color sub-pixel SP2 adjacent along the second direction R2, the second spacer 1312 may overlap with the via 151. By designing the second spacer 1312 as described above, the support effect of the second spacer 1312 near the overlapping position can be guaranteed.

[0078] For example, such as Figure 3 As shown, the length direction of the planar shape of the second spacer 1312 is along the first direction R1. That is, the length direction of the planar shape of the second spacer 1312 points to the third color sub-pixel SP3, and the width direction of the planar shape of the second spacer 1312 points to the first color sub-pixel SP1 and the second color sub-pixel SP2. Thus, in Figure 3 In the middle, the second spacer 1312 is arranged along the column direction; if the second spacer 1312 is arranged along the row direction, the length of the second spacer 1312 is limited, or it may overlap with the isolation groove 122, affecting the support effect of the second spacer 1312.

[0079] For example, Figure 4 It shows Figure 3 An enlarged schematic diagram of the display substrate at the dashed frame C1, as shown in the image. Figure 4As shown, the length direction of the second spacer 1312 is the column direction, and the width direction is the row direction. The planar shape of the second spacer 1312 is racetrack-shaped, with an aspect ratio of approximately 2.0. For example, in other embodiments, the planar shape of the second spacer 1312 may also be elliptical, rectangular, or rounded rectangle, with an aspect ratio of 1.5, 2.0, 2.5, or 3.0, etc.

[0080] For example, such as Figure 4 As shown, the planar shape of the subpixel opening 121 of different color subpixels can be designed to be different. For example, the subpixel opening 121 of the first color subpixel SP1 is basically square, and the square has a chamfer at one corner, such as... Figure 4 As shown by the dashed circle, the subpixel opening 121 of the second color subpixel SP2 is basically square, and the subpixel opening 121 of the third color subpixel SP3 is basically rectangular. In other embodiments, the planar shape of the subpixel opening 121 of different color subpixels can also adopt other shapes or combinations of shapes, such as circles, ellipses, racetrack shapes, etc.

[0081] For example, Figure 5 It shows Figure 3 An enlarged schematic diagram of the display substrate at the dashed frame C2, as shown in the image. Figure 4 and Figure 5 As shown, the environments of the second septum 1312 at different locations are different; in Figure 4 As shown, the second spacer 1312 is located to the right of the sub-pixel opening 121 of the first color sub-pixel SP1, adjacent to the chamfer of the square of the sub-pixel opening 121, and to the left of the sub-pixel opening 121 of the second color sub-pixel SP2; Figure 5 As shown, the second spacer 1312 is located to the left of the sub-pixel opening 121 of the first color sub-pixel SP1, not adjacent to the chamfer of the square of the sub-pixel opening 121, and the second spacer 1312 is located to the right of the sub-pixel opening 121 of the second color sub-pixel SP2.

[0082] For example, in other embodiments, the display substrate may further include other barrier structures to improve the barrier effect on the light-emitting material layer E2. For example, Figure 6A cross-sectional schematic diagram of another display substrate provided in at least one embodiment of the present disclosure is shown. In some embodiments, the display substrate may further include an inorganic insulating layer 160 disposed between a planarization layer 150 and a plurality of first electrodes E1. The inorganic insulating layer 160 includes an inorganic groove 161. For example, the planarization layer 150 includes an undercut groove 152 disposed between a plurality of vias 151. The inorganic groove 161 communicates with the undercut groove 152 to form an undercut groove structure N1. The undercut groove structure N1 has a shape that is smaller at the top and larger at the bottom, so that when the light-emitting material layer E2 is formed above the undercut groove structure N1, it helps the light-emitting material layer E2 to be disconnected at the undercut groove structure N1.

[0083] For example, at least a portion of the plurality of isolation trenches 122 or at least a portion of the plurality of isolation openings 123 in the pixel defining layer 120 can expose the undercut groove structure N1, thereby increasing the depth of the isolation trenches 122 or the isolation openings 123, so that when the light-emitting material layer E2 extends into the undercut groove structure N1, it can be sufficiently disconnected by the undercut groove structure N1. Figure 6 The image shows an example where the isolation opening 123 exposes the undercut groove structure N1. In other embodiments, the isolation groove 122 may also expose the undercut groove structure N1.

[0084] For example, Figure 7 This diagram shows a partial planar schematic of another display substrate provided in at least one embodiment of the present disclosure, compared to... Figure 5 , Figure 7 The arrangement range of the inorganic insulating layer 160 and the inorganic groove 161 is shown, for example, as... Figure 7 As shown, the light gray area is the coverage area of ​​the inorganic insulating layer 160, and the blank area is the opening range of the inorganic groove 161. It can be seen that the inorganic groove 161 is fully disposed between adjacent sub-pixels SP and is exposed by multiple isolation openings 123 to have a better blocking effect.

[0085] For example, Figure 8 A cross-sectional schematic diagram of another display substrate provided in at least one embodiment of the present disclosure is shown, as follows: Figure 8 As shown, in some embodiments, the plurality of spacers 131 includes a first spacer 1311, which does not overlap with the plurality of vias 151 in a direction perpendicular to the substrate 110; in addition, the plurality of spacers 131 may also include a second spacer 1312, which at least partially overlaps with the plurality of vias 151 in a direction perpendicular to the substrate 110; the plurality of spacers 131 also includes a third spacer 1313 disposed adjacent to the second spacer 1312.

[0086] Since the second spacer 1312 overlaps at least partially with the multiple through holes 151, the second spacer 1312 may sink at the overlapping position, that is, the height is insufficient. By setting a third spacer 1313 next to the second spacer 1312, the second spacer 1312 and the third spacer 1313 can work together to achieve a supporting effect, so as to achieve sufficient support.

[0087] For example, such as Figure 8 As shown, for every three pixel units P, a first spacer 1311, a second spacer 1312, and a third spacer 1313 are provided. The first spacer 1311 is disposed between a first color sub-pixel SP1 and a second color sub-pixel SP2 adjacent along the first direction R1, and between two third color sub-pixels SP3 adjacent along the second direction R2. The second spacer 1312 and the third spacer 1313 are at least disposed between a first color sub-pixel SP1 and a second color sub-pixel SP3 adjacent along the first direction R1, and between a first color sub-pixel SP1 and a second color sub-pixel SP3 adjacent along the second direction R2. Between sub-pixels SP2; since multiple vias 151 are also respectively set between two adjacent third-color sub-pixels SP3 along the first direction R1 and between a first-color sub-pixel SP1 and a second-color sub-pixel SP2 along the second direction R2, the positions of the second spacer 1312 and the third spacer 1313 may overlap with the vias 151. However, the overall support effect of the second spacer 1312 and the third spacer 1313 is greater than or equal to or slightly less than the support effect of the first spacer 1311, thereby ensuring the overall support effect of the multiple spacers 131 on the display substrate.

[0088] For example, such as Figure 8 As shown, the second spacer 1312 and the third spacer 1313 can be arranged along the first direction R1 to ensure that the lengths of the second spacer 1312 and the third spacer 1313 do not overlap with the isolation groove 122. For example, the second spacer 1312 and the third spacer 1313 can be arranged tangentially to save arrangement space; or, in other embodiments, the second spacer 1312 and the third spacer 1313 can also be arranged at intervals to avoid overlapping with the through hole 151 as much as possible.

[0089] For example, Figure 9 It shows Figure 8 An enlarged view of the display substrate at the dashed box B1. Figure 10 It shows Figure 8 An enlarged view of the display substrate at the dashed box B2. Figure 11 It shows Figure 8 An enlarged view of the display substrate at the dashed box B3. Figure 12 It shows Figure 8An enlarged schematic diagram of the display substrate at the dashed box B4, as shown below. Figures 9-12 As shown, the second spacer 1312 is in different environments at different locations.

[0090] For example, in Figure 9 In the portion shown, the second spacer 1312 and the third spacer 1313 are located to the left of the sub-pixel opening 121 of the first color sub-pixel SP1 and to the right of the sub-pixel opening 121 of the second color sub-pixel SP2, with the chamfer of the square of the sub-pixel opening 121 of the first color sub-pixel SP1 facing upwards; Figure 10 In the portion shown, the second spacer 1312 and the third spacer 1313 are located to the right of the sub-pixel opening 121 of the first color sub-pixel SP1 and to the left of the sub-pixel opening 121 of the second color sub-pixel SP2, with the chamfer of the square of the sub-pixel opening 121 of the first color sub-pixel SP1 facing upwards; Figure 11 In the portion shown, the second spacer 1312 and the third spacer 1313 are located to the left of the sub-pixel opening 121 of the first color sub-pixel SP1 and to the right of the sub-pixel opening 121 of the second color sub-pixel SP2. The chamfer of the square of the sub-pixel opening 121 of the first color sub-pixel SP1 faces left and is adjacent to the second spacer 1312 and the third spacer 1313. Figure 12 As shown, the second spacer 1312 and the third spacer 1313 are located to the right of the sub-pixel opening 121 of the first color sub-pixel SP1 and to the left of the sub-pixel opening 121 of the second color sub-pixel SP2. The chamfer of the square of the sub-pixel opening 121 of the first color sub-pixel SP1 faces to the right and is adjacent to the second spacer 1312 and the third spacer 1313.

[0091] For example, such as Figures 8-12 As shown, the second septum 1312 and the third septum 1313 have the same planar shape and planar dimensions, resulting in higher structural uniformity of the second septum 1312 and the third septum 1313 during the manufacturing process. For example, in Figures 8-12 In one embodiment, the planar shape of the second spacer 1312 and the third spacer 1313 is circular, and the diameter of the circles of the second spacer 1312 and the third spacer 1313 is the same; in other embodiments, the planar shape of the second spacer 1312 and the third spacer 1313 may also be square, rectangular, etc., and the shape and size of the second spacer 1312 and the third spacer 1313 may also be different.

[0092] For example, in Figure 8In the embodiments, the first spacer 1311, the second spacer 1312 and the third spacer 1313 can all have the same planar shape and planar size, so that the multiple spacers 131 have higher structural uniformity during the preparation process.

[0093] For example, in some embodiments, reference Figure 11 The plurality of isolation slots 122 include a first isolation slot 1221 and a second isolation slot 1222 partially surrounding the sub-pixel opening 121 of the first color sub-pixel SP, with the first isolation slot 1221 and the second isolation slot 1222 spaced apart. For example, the first isolation slot 1221 and the second isolation slot 1222 have a first interval G1. That is, the plurality of isolation slots 122 are not closed, and there is a break between adjacent isolation slots 122 to ensure that the second electrode E2 is continuously disposed among the plurality of sub-pixels SP, preventing the second electrode E2 from breaking at the isolation slot 122 and causing the signal to fail to transmit normally; for example, the first interval G1 is set to face the sub-pixel opening 121 of the third color sub-pixel SP.

[0094] For example, refer to Figure 11 The subpixel opening 121 of the third color subpixel SP3 includes a long side SP31 and a short side SP32, and the plurality of isolation slots 122 also includes a third isolation slot 1223 adjacent to the short side SP32. For example, the subpixel opening 121 of the third color subpixel SP3 includes two long sides SP31 and two short sides SP32, and the plurality of isolation slots 122 includes a third isolation slot 1223 adjacent to each short side SP32. This can further block the light-emitting material layer E2 of adjacent third color subpixels SP3 and second color subpixels SP2, reducing or even avoiding crosstalk between adjacent third color subpixels SP3 and second color subpixels SP2.

[0095] For example, refer to Figure 11 The plurality of isolation slots 122 may further include a fourth isolation slot 1224 and a fifth isolation slot 1225. The first isolation slot 1221, the second isolation slot 1222, the fourth isolation slot 1224, and the fifth isolation slot 1225 are arranged together around the sub-pixel opening 121 of the first color sub-pixel SP, and there is a gap between each pair of adjacent isolation slots in the first isolation slot 1221, the second isolation slot 1222, the fourth isolation slot 1224, and the fifth isolation slot 1225. Figure 11 The diagram shows four intervals, each facing the subpixel opening 121 of the third color subpixel SP3 adjacent to the first color subpixel SP. Furthermore, each of the four intervals faces one of the four sides of the square of the subpixel opening 121 of the first color subpixel SP.

[0096] Therefore, the sub-pixel opening 121 of the first color sub-pixel SP is designed with breaks around its perimeter to ensure the connectivity of the second electrode E2.

[0097] For example, in some embodiments, the interval between any two adjacent isolation trenches in the first isolation trench 1221, the second isolation trench 1222, the fourth isolation trench 1224, and the fifth isolation trench 1225 is 2μm-10μm, such as 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, or 10μm, which can meet the process requirements and ensure the continuity of the second electrode E2.

[0098] For example, in some embodiments, such as Figure 2 As shown, the minimum distance D2 between the multiple isolation openings 123 and the multiple spacers 131 is greater than the minimum distance D1 between the multiple isolation grooves 122 and the multiple spacers 131. That is, the spacers 131 are kept as far away from the isolation openings 123 as possible to prevent the height of the spacers 131 from being affected; in addition, the distance between the spacers 131 and the isolation grooves 122 can be appropriately closer to improve the blocking effect of the isolation grooves 122.

[0099] For example, in some embodiments, the minimum distance D2 between the plurality of isolation openings 123 and the plurality of spacers 131 is greater than or equal to 2 μm, such as 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, etc., and the minimum distance D1 between the plurality of isolation grooves 122 and the plurality of spacers 131 is less than 2 μm, such as 1.9 μm, 1.8 μm, 1.7 μm, 1.6 μm, 1.5 μm, etc., such as greater than or equal to 1 μm.

[0100] For example, when the distance between adjacent sub-pixels SP is relatively small, such as when the distance between the sub-pixel openings 121 of adjacent sub-pixels SP is less than 25μm, the above distance setting can ensure the structure and function of the spacer 131, the isolation opening 123 and the isolation groove 122. When the distance between adjacent sub-pixels SP is relatively large, such as when the distance between the sub-pixel openings 121 of adjacent sub-pixels SP is greater than or equal to 25μm, the setting of the spacer 131, the isolation opening 123 and the isolation groove 122 is not limited to the above distance setting.

[0101] For example, refer to Figure 12The plurality of isolation openings 123 include a first isolation opening 1231 and a second isolation opening 1232 that partially surround the sub-pixel opening 121 of the second color sub-pixel SP2. The first isolation opening 1231 and the second isolation opening 1232 are spaced apart to ensure the continuity of the second electrode E2 and prevent the signal from failing to transmit normally due to the breakage of the second electrode E2. For example, the plurality of isolation openings 123 also include a fourth isolation opening 1234 and a fifth isolation opening 1235 that partially surround the sub-pixel opening 121 of the second color sub-pixel SP2. The first isolation opening 1231, the second isolation opening 1232, the fourth isolation opening 1234, and the fifth isolation opening 1235 are all arranged around the sub-pixel opening 121 of the second color sub-pixel SP. For example, each pair of adjacent isolation openings 123 in the first isolation opening 1231, the second isolation opening 1232, the fourth isolation opening 1234, and the fifth isolation opening 1235 are spaced apart.

[0102] For example, the first isolation opening 1231, the second isolation opening 1232, the fourth isolation opening 1234 and the fifth isolation opening 1235 are respectively adjacent to the four sides of the square of the sub-pixel opening 121 of the second color sub-pixel SP2, and are respectively disposed between the sub-pixel opening 121 of the adjacent second color sub-pixel SP2 and the sub-pixel opening 121 of the third color sub-pixel SP3. This can effectively block the light-emitting material layer E3 of the adjacent second color sub-pixel SP2 and the third color sub-pixel SP3, so as to reduce or even avoid crosstalk between the adjacent second color sub-pixel SP2 and the third color sub-pixel SP3.

[0103] For example, such as Figure 12 As shown, the sub-pixel opening 121 of the third color sub-pixel SP adjacent to the second color sub-pixel SP includes a long side SP31 and a short side SP32. The plurality of isolation openings 123 also include a third isolation opening 1233 adjacent to the long side SP31, for example, a third isolation opening 1233 adjacent to each long side SP31. Thus, the long side SP31 of the sub-pixel opening 121 of the third color sub-pixel SP is adjacent to the third isolation opening 1233, and the short side SP32 is adjacent to the third isolation slot 1223.

[0104] For example, the first spacing G1 of the first isolation slot 122 and the second isolation slot 122 is set to face the third isolation opening 1233. For example, the spacing between each pair of adjacent isolation slots in the first isolation slot 1221, the second isolation slot 1222, the fourth isolation slot 1224, and the fifth isolation slot 1225 all face a third isolation slot 1223. This prevents adjacent third color sub-pixels SP3 and first color sub-pixels SP1 from directly generating crosstalk through the spacing / opening between adjacent two isolation slots 122.

[0105] For example, in some embodiments, for the isolation openings 123 (e.g., the first isolation opening 1231, the second isolation opening 1232, the fourth isolation opening 1234, and the fifth isolation opening 1235 described above) provided between adjacent second color sub-pixels SP and third color sub-pixels SP, the isolation openings 123 (e.g., the first isolation opening 1231, the second isolation opening 1232, the fourth isolation opening 1234, and the fifth isolation opening 1235 described above) are closer to the sub-pixel opening 121 of the second color sub-pixel SP than the sub-pixel opening 121 of the third color sub-pixel SP.

[0106] For example, in some embodiments, for the isolation opening 123 (e.g., the third isolation opening 1233 described above) provided between adjacent first color sub-pixels SP and third color sub-pixels SP, the isolation opening 123 (e.g., the third isolation opening 1233 described above) is closer to the sub-pixel opening 121 of the third color sub-pixel SP than the sub-pixel opening 121 of the first color sub-pixel SP.

[0107] Since different color sub-pixels exhibit different degrees of crosstalk, for example, the crosstalk between the third color sub-pixel (e.g., green sub-pixel) and the second color sub-pixel (e.g., red sub-pixel) is more severe than that between the first color sub-pixel (e.g., blue sub-pixel). By setting the isolation slot 122 close to the third color sub-pixel (e.g., green sub-pixel) and the second color sub-pixel (e.g., red sub-pixel), the optimization effect of the isolation opening 123 on crosstalk will be more obvious, achieving a reasonable and effective optimization of the anti-crosstalk settings between sub-pixels.

[0108] For example, in other embodiments, the plurality of isolation slots 122 may be arranged in other ways. Figure 14 A partial planar schematic diagram of another display substrate provided in at least one embodiment of the present disclosure is shown, such as... Figure 14 As shown, the multiple isolation slots 122 can be designed with a bend. In this case, the multiple isolation slots 122 are arranged to fully surround the sub-pixel openings 121 of the multiple sub-pixels SP, and there is a break S between adjacent isolation slots 122, such as... Figure 14 As shown by the dotted coil and other positions, this ensures the continuity of the second electrode E2 and prevents the signal from failing to transmit normally due to the breakage of the second electrode E2.

[0109] For example, such as Figure 14 As shown, the multiple spacers 131 and the multiple isolation grooves 122 do not overlap, thereby avoiding the influence of the multiple isolation grooves 122 on the height of the multiple spacers 131 and ensuring the support effect of the multiple spacers 131.

[0110] For example, in Figure 14In one embodiment, a spacer 131 is provided for every three pixel units. In other embodiments, the arrangement density of the spacers 131 can be increased to improve the support effect of the spacers 131.

[0111] For example, Figure 15 A partial planar schematic diagram of another display substrate provided in at least one embodiment of the present disclosure is shown, such as... Figure 15 As shown, a spacer 131 is provided for every two pixel units. At this time, the multiple spacers 131 do not overlap with the multiple isolation grooves 12, and the multiple spacers 131 do not overlap with the multiple vias 151, so as to ensure the support effect of the multiple spacers 131.

[0112] For example, in some embodiments, such as Figure 2 As shown, the display substrate may further include at least one buffer layer 111 and at least one barrier layer 112. The buffer layer 111 and the barrier layer 112 may be made of inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc., to prevent impurities entering from the substrate 110 from entering the interior of the display substrate.

[0113] For example, the display substrate may also include an encapsulation layer (not shown) disposed on the light-emitting device EM. The encapsulation layer may be a composite encapsulation layer, including a stack of organic encapsulation layers and inorganic encapsulation layers. The inorganic encapsulation layer may be made of inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride, and the organic encapsulation layer may be made of organic materials such as polyimide or resin.

[0114] For example, in embodiments of this disclosure, the substrate 110 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide or resin. The material of the first electrode E1 can include transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc gallium oxide (GZO), or a stack of transparent metal oxides and metals. The material of the second electrode E2 can be a metallic material such as lithium (Li), aluminum (Al), magnesium (Mg), or silver (Ag). The planarization layer 150 and the pixel defining layer 120 can be organic materials such as polyimide or resin. The inorganic insulating layer 160 can be an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0115] The embodiments disclosed herein do not specifically limit the materials of various structures of the display substrate, nor do they limit other structures of the display substrate. For details, please refer to the related technologies.

[0116] At least one embodiment of this disclosure also provides a display device, which includes the display substrate provided in the embodiments of this disclosure. For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. The embodiments of this disclosure do not limit the specific form of the display device.

[0117] For example, the display device provided in this embodiment has the same technical effect as the display substrate described above, but has a better display effect.

[0118] The following points also need to be explained:

[0119] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0120] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0121] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0122] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, The display substrate comprises: a plurality of pixel units, wherein each of the plurality of pixel units includes a plurality of sub-pixels; Substrate; A pixel defining layer, located on one side of the substrate, includes a plurality of sub-pixel openings for the plurality of sub-pixels and a plurality of isolation trenches located between the plurality of sub-pixel openings; and A spacer layer, located on the side of the pixel defining layer away from the substrate, includes a plurality of spacers; In the direction perpendicular to the substrate, the plurality of spacers and the plurality of isolation trenches do not overlap.

2. The display substrate according to claim 1, characterized in that, At least one spacer is provided for every two pixel units.

3. The display substrate according to claim 1, characterized in that, Also includes: A pixel circuit layer, disposed on the substrate, includes multiple pixel circuits. A planarization layer is disposed on the side of the pixel circuit layer away from the substrate, and includes a plurality of vias that expose the plurality of pixel circuits respectively. A plurality of first electrodes are disposed on the side of the planarization layer away from the substrate. A pixel defining layer is disposed on the side of the plurality of first electrodes away from the substrate. A plurality of sub-pixel openings expose the plurality of first electrodes, and the plurality of first electrodes are electrically connected to the plurality of pixel circuits through the plurality of vias. The plurality of spacers includes a first spacer that does not overlap with the plurality of vias in a direction perpendicular to the substrate.

4. The display substrate according to claim 3, characterized in that, Each of the plurality of pixel units includes a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels. The first spacer is disposed at least between a first color sub-pixel and a second color sub-pixel adjacent along the first direction, and between two third color sub-pixels adjacent along the second direction. The first direction is perpendicular to the second direction.

5. The display substrate according to claim 3, characterized in that, The plurality of spacers further includes a second spacer, which at least partially overlaps with the plurality of vias in a direction perpendicular to the substrate. The planar dimensions of the second spacer are larger than those of the first spacer.

6. The display substrate according to claim 5, characterized in that, The aspect ratio of the planar shape of the second spacer is greater than that of the planar shape of the first spacer.

7. The display substrate according to claim 5, characterized in that, Each of the plurality of pixel units includes a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels. The second spacer is disposed at least between two adjacent third color sub-pixels along the first direction and between one adjacent first color sub-pixel and one second color sub-pixel along the second direction. The first direction is perpendicular to the second direction.

8. The display substrate according to claim 7, characterized in that, The longitudinal direction of the planar shape of the second spacer is along the first direction.

9. The display substrate according to claim 3, characterized in that, The plurality of spacers further includes a second spacer, which at least partially overlaps with the plurality of vias in a direction perpendicular to the substrate. The plurality of spacers also includes a third spacer disposed adjacent to the second spacer.

10. The display substrate according to claim 9, characterized in that, Each of the plurality of pixel units includes a first color sub-pixel, a second color sub-pixel, and two third color sub-pixels. The second spacer and the third spacer are disposed at least between two adjacent third color sub-pixels along the first direction and between one adjacent first color sub-pixel and one second color sub-pixel along the second direction, wherein the first direction is perpendicular to the second direction. The second spacer and the third spacer are arranged along the first direction.

11. The display substrate according to claim 10, characterized in that, The second spacer and the third spacer have the same planar shape and planar dimensions.

12. The display substrate according to any one of claims 1-11, characterized in that, The plurality of sub-pixels includes a first color sub-pixel, and the plurality of isolation slots includes a first isolation slot and a second isolation slot that partially surround the sub-pixel opening of the first color sub-pixel, the first isolation slot and the second isolation slot being spaced apart.

13. The display substrate according to claim 12, characterized in that, The plurality of sub-pixels includes a third color sub-pixel adjacent to the first color sub-pixel, the first isolation slot and the second isolation slot have a first interval, the first interval being configured as a sub-pixel opening facing the third color sub-pixel.

14. The display substrate according to claim 13, characterized in that, The sub-pixel opening of the third color sub-pixel includes a long side and a short side. The plurality of isolation slots also includes a third isolation slot adjacent to the short side.

15. The display substrate according to any one of claims 1-14, characterized in that, The pixel defining layer further includes a plurality of isolation openings located between the plurality of sub-pixel openings, wherein the plurality of spacers and the plurality of isolation openings do not overlap in a direction perpendicular to the substrate. The sidewalls of the plurality of isolation grooves have a first slope angle, and the sidewalls of the plurality of isolation openings have a second slope angle, wherein the first slope angle is greater than the second slope angle.

16. The display substrate according to claim 15, characterized in that, The minimum distance between the plurality of isolation openings and the plurality of spacers is greater than the minimum distance between the plurality of isolation grooves and the plurality of spacers.

17. The display substrate according to claim 15, characterized in that, Also includes: A pixel circuit layer, disposed on the substrate, includes multiple pixel circuits. A planarization layer is disposed on the side of the pixel circuit layer away from the substrate, and includes a plurality of vias exposing the plurality of pixel circuits and undercut grooves disposed between the plurality of vias. An inorganic insulating layer is disposed on the side of the planarization layer away from the substrate, and includes an inorganic groove that communicates with the undercut groove to form an undercut groove structure. At least a portion of the plurality of isolation grooves or at least a portion of the plurality of isolation openings exposes the undercut groove structure.

18. The display substrate according to claim 15, characterized in that, The plurality of sub-pixels includes a second color sub-pixel, and the plurality of isolation openings includes a first isolation opening and a second isolation opening that partially surround the sub-pixel opening of the second color sub-pixel, the first isolation opening and the second isolation opening being spaced apart.

19. The display substrate according to claim 18, characterized in that, The plurality of sub-pixels also includes a third color sub-pixel adjacent to the second color sub-pixel, the sub-pixel opening of the third color sub-pixel including a long side and a short side. The plurality of isolation openings also includes a third isolation opening adjacent to the long side.

20. The display substrate according to claim 19, characterized in that, The plurality of sub-pixels also includes a first color sub-pixel adjacent to the third color sub-pixel, and the plurality of isolation slots include a first isolation slot and a second isolation slot that partially surround the sub-pixel opening of the first color sub-pixel, the first isolation slot and the second isolation slot having a first interval. The first interval is configured to face the third isolation opening.

21. The display substrate according to claim 19, characterized in that, For an isolation opening provided between adjacent second-color sub-pixels and third-color sub-pixels, the isolation opening is closer to the sub-pixel opening of the second-color sub-pixel than the sub-pixel opening of the third-color sub-pixel.

22. The display substrate according to claim 20, characterized in that, For an isolation opening provided between adjacent first color sub-pixels and third color sub-pixels, the isolation opening is closer to the sub-pixel opening of the third color sub-pixel than the sub-pixel opening of the first color sub-pixel.

23. The display substrate according to claim 20, characterized in that, The first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a green sub-pixel.

24. A display device, characterized in that, Includes the display substrate described in any one of claims 1-23.

Images