Integrated circuit package
By introducing a galvanic effect testing structure into the interposer layer, the corrosion problem caused by the galvanic effect in integrated circuit packaging is solved, enabling defect detection before assembly, avoiding waste of packaging and chips, and improving production yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2025-06-18
- Publication Date
- 2026-07-21
AI Technical Summary
In integrated circuit packaging, corrosion problems caused by the Galvani effect may not be discovered until after assembly, leading to the scrapping of chips and packages, increasing costs and waste.
A galvanic effect test structure is introduced into the interposer layer, including a detection contact pad and a test contact pad. The galvanic effect is detected by the test circuit before assembly to ensure that the interposer layer is free of defects before assembly.
This avoids packaging and chip scrap caused by the galvanic effect, improves yield, reduces waste, and achieves more efficient integrated circuit packaging production.
Smart Images
Figure CN224538714U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to an integrated circuit package. Background Technology
[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have resulted in several generations of integrated circuits, each with smaller and more complex circuits than the previous generation. Throughout the evolution of integrated circuits, functional density (the number of interconnects per unit chip area) has typically increased, while geometry (the smallest component (or line) that can be manufactured using the technology) has decreased. This miniaturization process usually provides benefits by increasing production efficiency and reducing associated costs. This miniaturization has also increased the complexity of integrated circuit processes and manufacturing.
[0003] With the miniaturization of integrated circuit features, various efforts have been made to address the problems associated with integrated circuit packaging. In some cases, an integrated circuit package includes a substrate, one or more integrated circuit chips, and an interposer layer between the substrate and the integrated circuit chips. However, this type of packaging presents many challenges and can lead to scrapped wafers or other drawbacks. Utility Model Content
[0004] This invention provides an integrated circuit package, including a first integrated circuit chip and an interposer layer coupled to the first integrated circuit chip. The interposer layer includes a galvanic effect test structure, which includes test contact pads and detection contact pads, as well as a plurality of main contact pads electrically coupled to the first integrated circuit chip. The integrated circuit package includes a substrate coupled to the interposer layer. Attached Figure Description
[0005] The various aspects of this utility model can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.
[0006] Figure 1A This is a simplified schematic diagram of an integrated circuit packaging assembly before assembly, according to some embodiments.
[0007] Figure 1B According to some embodiments Figure 1A A simplified schematic diagram of integrated circuit packaging components after assembly.
[0008] Figure 2A This is a cross-sectional view of the interposer layer of an integrated circuit package containing a galvanic effect test structure according to some embodiments.
[0009] Figure 2BAccording to some embodiments Figure 2A A top view of the intermediary layer.
[0010] Figure 3A This is a cross-sectional view of the interposer layer of an integrated circuit package containing a galvanic effect test structure according to some embodiments.
[0011] Figure 3B According to some embodiments Figure 3A A top view of the intermediary layer.
[0012] Figures 4A to 4I These are cross-sectional views of the interposer layer in an integrated circuit package at various process stages, according to some embodiments.
[0013] Figure 5 This is an enlarged cross-sectional view of an intermediate layer portion containing galvanic corrosion according to some embodiments.
[0014] Figure 6 This is a cross-sectional view of an integrated circuit package assembled according to some embodiments.
[0015] Figure 7 This is a block diagram of an intermediary layer testing and assembly system according to some embodiments.
[0016] Figure 8 This is a flowchart of a method according to some embodiments.
[0017] Figure 9 This is a flowchart of a method according to some embodiments.
[0018] Figure 10 This is a table comparing the preciousness of metals according to some embodiments.
[0019] Explanation of reference numerals in the attached figures
[0020] 100: Integrated circuit packaging, packaging
[0021] 102: Intermediary Layer
[0022] 104a: First integrated circuit chip
[0023] 104b: Second integrated circuit chip
[0024] 106: Substrate
[0025] 108: Gavanny effect test structure
[0026] 110: Encapsulation
[0027] 112: Semiconductor substrate
[0028] 114: Dielectric Stack
[0029] 115: First interlayer dielectric layer
[0030] 116: Passivation layer
[0031] 117: Second interlayer dielectric layer
[0032] 118: Through-silicon vias, semiconductor vias
[0033] 119: Third interlayer dielectric layer
[0034] 120, 126: Metal wire
[0035] 121: Fourth interlayer dielectric layer
[0036] 122: Metal wire
[0037] 123: Grounding plane
[0038] 124, 127: Conductive vias
[0039] 125: Fifth interlayer dielectric layer
[0040] 130a, 130b, 130c, 130d, 130e: Contact pads
[0041] 132: Metal Column
[0042] 134, 134a, 134c: Solder microbumps
[0043] 140: Grounding ring
[0044] 142: Main Test Structure
[0045] 147: Test Circuit
[0046] 149: First conductor, second conductor
[0047] 150: Copper dendrites
[0048] 154: Distilled water
[0049] 156: Corrosion
[0050] 160: Intermediate layer semiconductor chip
[0051] 164: Reflux Structure
[0052] 166: Solder bump
[0053] 168: Internal electrical interconnection structure
[0054] 170: Control System
[0055] 172, 177: Assembly System
[0056] 700: System
[0057] 800, 900: Methods
[0058] 802, 804, 806, 902, 904, 906: Steps
[0059] 1000: Table
[0060] 1002, 1004, 1006: District
[0061] 2A-2A, 3A-3A: Section lines Detailed Implementation
[0062] The following description provides numerous different embodiments or instances for implementing various features of this invention. Specific examples of components and configurations are described below to simplify the content of this invention. Of course, these examples are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be reused in various instances of this invention. This reuse is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0063] Furthermore, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to facilitate the description of the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.
[0064] Terms indicating relative degree, such as “about” or “substantially”, should be interpreted as understood by a person skilled in the art in light of current technical specifications.
[0065] This invention provides an integrated circuit package interposer with a galvanic effect test structure. The integrated circuit package includes one or more integrated circuit chips positioned on top of the interposer. The interposer is positioned on a substrate. The interposer includes electrical connectors that electrically couple the one or more integrated circuit chips to electrical connectors on the substrate. Before mounting the one or more integrated circuit chips onto the interposer, the interposer is tested for the galvanic effect using its galvanic effect test structure. The galvanic effect test determines whether there are defects in the interposer that could cause the galvanic effect. If the test of the galvanic effect test structure does not show the presence of the galvanic effect, the interposer can be used in the integrated circuit package. One or more integrated circuit chips can be mounted onto the interposer, and the interposer can be mounted onto the substrate.
[0066] Embodiments of this invention offer various benefits to integrated circuit packaging and integrated circuit packaging technology. A dedicated galvanic effect test structure can detect the galvanic effect on the interposer before one or more chips are coupled to it. This avoids situations where the galvanic effect is not detected until one or more chips are mounted to the interposer, resulting in scrapped integrated circuit packages and wasted chips. Conversely, if the galvanic effect test structure reveals a defect in the interposer, only the relatively inexpensive interposer is scrapped, without the loss of the associated integrated circuit chip. This leads to better-performing integrated circuit packages, fewer scrapped wafers, and higher overall yield.
[0067] Figure 1A This is a simplified schematic diagram of an integrated circuit package 100 before assembly, according to some embodiments. The components of the integrated circuit package include an interposer 102, a first integrated circuit chip 104a, a second integrated circuit chip 104b, and a substrate 106. The interposer 102 includes a galvanic effect testing structure 108. As will be described in more detail below, the galvanic effect testing structure 108 helps ensure that the components of the integrated circuit package 100 function correctly after assembly.
[0068] In this document, unless otherwise specified, the suffixes "a" and "b" associated with integrated circuit chips 104a and 104b may be omitted. Therefore, in the following description, integrated circuit chips 104a and 104b may be generally referred to as reference numeral 104 without the suffix.
[0069] Although Figure 1ANot shown, each component of the integrated circuit package 100 may include multiple interconnect structures that enable electrical signals to be transmitted between the components of the integrated circuit package 100. For example, each component of the integrated circuit package 100 may include one or more types of surface layer interconnect structures, such as contact pads, solder bumps, solder balls, redistribution layers, or other types of interconnect structures, that enable signals to be transmitted between the components of the integrated circuit package 100.
[0070] During assembly, integrated circuit chip 104 is mounted onto interposer 102. Interposer 102 is mounted onto substrate 106. Each of the bottom layers of integrated circuit chip 104 includes one or more surface layer electrical interconnect structures for electrical connection with corresponding surface layer electrical interconnect structures on the top layer of interposer 102. The bottom layer of interposer 102 includes surface layer electrical interconnect structures for electrical connection with corresponding surface layer electrical interconnect structures on the top layer of substrate 106. The bottom layer of substrate 106 also includes surface layer interconnect structures.
[0071] After assembly, the integrated circuit package 100 can be mounted on the circuit board of an electronic device. The surface layer interconnect structure on the bottom of the substrate 106 can be coupled to corresponding structures on the circuit board. Signals can be transmitted from the circuit board through the substrate 106, then through the interposer 102, to the integrated circuit chip 104. Similarly, signals can also be transmitted from the integrated circuit chip 104 through the interposer 102, then through the substrate 106, to the circuit board. Signals can also be transmitted between chips 104 through the interposer 102.
[0072] In some embodiments, each integrated circuit chip 104 corresponds to an integrated circuit die containing semiconductor material. Each integrated circuit chip 104 may include a plurality of transistors conforming to a semiconductor substrate. Each integrated circuit chip 104 may include conductive vias, metal lines, and other internal interconnect structures to form the circuit structure of the integrated circuit chip 104.
[0073] In some embodiments, integrated circuit chips 104a and 104b are each diced from a system-on-chip (SoC) integrated circuit die. In some embodiments, integrated circuit chips 104a and 104b may be referred to as chiplets. In some embodiments, integrated circuit chips 104a and 104b are diced from different wafers. In some embodiments, integrated circuit chips 104a and 104b are each independent SoCs. Although Figure 1A Two integrated circuit chips 104a and 104b are shown, but in reality there may be only one integrated circuit chip or more than two integrated circuit chips 104.
[0074] The galvanic effect, caused by galvanic corrosion, may exist on the interlayer 102. Galvanic corrosion is an electrochemical process that preferentially occurs when one metal is in electrical contact with another metal. In some cases, this galvanic corrosion may occur on the upper surface of the interlayer 102.
[0075] In some embodiments, the interposer 102 may include aluminum contact pads. Copper material may be placed on the aluminum contact pads. Solder microbumps may then be formed on top of the copper. In this case, copper dendrites may form at the microbumps, and the copper dendrites may contact the aluminum contact pads. This may result in a chain leakage current in the assembled package. More specifically, in some embodiments, the interposer 102 may include aluminum contact pads for a primary test structure for performing primary testing on the interposer. The primary test structure may correspond to a good die test structure for performing pretty good die (PGD) testing on the interposer. The aforementioned copper dendrites may overflow onto the aluminum test pads, resulting in a chain leakage current. In some embodiments, the primary test structure is a wafer acceptance test (WAT) structure. In some embodiments, the wafer acceptance test uses standard manufacturing facility test tools with fixed probe tips / test channels. In some embodiments, the wafer acceptance test is more flexible in the number of channels, using custom probe cards to apply voltage and read voltage or current.
[0076] In some possible solutions, a cascade of leakage currents may only be detected after the integrated circuit package is assembled. In other words, in some possible solutions, a cascade of leakage currents may only be detected after the integrated circuit chip 104 has been mounted on the interposer 102. If a cascade of leakage currents caused by the galvanic effect is only detected after package assembly, the entire package may need to be scrapped. While the manufacturing cost of the interposer itself may be relatively low, the manufacturing cost of the integrated circuit chip 104 may be quite high. Therefore, detecting the galvanic effect after package assembly may result in the scrapping of the integrated circuit chip 104 along with the package 100.
[0077] This invention provides a solution for detecting the Gavanee effect in an interposer layer 102 before assembly. More specifically, the interposer layer 102 includes a Gavanee effect test structure 108. The Gavanee effect test structure 108 includes a detection contact pad and a test contact pad. During the process stage using the Gavanee effect test structure, the detection area surface may not have other structures, while metal pillars or other metal structures and solder microbumps are located above the test contact pads.
[0078] In some embodiments, the detection contact pads are coupled to a ground plane embedded within the interposer. The detection contact pads can be coupled to the ground plane via one or more conductive vias and metal interconnects. The test contact pads can be coupled to one or more other circuit structures embedded within the interposer, which will be connected to one or more other components of the package after assembly. Therefore, the galvanic effect test structure may include a buried ground plane and various conductive vias and metal interconnects.
[0079] In some embodiments, test circuitry is coupled to an interposer to perform a galvanic effect test to detect galvanic corrosion or the galvanic effect in the interposer. The test circuitry may include one or more probes or wires. A first probe may contact solder microbumps located on test contact pads of the galvanic effect test structure. A second probe may directly contact detection contact pads of the galvanic effect test structure. The test circuitry may apply one or more test signals to the test contact pads and measure one or more response signals at the detection contact pads. The one or more response signals may include voltage, current, charge, or other electrical characteristics that indicate the presence or absence of the galvanic effect.
[0080] In some embodiments, the interposer layer includes a primary test structure. The primary test structure may include primary test contact pads and primary detection contact pads. The detection contact pads may be coupled to a buried ground plane. In the presence of primary test contact pads, the galvanic effect test may be performed simultaneously or continuously by the test circuitry along with the primary test. Therefore, in some embodiments, the galvanic effect test can be conveniently performed together with other tests to be performed by the same test equipment.
[0081] In some embodiments, if the galvanic effect test indicates the presence of galvanic corrosion or galvanic effect, the interposer 102 may be scrapped before package 100 assembly. If the galvanic effect test indicates the absence of galvanic corrosion or galvanic effect, assembly of package 100 may continue, including mounting chip 104 on interposer 102.
[0082] In some embodiments, the interposer 102 is a semiconductor interposer. The semiconductor interposer may include a semiconductor substrate. As previously described, various dielectric layers, metal lines, conductive vias, contact pads, and solder bumps may be formed on the semiconductor substrate. Conductive structures, such as through-silicon vias (TSVs), may be formed on the semiconductor substrate to provide electrical connections between various conductive structures on the semiconductor substrate and the substrate 106 that will be coupled to the bottom of the interposer 102. While the term TSV can refer to "through-silicon via," in practice, TSV can also refer to "through-semiconductor via" when the interposer includes a semiconductor chip or semiconductor substrate other than silicon.
[0083] In some embodiments, the interposer 102 is an integrated circuit chip including top and bottom interconnect structures and through-silicon vias. The interposer 102 may include transistors and other circuitry formed together with a semiconductor substrate. In some embodiments, the interposer includes an integrated circuit chip or semiconductor die embedded in a dielectric structure. The dielectric structure may include a molding compound or other types of structures. Conductive vias may be formed in the dielectric structure in the side regions of the integrated circuit chip within the interposer 102. The top and bottom of the dielectric structure may include redistribution lines made of a redistribution metal layer.
[0084] Substrate 106 may include a packaging substrate, such as a PCB substrate, an organic substrate, or other types of substrate. The surface layer interconnect structure on top of substrate 106 may be coupled to the bottom of interposer 102 via controlled-collapse chip connection bumps (C4 bumps) or other types of conductive structures. Substrate 106 may include package traces or other internal interconnect structures providing electrical connections between the top and bottom surface layer interconnect structures of substrate 106. Package balls may be coupled to the bottom of substrate 106 to provide electrical connections to a circuit board on which package 100 can be mounted. Various other conductive structures may be utilized without departing from the scope of this invention.
[0085] Figure 1BThis is a simplified schematic diagram of the assembled integrated circuit package 100. Specifically, integrated circuit chips 104a and 104b are coupled to the top of the interposer 102. The interposer 102 is coupled to the top of the substrate 106. An encapsulation 110 is formed on the substrate surrounding the interposer 102 and the integrated circuit chips 104a and 104b. The encapsulation 110 may include a molding compound, a dielectric shell, or other structures to protect the integrated circuit chips 104a and 104b and the interposer 102. As previously described, the assembly of the package 100 is performed after the interposer 102 is tested for the galvanic effect using the galvanic effect test structure 108.
[0086] The integrated circuit package 100 may correspond to an interposer-based package, a local silicon interconnect (LSI)-based package, an integrated fan-out (InFO)-based package, a chip-on-the-wafer-on-substrate (CoWoS)-based package, a system-on-integrated-chip (SoIC)-based package, a wafer-on-wafer (WoW)-based package, or other types of packages.
[0087] Figure 2A This is a cross-sectional view of the interlayer 102 of the galvanic effect test structure 108 according to some embodiments. Figure 2A The intermediary layer 102 is Figure 1A and Figure 1B An example of interposer 102. Interposer 102 may correspond to a semiconductor integrated circuit chip or a semiconductor die. Alternatively, although not shown, Figure 2A The intermediate layer 102 shown may correspond to the embedded layer. Figure 2A Semiconductor die in an additional interposer structure not shown in the figure.
[0088] Interposer 102 includes a semiconductor substrate 112. Interposer 102 includes a dielectric stack 114 on the semiconductor substrate 112. Interposer 102 includes a passivation layer 116 on top of the dielectric stack 114.
[0089] The semiconductor substrate 112 may include silicon, silicon germanium, or other suitable semiconductor materials. Although Figure 2A Not shown, but in some embodiments, transistors may be formed together with the semiconductor substrate 112. The substrate 112 includes a silicon through-hole 118 extending downward from the top of the semiconductor substrate 112, although... Figure 2ANot shown, but silicon vias may extend to the bottom of semiconductor substrate 112 to facilitate connection with substrate 106, or to other components depending on the configuration of package 100 where interposer 102 is to be implemented.
[0090] The silicon through-hole 118 corresponds to a conductive via. The silicon through-hole 118 may include a metallic material. In one exemplary embodiment, the silicon through-hole includes copper. Alternatively, the silicon through-hole may include tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials.
[0091] In some embodiments, the dielectric stack 114 corresponds to a plurality of interlayer dielectric layers formed over the semiconductor substrate 112. The dielectric stack 114 includes a first interlayer dielectric layer 115. The first interlayer dielectric layer 115 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials.
[0092] Multiple metal lines 120 are formed on the top surface of the semiconductor substrate 112. Each metal line 120 may be connected to a respective through-silicon via 118. Although not shown, some metal lines 120 may be connected to multiple through-silicon vias. Some metal lines 120 may not directly contact any of the through-silicon vias 118. In one exemplary embodiment, the metal lines 120 comprise copper. However, the metal lines 120 may comprise tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The metal lines 120 may correspond to a first metal interconnect layer, sometimes referred to as metal 1. The metal lines 120 are covered by an interlayer dielectric layer 115.
[0093] The dielectric stack 114 includes a second interlayer dielectric layer 117 on a first interlayer dielectric layer 115. The second interlayer dielectric layer 117 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials. Although Figure 2A Not shown, but conductive vias or plugs may be formed in the interlayer dielectric layer 117 and contact the top surface of the metal wire 120.
[0094] The dielectric stack 114 includes a third interlayer dielectric layer 119. The third interlayer dielectric layer 119 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials.
[0095] Multiple metal lines 122 are formed on the top surface of the interlayer dielectric layer 117. Each metal line 122 may be connected to the top surface of a respective conductive via formed in the first interlayer dielectric layer 117. In one exemplary embodiment, the metal line 122 comprises copper. However, the metal line 122 may comprise tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The metal line 122 may correspond to a second metal interconnect layer, sometimes referred to as metal 2. The metal lines 122 are covered by the interlayer dielectric layer 119.
[0096] The dielectric stack 114 includes a fourth interlayer dielectric layer 121 on a third interlayer dielectric layer 119. The fourth interlayer dielectric layer 121 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials. Conductive vias 124 are formed in the interlayer dielectric layer 121 and contact the top surface of some metal lines 122. The conductive vias 124 may include copper, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials.
[0097] Figure 2A A ground plane 123 is illustrated, which is formed from the same material as the metal wire 122 in the same deposition step. The ground plane 123 is part of the Gavanee effect test structure 108. The ground plane 123 corresponds to a large metal plane embedded in the interposer layer 102.
[0098] The dielectric stack 114 includes a fifth interlayer dielectric layer 125 on the fourth interlayer dielectric layer 121. The fifth interlayer dielectric layer 125 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials.
[0099] Multiple metal lines 126 are formed on the top surface of the interlayer dielectric layer 121. Each metal line 126 may be connected to the top surface of a respective conductive via 124 formed in the fourth interlayer dielectric layer 121. In one exemplary embodiment, the metal lines 126 comprise copper. However, the metal lines 126 may comprise tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The metal lines 126 may correspond to a third metal interconnect layer, sometimes referred to as metal 3. The metal lines 126 are covered by the interlayer dielectric layer 125.
[0100] A passivation layer 116 is formed on the interlayer dielectric layer 125. The passivation layer 116 may include SiN, SiON, SiOCN, SiOC, SiCN, or other suitable dielectric layers. Although Figure 2A The passivation layer 116 is depicted as a single passivation layer, but in reality, the passivation layer 116 may include multiple layers.
[0101] The passivation layer 116 includes openings that expose the metal lines 126 of the third interlayer dielectric layer 125. Contact pads 130 are formed in these openings, located on the exposed portions of the metal lines 126. The contact pads 130 may be formed of a metallic material. In some embodiments, the contact pads 130 are formed of a different material than the metal lines 126. In an example where the metal lines 126 are copper, the contact pads 130 may be aluminum. Other metals may be used to form the contact pads 130 without departing from the scope of this invention.
[0102] exist Figure 2A The interposer 102 includes multiple contact pads 130a, multiple contact pads 130b, and one contact pad 130c. Contact pads 130a correspond to primary contact pads associated with the standard functions of the interposer 102 and are configured to be electrically coupled to the integrated circuit chip 104. Metal pillars 132 are located on top of and in contact with each contact pad 130a. Metal pillars 132 comprise a metallic material different from that of the contact pads 130a. In the example where the contact pads 130a are aluminum, metal pillars 132 may comprise copper. Other materials may be used to fabricate metal pillars 132 without departing from the scope of this invention. Solder microbumps 134a are formed on the metal pillars 132. As will be described in more detail below, solder microbumps 134a and metal pillars 132 are used to provide electrical interconnection between the interposer 102 and the integrated circuit chip 104.
[0103] Contact pad 130b differs from contact pad 130a because the metal pillar 132 is not formed on contact pad 130b. Therefore, in Figure 2A In the process stages shown, contact pad 130b is exposed, while contact pad 130a is covered by metal pillars 132 and microbumps 134. The central contact pad 130c is also covered by metal pillars 132 and microbumps 134c.
[0104] In some embodiments, contact pad 130c is a test contact pad of the Gavanee effect test structure 108. In some embodiments, contact pad 130b is a detection contact pad of the Gavanee effect test structure 108. Therefore, contact pad 130b and one or more contact pads 130c, along with accompanying metal pillars 132 and microbumps 134c, are part of the Gavanee effect test structure 108. Ground plane 123 is also part of the Gavanee effect test structure 108.
[0105] like Figure 2AAs shown, the detection contact pad 130b is directly electrically coupled to the ground plane 123 via one or more metal lines 126 and conductive vias 124. The test contact pad 130c is not directly electrically coupled to the ground plane 123. Instead, the detection contact pad 130c may be part of the standard electrical interconnect network of the interposer 102, enabling electrical signals to be transmitted between one or more components of the package 100 along with the contact pad 130a through the interposer 102.
[0106] As previously mentioned, copper dendrites may form at the microbump 134. These copper dendrites may overflow or flow and contact the aluminum contact pads 130. This can lead to a chain of leakage currents in the assembled package. More specifically, in some embodiments, the interposer 102 may include aluminum contact pads for performing primary tests (e.g., good die (PGD) testing) on the interposer. The aforementioned copper dendrites may overflow onto the aluminum primary test pads, resulting in a chain of leakage currents.
[0107] Prior to assembly of package 100, a Gavanee effect test can be performed using a Gavanee effect test structure 108. In some embodiments, during the Gavanee effect test, test circuitry is coupled to interposer 102 to perform the Gavanee effect test to detect Gavanee corrosion or the Gavanee effect in the interposer. The test circuitry may include one or more probes or leads. A first probe may contact solder microbumps 134c positioned on test contact pads 130c of the Gavanee effect test structure 108. A second probe may directly contact exposed detection contact pads 130b of the Gavanee effect test structure 108. The test circuitry may apply one or more test signals to the test contact pads 130c and may measure one or more response signals at the detection contact pads 130b. The one or more response signals may include voltage, current, charge, or other electrical characteristics that indicate the presence or absence of the Gavanee effect. In some embodiments, the Gavanee effect test includes applying a voltage and sensing a current. If there is no current, there is no Gavanee effect. If there is current, this represents a leakage current flow due to the Gavanee effect.
[0108] In some embodiments, the detection contact pad 130b comprises a low-noble metal surrounding the target test contact pad 130c. The low-noble metal helps attract copper dendrites toward itself to detect bridging caused by galvanic corrosion. In some embodiments, as previously stated, the low-noble metal is aluminum. Other low-noble metals can be used as the detection contact pad 130b without departing from the scope of this invention. In some embodiments, a plurality of low-noble metal detection contact pads 130b are placed within the minimum microbump spacing of the microbump 134a. This can help improve the sensitivity of the galvanic effect test structure 108.
[0109] In some embodiments, the surface area of the ground plane 123 is significantly larger than the surface area of the test contact pad 130c. In some embodiments, the area of the ground plane 123 is more than 4000 times larger than the area of the test contact pad 130c. Such a large area difference can significantly help improve the sensitivity of the galvanic effect test. If galvanic corrosion is present, this large area difference can lead to a large charge potential difference during the galvanic effect test.
[0110] Figure 2B According to some embodiments Figure 2A Top view of intermediary layer 102. Figure 2A The cross-sectional view is along Figure 2B The tangent 2A is taken in the middle. Figure 2B The top view illustrates that the exposed detection contact pad 134b has a rectangular shape surrounding a central solder microbump 134c (and a buried test contact pad 130c). An array of solder microbumps 134a (and buried contact pads 130a) surrounds the detection contact pad 130b. In some embodiments, the distance between the detection area 134b and the microbumps 134 is between 2 micrometers and 4 micrometers. Figure 2B The description also includes a grounding ring 140 surrounding the interposer 102. The grounding ring 140 may comprise copper or other conductive materials. A grounding voltage may be applied to the grounding ring 140. In some embodiments, the grounding ring 140 is electrically coupled to an embedded grounding plane 123. Other surface component arrangements of the Gavanee effect test structure 108 may be used without departing from the scope of this invention.
[0111] Figure 3A This is a cross-sectional view of intermediary layer 102 according to some embodiments. Intermediary layer 102 is Figure 1A and Figure 1B An example of intermediary layer 102. Figure 3A Intermediate layer 102 and Figure 2A The intermediate layer 102 shares many of the same structures. The shared structures are identified by the same reference number.
[0112] In some embodiments, Figure 3A The interposer 102 includes a primary test structure 142. The primary test structure 142 may correspond to a good die (PGD) test structure. As previously described, the primary test structure 142 is used to detect the quality and functionality of the interconnect structure of the interposer 102 prior to assembly of the package 100. Advantageously, the galvanic effect test structure 108 can be used in the same test procedure to determine the presence of galvanic corrosion.
[0113] The primary test structure 142 includes a primary test contact pad 130e and a primary detection contact pad 130d. During the primary test, a first probe is connected to the primary test contact pad 130e, and a test signal is applied to the primary contact pad 130e through the first probe. During the primary test, a second probe is connected to the primary detection contact pad 130d. One or more electrical signals are detected at the primary detection pad 130d to determine the quality of the interconnect structure of the interposer layer 102.
[0114] The primary test contact pad 130e is electrically connected to one or more metal lines 120 in the first interlayer dielectric layer 115 via metal line 126, conductive via 124, metal line 122, and conductive via 127 formed in the first interlayer dielectric layer 115. The metal lines 120 to which the test contact pad 130e is coupled may correspond to a ground plane. The primary detection contact pad 130d is connected to the ground plane 123 via metal line 126 and conductive via 124.
[0115] In some embodiments, the galvanic effect test contact pad 130c is coupled to an embedded ground plane or metal wire 120 via one or more conductive vias 124 and 127, bypassing the ground plane 123. Various other arrangements and configurations of the main test structure 142 and the galvanic effect test structure 108 can be utilized without departing from the scope of this invention.
[0116] Figure 3B According to some embodiments Figure 3A Top view of intermediary layer 102. Figure 3A The cross-sectional view is along Figure 3B The tangent 3A is taken. Figure 3B The top view illustrates the location of the Gavanee effect test structure 108 and the main test structure 142. Grounding ring 140 appears... Figure 3B Other arrangements and configurations of the main test structure 142 and the Gavanee effect test structure 108 can be used without departing from the scope of this invention.
[0117] Figures 4A to 4I This is a cross-sectional view of the intermediate layer 102 at various process stages. Figures 4A to 4I Explanation of formation Figure 3A and Figure 3B The process of intermediate layer 102, but this process can also be used to form Figure 2A and Figure 2B Intermediate layer 102.
[0118] exist Figure 4A In this configuration, the interposer 102 includes a semiconductor substrate 112. The semiconductor substrate 112 may include silicon, silicon germanium, or other suitable semiconductor materials. Figure 4AIn this process, a silicon through-hole 118 has been formed in the semiconductor substrate, extending downwards from the top of the semiconductor substrate 112 into the semiconductor substrate 112. Although Figure 2A Not shown, but the through-silicon via 118 may extend to the bottom of the semiconductor substrate 112 for connection to the substrate 106 or other components, depending on the configuration of the package 100 in which the interposer 102 is implemented. In one exemplary embodiment, the through-silicon via 118 comprises copper. Alternatively, the through-silicon via may comprise tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials.
[0119] exist Figure 4B In this process, a first interlayer dielectric layer 115 has been formed on the semiconductor substrate 112 and the silicon through-hole 118. The first interlayer dielectric layer 115 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, and AlO, or other suitable dielectric materials. The first interlayer dielectric layer 115 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes.
[0120] exist Figure 4B In this embodiment, an interlayer dielectric layer 115 has been patterned to expose silicon vias 118. Multiple metal lines 120 have been formed in openings in the interlayer dielectric layer 115 on the top surface of the semiconductor substrate 112. Each metal line 120 may be connected to its respective silicon via 118. Although not shown, some metal lines 120 may be connected to multiple silicon vias. Some metal lines 120 may not directly contact any silicon via 118. In one exemplary embodiment, the metal lines 120 comprise copper. However, the metal lines 120 may comprise tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The metal lines 120 may correspond to a first metal interconnect layer, sometimes referred to as metal 1. The metal lines 120 are covered by the interlayer dielectric layer 115. The metal lines 120 may be deposited by physical vapor deposition, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.
[0121] exist Figure 4C In this process, a second interlayer dielectric layer 117 has been formed on the first interlayer dielectric layer 115. The second interlayer dielectric layer 117 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, and AlO, or other suitable dielectric materials. The interlayer dielectric layer 117 may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition processes.
[0122] exist Figure 4CIn this configuration, a conductive via 127 is formed in the interlayer dielectric layer 117 and contacts the top surface of the metal line 120. The conductive via 127 can be formed by patterning the interlayer dielectric layer 117 to form trenches exposing selected metal lines 120, and depositing conductive material in the trenches. The conductive material may include copper, aluminum, tungsten, titanium, tantalum, or other suitable conductive materials. The conductive material can be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.
[0123] exist Figure 4D In this configuration, a third interlayer dielectric layer 119 is formed on the interlayer dielectric layer 117. The third interlayer dielectric layer 119 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, and AlO, or other suitable dielectric materials. The interlayer dielectric layer 119 may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition processes.
[0124] exist Figure 4D In this configuration, multiple metal lines 122 are formed on the top surface of the interlayer dielectric layer 117. Each metal line 122 may be connected to the top surface of a respective conductive via formed in the first interlayer dielectric layer 117. In one exemplary embodiment, the metal line 122 comprises copper. However, the metal line 122 may comprise tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The metal line 122 may correspond to a second metal interconnect layer, sometimes referred to as metal 2. The metal line 122 may be formed by patterning the interlayer dielectric layer 121 to form trenches in the interlayer dielectric layer 121 and depositing conductive material in the trenches. The conductive material may be deposited by physical vapor deposition, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.
[0125] exist Figure 4E In this configuration, a fourth interlayer dielectric layer 121 is formed on the third interlayer dielectric layer 119. The fourth interlayer dielectric layer 121 may comprise one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, and AlO, or other suitable dielectric materials. The interlayer dielectric layer 121 may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition processes.
[0126] exist Figure 4EIn this configuration, a conductive via 124 is formed in the interlayer dielectric layer 121, contacting the top surface of some metal lines 122. The conductive via 124 may comprise copper, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The conductive via 124 may be formed in a manner similar to that described for conductive via 127. A ground plane 123 is formed from the same material as the metal lines 122 in the same deposition step. The ground plane 123 is part of the Gavanee effect test structure 108. The ground plane 123 corresponds to a large ground metal plane embedded in the interlayer 102.
[0127] exist Figure 4F In this configuration, the fifth interlayer dielectric layer 125 has been deposited on the fourth interlayer dielectric layer 121. The fifth interlayer dielectric layer 125 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, and AlO, or other suitable dielectric materials. The interlayer dielectric layer 125 may be deposited by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or other suitable deposition processes.
[0128] exist Figure 4F In this embodiment, multiple metal lines 126 have been formed on the top surface of the interlayer dielectric layer 121. Each metal line 126 may be connected to the top surface of a respective conductive via 124 formed in the fourth interlayer dielectric layer 121. In one exemplary embodiment, the metal line 126 comprises copper. However, the metal line 126 may comprise tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The metal line 126 may correspond to a third metal interconnect layer, sometimes referred to as metal 3. The metal line 126 may be formed in a manner similar to that described for metal line 120.
[0129] exist Figure 4G In this process, a passivation layer 116 has been formed on the interlayer dielectric layer 125. The passivation layer 116 may include SiN, SiON, SiOCN, SiOC, SiCN, or other suitable dielectric layers. Although Figure 4G Passivation layer 116 is illustrated as a single passivation layer, but in practical applications, passivation layer 116 may include multiple layers. For example, a first passivation layer may be formed and patterned to expose metal line 126. Lower contact pad 130 may then be formed on the exposed metal line 126.
[0130] Contact pads 130 may be formed of a metallic material. In some embodiments, contact pads 130 may be formed of a material different from that of the metal line 126. For example, contact pads 130 may be formed of a less precious metal. In the example where the metal line 126 is copper, contact pads 130 may be aluminum. Other metals may be used to form contact pads 130 without departing from the scope of this invention. Contact pads 130 may be formed by physical vapor deposition, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.
[0131] After the contact pads 130 are formed, a second passivation layer can be formed on the first passivation layer and the contact pads 130. The second passivation layer can then be patterned to expose the contact pads 130b of the Gavanee effect test structure 108 and the contact pads 130d and 130e of the main test structure 142, as shown. Figure 4G As shown.
[0132] exist Figure 4H In this embodiment, metal pillars 132 are formed on contact pads 130a and test contact pads 130c of the Gavanee effect test structure 108. The metal pillars 132 comprise a metallic material different from that of the contact pads 130. In the example where the contact pads 130 are aluminum, the metal pillars 132 may comprise copper. Other materials may be used to form the metal pillars 132 without departing from the scope of this invention. Figure 4H In the middle, solder microbumps 134 have been formed on the metal pillar 132.
[0133] exist Figure 4I In this process, copper dendrites have formed at the metal pillars 132 and solder microbumps 134c, and overflow onto the detection contact pads 130b. A galvanic effect test can detect bridging formed by the copper dendrites 150. In some embodiments, a primary test at the main contact pads 130d and 130e can detect the galvanic effect caused by the copper dendrites.
[0134] Figure 4I Test circuitry 147 performing a primary test at primary test structure 142 is also illustrated. Specifically, a first conductor 149 is coupled to test contact pad 130E. A second conductor 149 is coupled to detection contact pad 130d. A test signal is then applied to test contact pad 130E, and a response signal is measured at test contact pad 130d. The primary test can detect the quality of the interposer 102. In some embodiments, the primary test can also detect the presence of copper dendrites 150 forming a bridge. Alternatively, test circuitry 147 can apply separate probes to solder microbumps 1304C and Gavanee effect detection electrodes 130b.
[0135] Figure 5 This is an enlarged cross-sectional view of a portion of the intermediary layer 102 according to some embodiments. Figure 5 In this process, the interposer 102 has been rinsed with distilled water. Distilled water 154 is used to rinse the top of the interposer 102. A potential difference can be applied between the detection electrode 130b and the solder microbumps 1304C. Copper dendrites 150 have formed and flowed onto the detection contact pads 130b. This results in corrosion 156 of the detection electrode 130b. This corrosion can be detected by the galvanic effect test as previously described, so that the interposer 102 can be discarded before package assembly.
[0136] In some embodiments, the metal pillar 132 may be formed of a high-noble metal such as gold, platinum, silver, or titanium. The contact pad 130 may be formed of a low-noble metal such as tin, aluminum, cadmium, galvanized steel, zinc, or magnesium. In the Gavanie effect, the low-noble metal acts as the anode, and the high-noble metal acts as the cathode. Ions can move from the anode to the cathode.
[0137] Figure 6 This is a cross-sectional view of an integrated circuit package 100 according to some embodiments. Figure 6 The integrated circuit package 100 is Figure 1B An example of an integrated circuit package 100. The integrated circuit package 100 is assembled after testing the presence of the galvanic effect in the interposer layer 102.
[0138] Intermediate layer 102 can also be called intermediate semiconductor chip 160, and corresponds to Figures 1A to 5 The diagram shows an example of an interposer 102 that includes the Gavané effect test structure 108. Alternatively, the interposer semiconductor chip 160 may be part of a larger interposer 102. The semiconductor chip 160 can be considered as an interposer substructure.
[0139] Integrated circuit chips 104a and 104b are attached to the interposer 102. Solder microbumps 134 provide electrical connections between integrated circuit chips 104a and 104b and the interposer 102 / semiconductor chip 160. The internal interconnect structure of the interposer 102 / semiconductor chip 160 provides direct electrical communication between integrated circuit chips 104a and 104b. A galvanic effect test structure 108 is present in the interposer 102 / semiconductor chip 160, although... Figure 6 It is not obvious in the middle.
[0140] Interposer 102 is attached to substrate 106. Through-silicon vias 118 electrically connect integrated circuit chips 104a and 104b to substrate 106. Interposer 102 also includes reflow structures 164. Solder bumps 166 provide electrical contact with the top surface of substrate 106. Internal electrical interconnect structures 168 of substrate 106 connect solder bumps 166 to solder balls 170 coupled to the bottom of substrate 106.
[0141] Molding compound 174 may cover the interposer 102 and integrated circuit chips 104a and 104b. Encapsulation 110 may further accommodate integrated circuit chips 104a and 104b and the interposer 102, and may be positioned on the top surface of substrate 106. Various other configurations of integrated circuit package 100 may be utilized without departing from the scope of this invention.
[0142] In some embodiments, the top surface of the interposer / semiconductor chip 160 is covered by a passivation layer 177. The passivation layer 177 is a dielectric material. After the integrated circuit package 100 is assembled, the passivation layer 177 completely covers the top surface of the detection contact pad 130b, making the top surface of the detection contact pad 130b inaccessible for electrical coupling. The detection contact pad 130d and test contact pad 130e of the main test structure are also covered by the passivation layer 177 and are no longer accessible for electrical coupling.
[0143] Figure 7 This is a block diagram of a system 700 according to some embodiments. System 700 includes a control system 170 and a test circuit 147. The control system 170 controls the test circuit 147 to perform one or more tests on the interposer 102 prior to assembling an integrated circuit package containing the interposer 102. The interposer 102 includes a Gavanee effect test structure 108 (not shown). The control system 170 controls the test circuit 147 to perform a Gavanee effect test on the interposer 102. In response to the control system 170, the test circuit 147 applies a test signal to the test contact pads of the Gavanee effect test structure. The test circuit 147 receives a response signal through the detection contact pads of the Gavanee effect test structure 108.
[0144] In some embodiments, test circuitry 147 analyzes the response signal to determine if interposer 102 is defective. Test circuitry 147 can then provide test result data to control system 170, indicating whether interposer 102 is determined to be defective or suitable for inclusion in an integrated circuit package. If the test result data indicates that interposer 102 is suitable for inclusion in an integrated circuit package, control system 170 controls assembly system 172 to include interposer 102 in the integrated circuit package. Alternatively, control system 170 can record the state of interposer 102 as ready and suitable for assembly. If the test result indicates that interposer 102 is defective, control system 170 can mark or otherwise record the state of interposer 102 as defective and should be discarded. Control system 170 can also control assembly system 172 not to use interposer 102 in the integrated circuit package.
[0145] In some embodiments, the test circuit 147 provides a response signal to the control system 170. The control system 170 can then analyze the response signal to determine whether the interposer layer 102 has defects.
[0146] Figure 8 This is a flowchart of method 800 according to some embodiments. Method 800 can be utilized Figures 1A to 7 The process, components, and systems described herein. In step 802, method 800 includes forming a dielectric stack of the interposer on a semiconductor substrate. An example of an interposer is... Figure 2AIntermediate layer 102. An example of a semiconductor substrate is... Figure 2A The semiconductor substrate 112 in the middle. An example of a dielectric stack is... Figure 2A The dielectric stack 114 is shown in step 804. Method 800 includes forming a plurality of metal interconnect structures within the dielectric stack in step 804. An example of a metal interconnect structure is... Figure 2A Structures 120, 112, 123, 124, and 126 are included. In step 806, method 800 includes forming a plurality of contact pads on the dielectric stack, including a plurality of main contact pads, a first test contact pad of the Gavanee effect test structure, and a detection contact pad of the Gavanee effect test structure. An example of a main contact pad is... Figure 2A Contact pad 130a in the example. An example of testing contact pads is... Figure 2A The test contact pad 130c is shown in the image. An example of detecting contact pads is... Figure 2A The detection contact pad 130b in the middle.
[0147] Figure 9 This is a flowchart of method 900 according to some embodiments. Method 900 can utilize... Figures 1A to 7 The process, components, and systems described herein. In step 902, method 900 includes applying a first test signal to a first test contact pad of a galvanic effect test structure in an interposer layer, the interposer layer including a semiconductor substrate located beneath the first test contact pad and semiconductor vias in the semiconductor substrate. An example of a galvanic effect test structure is... Figure 2A The Gavanee effect test structure 108 is used in the test. An example of testing contact pads is... Figure 2A The test contact pad is 130c. An example of an interposer layer is... Figure 2A Intermediate layer 102. An example of a semiconductor substrate is... Figure 2A The semiconductor substrate 112 in the example. An example of semiconductor through-hole is... Figure 2A The semiconductor via 118 is shown. In step 904, method 900 includes receiving a first response signal from a first detection contact pad in the interposer layer based on a first test signal. An example of a detection contact pad is... Figure 2A The detection contact pad 130b is in step 906. In step 906, method 900 includes detecting galvanic corrosion of the interposer layer based on a first response signal.
[0148] Figure 10Table 1000 illustrates the relative preciousness of metals, according to some embodiments. Table 1000 illustrates zones 1002, 1004, and 1006. Zone 1002 represents metals that are generally compatible with each other and are therefore unlikely to undergo galvanic corrosion. Metals falling into zone 1004 may have some minor corrosion problems. Metals falling into zone 1006 are highly dissimilar and will undergo galvanic corrosion under certain conditions, such as in the presence of an electrolyte. As can be seen, copper and aluminum fall into zone 1006 and are highly dissimilar and prone to galvanic corrosion.
[0149] This invention provides an interposer for integrated circuit packaging with a Gavanee effect testing structure. The integrated circuit package includes one or more integrated circuit chips positioned on top of the interposer. The interposer is positioned on a substrate. The interposer includes electrical connectors that electrically couple the one or more integrated circuit chips to electrical connectors on the substrate. Before mounting the one or more integrated circuit chips onto the interposer, the interposer is tested for the Gavanee effect using its Gavanee effect testing structure. The Gavanee effect test determines whether a defect in the interposer exists that could cause the Gavanee effect. If the test of the Gavanee effect testing structure does not indicate the presence of the Gavanee effect, the interposer can be used in the integrated circuit package. One or more integrated circuit chips can be mounted onto the interposer, and the interposer can be mounted onto a substrate.
[0150] Embodiments of this invention offer various benefits to integrated circuit packaging and integrated circuit packaging technology. A dedicated Gavanie effect test structure can detect the Gavanie effect on the interposer before one or more chips are coupled to it. This avoids situations where the Gavanie effect is not detected until one or more chips are mounted to the interposer, resulting in scrapped integrated circuit packages and wasted chips. Conversely, if the Gavanie effect test structure indicates a defect in the interposer, only the relatively inexpensive interposer is scrapped, without losing the associated integrated circuit chips. This leads to better-performing integrated circuit packages, fewer scrapped wafers, and higher overall yield.
[0151] In some embodiments, the integrated circuit package includes a first integrated circuit chip and an interposer coupled to the first integrated circuit chip. The interposer includes a galvanic effect test structure including test contact pads and detection contact pads, and a plurality of main contact pads electrically coupled to the first integrated circuit chip. The integrated circuit package includes a substrate coupled to the interposer.
[0152] The features of the above embodiments are beneficial for those skilled in the art to understand this utility model. Those skilled in the art should understand that this utility model can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this utility model, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this utility model.
Claims
1. An integrated circuit package, characterized in that, include: First integrated circuit chip; An intermediary layer, coupled to the first integrated circuit chip, the intermediary layer comprising: The Gavanee effect test structure includes test contact pads and detection contact pads; and Multiple main contact pads are electrically coupled to the first integrated circuit chip; and a substrate is coupled to the interposer layer.
2. The integrated circuit package according to claim 1, characterized in that, The galvanic effect test structure includes an embedded ground plane electrically coupled to the detection contact pad.
3. The integrated circuit package according to claim 2, characterized in that, The surface area of the embedded ground plane is at least 4,000 times the surface area of the test contact pad.
4. The integrated circuit package according to claim 1, characterized in that, The galvanic effect test structure includes: Metal pillars, on the test contact pads; and Solder bumps on the metal pillar.
5. The integrated circuit package according to claim 4, characterized in that, The entire top surface of the test contact pad is covered with a dielectric material.
6. The integrated circuit package according to claim 1, characterized in that, The detection contact pad surrounds the test contact pad.
7. The integrated circuit package according to claim 6, characterized in that, The interposer layer includes a plurality of primary contact pads surrounding the detection contact pads, wherein one or more of the primary contact pads are electrically coupled to the first integrated circuit chip.
8. The integrated circuit package according to claim 7, characterized in that, Includes a second integrated circuit chip, which is attached to the interposer and electrically coupled to one or more of the main contact pads.
9. The integrated circuit package according to claim 1, characterized in that, The interposer layer includes a semiconductor substrate and semiconductor vias in the semiconductor substrate, the semiconductor vias electrically coupling the first integrated circuit chip to the substrate.
10. The integrated circuit package according to claim 1, characterized in that, The interposer layer includes a main test structure, including a second test contact pad and a second detection contact pad.