Semiconductor package

Abstract

Embodiment semiconductor packages can include a semiconductor device, a molding material laterally surrounding the semiconductor device, and an alignment mark including a first through-molding-via (TMV) and a second TMV each formed in the molding material. The first TMV can have a first particular size between 10 microns and 150 microns, and the second TMV can have a second particular size between 100 microns and 500 microns. One or more first TMVs can be located in a first region, and one or more second TMVs can be located in a second region surrounding the first region. The first region can have a diameter between 100 microns and 1000 microns, and the second region can be an annular region having an inner diameter between 120 microns and 1600 microns and an outer diameter between 270 microns and 2000 microns.

Description

Technical Field

[0001] Embodiments of this utility model relate to semiconductor packages. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon. Tens, hundreds, or thousands of integrated circuits are typically fabricated on a single semiconductor wafer, and the individual dies on the wafer can be separated by sawing between multiple integrated circuits along multiple dicing lines. For example, each die is often individually packaged in a multi-chip module or other type of package.

[0003] In addition to smaller electronic components, improvements have been made to component packaging in an effort to provide smaller packages that occupy less area than previous packages. Exemplary approaches include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), 3-dimensional integrated circuits (3DIC), wafer-level packages (WLP), packages on packages (PoP), system-on-chips (SoC), or system-on-integrated circuits (SoIC) devices. Some of these 3D devices (e.g., 3DIC, SoC, SoIC) are fabricated by placing chips on chips at the semiconductor wafer level. Due to the reduced interconnect length between stacked chips, these 3D devices offer higher integration density and other advantages such as faster speeds and higher bandwidth. However, many challenges exist associated with 3D devices. Utility Model Content

[0004] This utility model provides a semiconductor package including a semiconductor device; a molding material laterally surrounding the semiconductor device; and alignment marks including a first molded through-hole (TMV) and a second TMV, each of the first TMV and the second TMV being formed in the molding material, wherein the first TMV includes a first specific size and the second TMV includes a second specific size larger than the first specific size.

[0005] This utility model provides a semiconductor package, including a molding material, a rectangular plate geometry including a length direction, a width direction, and a thickness direction; alignment marks including a first TMV and a second TMV, each of the first TMV and the second TMV being formed in the molding material and having a corresponding axis of symmetry parallel to the thickness direction, wherein the first TMV includes a first specific size and the second TMV includes a second specific size larger than the first specific size; and a plurality of third TMVs formed in the molding material, each of the plurality of third TMVs including another axis of symmetry parallel to the thickness direction, wherein the plurality of third TMVs are arranged in a rectangular manner around the periphery of a first rectangular region in a plane spanned by the length direction and the width direction. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 It is an exploded vertical cross-sectional view of the components of the relevant semiconductor package during the package assembly and surface mount processes.

[0008] Figure 2 This is a vertical cross-sectional view showing the relevant assembled semiconductor package mounted on a support substrate.

[0009] Figure 3 This is a vertical cross-sectional view of another semiconductor package including an integrated fan-out package according to various embodiments.

[0010] Figure 4A This is a vertical cross-sectional view of an intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0011] Figure 4B This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0012] Figure 4C This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0013] Figure 4D This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0014] Figure 4E This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0015] Figure 4F This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0016] Figure 4G This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0017] Figure 5A This is a top view of a wafer-level intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0018] Figure 5B According to various embodiments Figure 5A A top perspective view of the repeating unit of the intermediate structure, which can be used to form a semiconductor package.

[0019] Figure 5C This is a top view of a wafer-level intermediate structure that can be used to form a semiconductor package according to various embodiments, showing four adjacent repeating units.

[0020] Figure 5D According to various embodiments Figure 5C A top perspective view of the repeating unit of the intermediate structure, which can be used to form a semiconductor package.

[0021] Figure 6A This is a top perspective view of repeating units that can be used to form intermediate structures of semiconductor packages according to various embodiments.

[0022] Figure 6B According to various embodiments Figure 6A A top view of a portion of the middle structure, showing details of the alignment marks.

[0023] Figure 6C According to various embodiments Figure 6A A vertical cross-sectional view of the repeating unit, which shows further details of the intermediate structure.

[0024] Figure 7A This is a top view of a wafer-level intermediate structure that can be used to form related semiconductor packages.

[0025] Figure 7B yes Figure 7A A top view of the first part of the intermediate structure, showing the molded through-hole (TMV) that can be used as an alignment mark.

[0026] Figure 7C yes Figure 7A A vertical cross-sectional view of the first part of the intermediate structure, which shows the non-uniformity of TMV.

[0027] Figure 7D yes Figure 7A A top view of the second part of the intermediate structure, which shows the molded through-hole (TMV) that can be used as an alignment mark.

[0028] Figure 7E yes Figure 7A A vertical cross-sectional view of the second part of the intermediate structure, which shows the non-uniformity of TMV.

[0029] Figure 7F This is a top view of another wafer-level intermediate structure that can be used to form a semiconductor package, according to various embodiments.

[0030] Figure 7G According to various embodiments Figure 7F A top view of the first part of the intermediate structure, which shows details of the first alignment mark containing multiple first TMVs and multiple second TMVs.

[0031] Figure 7H According to various embodiments Figure 7F A vertical cross-sectional view of the first part of the intermediate structure, which shows the improved uniformity of the first TMV.

[0032] Figure 7I According to various embodiments Figure 7F A top view of the second part of the intermediate structure, which shows details of the second alignment mark containing multiple first TMVs and multiple second TMVs.

[0033] Figure 7J According to various embodiments Figure 7F A vertical cross-sectional view of the second part of the intermediate structure, which shows the improved uniformity of the first TMV.

[0034] Figure 8A It is a top view of alignment marks including a plurality of first TMVs and a plurality of second TMVs according to various embodiments.

[0035] Figure 8B According to various embodiments Figure 8A A magnified top view of the alignment marks, showing the geometric details of the first TMV and the second TMV.

[0036] Figure 8C It is a top view of another alignment mark including multiple first TMVs and a single second TMV according to various embodiments.

[0037] Figure 8D It is a top view of another alignment mark including a single first TMV and multiple second TMVs according to various embodiments.

[0038] Figure 9A top view of various types of TMVs that can be used to form alignment marks according to various embodiments is shown.

[0039] Figure 10A This is a vertical cross-sectional view of an intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0040] Figure 10B This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0041] Figure 10C This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0042] Figure 10D This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0043] Figure 11A This is a vertical cross-sectional view of an intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0044] Figure 11B This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0045] Figure 11C This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0046] Figure 11D This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0047] Figure 11E This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0048] Figure 12A This is a vertical cross-sectional view of an intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0049] Figure 12B This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0050] Figure 12C This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0051] Figure 12D This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0052] Figure 13A This is a vertical cross-sectional view of an intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0053] Figure 13B This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0054] Figure 13C This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0055] Figure 13D This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0056] Figure 13E This is a vertical cross-sectional view of another intermediate structure that can be used to form a semiconductor package according to various embodiments.

[0057] Figure 14 This is a flowchart illustrating the process of forming a semiconductor package according to various embodiments.

[0058] [Explanation of Symbols]

[0059] 100, 300: Semiconductor packages

[0060] 102: Supporting substrate

[0061] 104: First Semiconductor Device / Three-Dimensional Semiconductor Device / SoC Chip Stacking / Semiconductor Device

[0062] 104a, 104b, 104c, 104d: Semiconductor devices

[0063] 106: Second Semiconductor Device / HBM Die Stack

[0064] 108: Intermediary

[0065] 110: Package substrate

[0066] 112: First solder ball / solder ball

[0067] 114: Lower surface

[0068] 116, 126: Upper surface

[0069] 120: First metal bump

[0070] 122: First bottom filler material portion

[0071] 124: Second metal bump

[0072] 128: Second bottom filler material section

[0073] 130, 132: Conductive bonding pads

[0074] 134: Third bottom filler material section

[0075] 302: Integrated Fan-Out (InFO) Package

[0076] 304: Molding material

[0077] 306: Redistribution layer

[0078] 306a: First redistribution layer

[0079] 306b: Second redistribution layer

[0080] 308a: First bonding pad

[0081] 308b: Second bonding pad

[0082] 310a: First spacing

[0083] 310b: Second spacing

[0084] 312: Molded Through Hole / Conductive Through Hole / TMV / Alignment Mark

[0085] 312a: First TMV / First Conductive Via

[0086] 312b: Second TMV / Second Conductive Via

[0087] 312c: Third TMV

[0088] 312d, 312e: TMV

[0089] 314: Electrical devices

[0090] 400a, 400b, 400c, 400d, 400e, 400f, 500ab, 500cd, 600, 1000a, 1000b, 1000c, 1000d, 1100a, 1100b, 1100c, 1100d, 1100e, 1200a, 1200b, 1200c, 1200d, 1300a, 1300b, 1300c, 1300d, 1300e: Intermediate Structure

[0091] 402: Supporting substrate / substrate

[0092] 403: Redistributed dielectric layer

[0093] 404: Seed layer

[0094] 406: Patterned photoresist

[0095] 407: Redistributed cabling interconnects

[0096] 408, 410: Opening

[0097] 409: Solder resist (SR) material

[0098] 412: Redistribution bonding pad

[0099] 414: Third metal bump

[0100] 502, 502a, 502b, 502c, 502d: Repeating units

[0101] 502a: First repeating unit

[0102] 502b: Second repeating unit

[0103] 504: Cutting track

[0104] 506a, 506b, 506c, 506d: Rectangular area / zone

[0105] 508: Alignment Mark

[0106] 508a: Alignment Mark / Type 1 TMV / First Alignment Mark / Corner Alignment Mark

[0107] 508b: Alignment Mark / Second Type TMV / Center TMV / Second Alignment Mark / Center Alignment Mark

[0108] 508c: Cut alignment mark / alignment mark

[0109] 510: Center

[0110] 802a: Zone 1

[0111] 802b: Second District

[0112] 802c: Zone 3

[0113] 804a: Diameter

[0114] 804b: Inner diameter

[0115] 804c: Outer diameter

[0116] 804d: Width

[0117] 1400: Method

[0118] 1402, 1404, 1406, 1408: Operations Detailed Implementation

[0119] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0120] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature shown in the figures and another (other) element or feature. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless otherwise explicitly stated, each element with the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0121] Typically, in a semiconductor package, multiple semiconductor integrated circuit (IC) dies / devices (i.e., "chips") can be mounted on a common substrate, which may also be referred to as the "package substrate." In some embodiments, electrical connections to the semiconductor package can be achieved by mounting the package substrate onto a support substrate containing electrical interconnects (e.g., a printed circuit board, PCB). The semiconductor package may also include one or more interposers to which semiconductor dies are attached and electrically coupled. The interposers may in turn be attached and electrically coupled to the package substrate, which may further be attached to the PCB. In this way, individual structures (e.g., semiconductor dies, interposers, package substrates, and PCBs) can be manufactured and then assembled.

[0122] The disclosed embodiments can provide advantages over existing semiconductor packages. For example, in one embodiment, the semiconductor package may include multiple alignment marks having a first through-molding-via (TMV) and a second TMV. The second TMV may have a larger dimension (e.g., edge, width, diameter, etc.) than the corresponding dimension of the first TMV. The first and second TMVs can be formed by an electroplating process, and the presence of the larger second TMV can regulate the electroplating current density to have a more uniform spatial distribution than might be possible if all TMVs (first and second TMVs) had the same dimension. In this respect, the resulting diameter uniformity and coplanarity of the resulting TMVs can be improved. Therefore, the smaller size of the first TMV can allow for increased positioning accuracy when used as alignment marks in pick-and-place processes that can be used to position multiple semiconductor devices within a semiconductor package.

[0123] An embodiment of the semiconductor package may include a semiconductor device, a molding material laterally surrounding the semiconductor device, and alignment marks including a first TMV and a second TMV, each formed in the molding material. The first TMV may have a first specific dimension between 10 micrometers and 150 micrometers, and the second TMV may have a second specific dimension corresponding to the first specific dimension, such that the second specific dimension is between 100 micrometers and 500 micrometers. One or more first TMVs may be located in a first region, and one or more second TMVs may be located in a second region surrounding the first region. The first region may have a diameter between 100 micrometers and 1000 micrometers, and the second region may be an annular region having an inner diameter between 120 micrometers and 1600 micrometers and an outer diameter between 270 micrometers and 2000 micrometers.

[0124] According to another embodiment, the semiconductor package may include a molding material having a rectangular slab geometry (including a length direction, a width direction, and a thickness direction), and alignment marks, each alignment mark comprising a respective axis of symmetry formed in the molding material and having a axis of symmetry parallel to the thickness direction, such that a first TMV includes a first specific dimension and a second TMV includes a second specific dimension corresponding to the first specific dimension, and the second specific dimension is larger than the first specific dimension. The semiconductor package may further include a plurality of third TMVs formed in the molding material, each third TMV including another axis of symmetry parallel to the thickness direction, such that the plurality of third TMVs are arranged in a rectangular arrangement around the periphery of a first rectangular region in a plane spanned by the length and width directions.

[0125] An embodiment of a method for forming a semiconductor package may include forming a plurality of conductive vias on a substrate, including alignment marks formed by a first conductive via and a second conductive via, such that the first conductive via has a first specific size and the second conductive via has a second specific size corresponding to and larger than the first specific size; positioning a semiconductor device on the substrate and aligning the semiconductor device relative to the alignment marks; attaching the semiconductor device to the substrate; and forming a molding material around the semiconductor device and the plurality of conductive vias, such that the plurality of conductive vias includes a corresponding plurality of TMVs.

[0126] Figure 1 This is an exploded vertical cross-sectional view of multiple components of the relevant semiconductor package 100 during package assembly and surface mount processes. Figure 2 This is a vertical cross-sectional view showing a related assembled semiconductor package 100 mounted on the surface of a support substrate 102, such as a printed circuit board (PCB). The semiconductor package 100 in this example is a chip-on-wafer-on-substrate (CoWoS) semiconductor package; however, it will be understood that similar assembly and mounting processes can be used for other types of semiconductor packages, such as integrated fan-out (InFO) semiconductor packages, flip-chip semiconductor packages, etc.

[0127] refer to Figure 1 and Figure 2 The associated semiconductor package 100 may include integrated circuit (IC) semiconductor devices, such as a plurality of first semiconductor devices 104 and a plurality of second semiconductor devices 106. In the package assembly process, the first semiconductor devices 104 and the second semiconductor devices 106 may be mounted on an intermediary 108. The intermediary 108, containing the first semiconductor devices 104 and the second semiconductor devices 106, may be mounted onto a package substrate 110 to form the semiconductor package 100. The semiconductor package 100 can then be mounted onto a support substrate 102, such as a printed circuit board (PCB), by mounting the package substrate 110 onto a support substrate 102 using an array of first solder balls 112 on the lower surface 114 of the package substrate 110.

[0128] The parameters that ensure the correct interconnection between the package substrate 110 and the support substrate 102 are compatible with the mounting surface (i.e., Figure 1The coplanarity among the multiple surfaces of the plurality of first solder balls 112 in contact with the upper surface 116 of the support substrate 102 is a concern. Low coplanarity among the plurality of first solder balls 112 may lead to solder cold joints (i.e., insufficient melting of solder material, resulting in poor adhesion, easy breakage and separation) and / or solder bridging problems (i.e., the solder material of one solder ball 112 contacts the material of an adjacent solder ball 112, resulting in an accidental connection (i.e., an electrical short circuit).

[0129] During the mounting of the package substrate 110 surface onto the support substrate 102, deformation of the package substrate 110 (e.g., stress-induced warping of the package substrate 110) can be a cause of low coplanarity among the multiple first solder balls 112. Deformation of the package substrate 110 is not uncommon, especially when semiconductor packages 100 are used in high-performance computing applications. These high-performance semiconductor packages 100 tend to be relatively large and may include multiple semiconductor devices mounted to the package substrate 110 (e.g., first semiconductor device 104, second semiconductor device 106), which can increase the likelihood of warping or other deformation of the package substrate 110. Such deformation can pose challenges to the effective soldering and mounting of these types of semiconductor package substrates 110 onto the support substrate 102.

[0130] In various embodiments, the first semiconductor device 104 may be a three-dimensional device, such as a three-dimensional integrated circuit (3DIC), a system-on-a-chip (SoC), or a system-on-integrated-chip (SoIC) device (i.e., a stack of chips bonded using hybrid bonding). The three-dimensional semiconductor device 104 can be formed by placing chips on top of each other at the semiconductor wafer level. Due to the reduced interconnect length between the stacked chips, these three-dimensional devices can provide improved integration density and other advantages, such as faster speeds and higher bandwidth. In some embodiments, the first three-dimensional semiconductor device 104 may also be referred to as a "first chip stack."

[0131] The second semiconductor device 106 may differ from the first semiconductor device 104 in its structure, design, and / or function. One or more second semiconductor devices 106 may be three-dimensional semiconductor devices, also referred to as a "second chip stack." In some embodiments, one or more second semiconductor devices 106 may include memory devices, such as high bandwidth memory (HBM) devices. Figure 1 and Figure 2In the example shown, semiconductor package 100 may include SoC die stack 104 and HBM die stack 106, but it should be understood that semiconductor package 100 may include more or fewer semiconductor devices.

[0132] Refer again Figure 2 The first semiconductor device 104 and the second semiconductor device 106 may be mounted on the interposer 108. In some cases, the interposer 108 may be an organic interposer comprising a polymer dielectric material (e.g., a polyimide material) having a plurality of metal interconnect structures extending therethrough. In other cases, the interposer 108 may be a semiconductor interposer, such as a silicon interposer, having a plurality of interconnect structures (e.g., through-silicon vias) extending therethrough. Other suitable configurations for the interposer 108 are within the scope of this disclosure. The interposer 108 may include a plurality of conductive bonding pads on an upper and lower surface of the interposer and a plurality of conductive interconnects extending through the interposer 108 between the upper and lower bonding pads. The plurality of conductive interconnects may distribute and route electrical signals between the first semiconductor device 104, the second semiconductor device 106, and the underlying package substrate 110.

[0133] Multiple first metal bumps 120, such as microbumps, can electrically connect multiple conductive bonding pads on the bottom surfaces of the first semiconductor device 104 and the second semiconductor device 106 to multiple conductive bonding pads on the upper surface of the intermediary 108. In a non-limiting embodiment, the multiple first metal bumps 120 in the form of microbumps may include multiple first metal stacks, such as multiple Cu-Ni-Cu stacks, located on the bottom surfaces of the first semiconductor device 104 and the second semiconductor device 106, and multiple second metal stacks (e.g., Cu-Ni-Cu stacks) located on the upper surface of the intermediary 108. A solder material such as tin (Sn) may be located between the respective first and second metal stacks to electrically connect the first semiconductor device 104 and the second semiconductor device 106 to the intermediary 108. Other suitable materials for the first metal bumps 120 and solder materials are also within the scope of this disclosure.

[0134] After the first semiconductor device 104 and the second semiconductor device 106 are mounted onto the intermediary 108, a first bottom filler material portion 122 can be selectively disposed in the space surrounding the plurality of first metal bumps 120 and between the bottom surfaces of the first semiconductor device 104 and the second semiconductor device 106 and the upper surface of the intermediary 108, such as... Figure 2As shown. The first underfill material portion 122 may also be disposed in the space between adjacent first semiconductor devices 104 and second semiconductor devices 106 that laterally separate the semiconductor package 100. In various embodiments, the first underfill material portion 122 may include an epoxy material, which may include a composite of resin and filler material.

[0135] Refer again Figure 2 Intermediate 108 may be mounted on package substrate 110, which may provide mechanical support for intermediate 108 and first semiconductor device 104 and second semiconductor device 106 mounted on intermediate 108. Package substrate 110 may include suitable materials, such as organic materials (e.g., polymers and / or thermoplastics), semiconductor materials (e.g., semiconductor wafers, such as silicon wafers), ceramic materials, glass materials, combinations thereof, etc. Other suitable substrate materials are within the scope of this disclosure. In various embodiments, package substrate 110 may include a plurality of conductive bonding pads (not shown) in the upper surface 126 of package substrate 110. A plurality of second metal bumps 124, such as C4 solder bumps, may electrically connect a plurality of conductive bonding pads (not shown) on the bottom surface of intermediate 108 to a plurality of conductive bonding pads on the upper surface 126 of package substrate 110. In various embodiments, second metal bumps 124 may include suitable solder materials, such as tin (Sn), but other suitable solder materials are also within the scope of this disclosure.

[0136] The second bottom filler material portion 128 can be disposed in the space between the bottom surface of the plurality of second metal bumps 124 and the intermediary 108 and the upper surface 126 of the package substrate 110, for example, Figure 2 As shown. In various embodiments, the second bottom filler material portion 128 may include an epoxy-based material, which may include a composite of resin and filler materials. In some embodiments, the cap or cover body ( Figure 1 and Figure 2 (Not shown) can be mounted to package substrate 110 and can provide an enclosure around the upper and side surfaces of the first semiconductor device 104 and the second semiconductor device 106.

[0137] As described above, the package substrate 110 can be mounted to a support substrate 102, such as a printed circuit board (PCB). Other suitable support substrates 102 are within the scope of this disclosure. The package substrate 110 may include a plurality of conductive bonding pads 130 in a lower surface 114 of the package substrate 110. A plurality of conductive interconnects (not shown) may extend through the package substrate 110 between the plurality of conductive bonding pads on the upper surface 126 and the lower surface 114 of the package substrate 110. A plurality of first solder balls 112 (or bump structures) may electrically connect the plurality of conductive bonding pads 130 on the lower surface 114 of the package substrate 110 to a plurality of conductive bonding pads 132 on the upper surface 116 of the support substrate 102.

[0138] The plurality of conductive bonding pads 130 of the package substrate 110 and the plurality of conductive bonding pads 132 of the support substrate 102 may be formed of a suitable conductive material (e.g., copper). Other suitable conductive materials are within the scope of this disclosure. The plurality of first solder balls 112 on the lower surface 114 of the package substrate 110 may be formed as an array of first solder balls 112, such as a ball grid array (BGA), which may include an array pattern corresponding to the array pattern of the plurality of conductive bonding pads 132 on the upper surface 116 of the support substrate 102. In a non-limiting example, the array of first solder balls 112 may include a grid pattern and may have a spacing (i.e., the distance between the center of each solder ball 112 and the center of each adjacent solder ball 112). In exemplary embodiments, the spacing may be between approximately 0.8 and 1.0 mm, but larger and smaller spacings may be used.

[0139] The first solder ball 112 may include any suitable solder material, such as tin, lead, silver, indium, zinc, nickel, bismuth, antimony, cobalt, copper, germanium, alloys thereof, combinations thereof, etc. Other materials suitable for the first solder ball 112 are also within the scope of this disclosure. In some embodiments, the lower surface 114 of the package substrate 110 may include a solder resist (SR) material coating (not shown), which may also be referred to as a “solder mask”. The SR material coating may provide a protective coating for the package substrate 110 and any underlying circuit patterns formed on or within the package substrate 110. The SR material coating may also inhibit solder material adhesion to the lower surface 114 of the package substrate 110 during reflow processes. In embodiments where the lower surface 114 of the package substrate 110 may include an SR material coating, the SR material coating may include a plurality of openings through which a plurality of conductive bonding pads 130 may be exposed.

[0140] In various embodiments, each conductive bonding pad 130 in different regions of the package substrate 110 may have the same size and shape. Figure 1 and Figure 2 In the illustrated embodiments, the surfaces of the plurality of conductive bonding pads 130 may be substantially coplanar with the lower surface 114 of the package substrate 110, which in some embodiments may include a solder resist (SR) coating. Alternatively, the surfaces of the plurality of conductive bonding pads 130 may be recessed relative to the lower surface 114 of the package substrate 110. In some embodiments, the surfaces of the plurality of conductive bonding pads 130 may be raised relative to the lower surface 114 of the package substrate 110.

[0141] Refer again Figure 1 and Figure 2 The first solder ball 112 may be disposed on the corresponding conductive bonding pad 130. In a non-limiting example, the conductive bonding pad 130 may have a width dimension between about 500 μm and about 550 μm (e.g., about 530 μm), and the first solder ball 112 may have an outer diameter between about 600 μm and about 650 μm (e.g., about 630 μm), although larger and smaller dimensions of the first solder ball 112 and / or the conductive bonding pad 130 are within the scope of the disclosure.

[0142] The first solder reflow process may include subjecting the package substrate 110 to an elevated temperature (e.g., at least about 250°C) to melt a plurality of first solder balls 112 and cause the plurality of first solder balls 112 to adhere to a plurality of conductive bonding pads 130. After the first reflow process, the package substrate 110 may be cooled to cause the plurality of first solder balls 112 to re-solidify. After the first solder reflow process, the plurality of first solder balls 112 may adhere to the plurality of conductive bonding pads 130. Before the first reflow process, each solder ball 112 may extend a vertical height from the lower surface 114 of the package substrate 110, which may be less than the outer diameter of the solder ball 112. For example, when the outer diameter of the solder ball 112 is between about 600 μm and about 650 μm (e.g., about 630 μm), the vertical height of the solder ball 112 after the first reflow process may be between about 500 μm and about 550 μm (e.g., about 520 μm).

[0143] In various embodiments, such as Figure 2The process of mounting the package substrate 110 onto the support substrate 102 may include aligning the package substrate 110 with the support substrate 102 such that a plurality of first solder balls 112 contacting the plurality of conductive bonding pads 130 of the package substrate 110 can be positioned above corresponding plurality of bonding pads (e.g., a plurality of conductive bonding pads 132). A second solder reflow process may then be performed. The second solder reflow process may include subjecting the package substrate 110 to an elevated temperature (e.g., at least about 250°C) to melt the plurality of first solder balls 112 and cause the plurality of first solder balls 112 to adhere to the corresponding conductive bonding pads 132 on the support substrate 102. Surface tension may cause the semi-liquid solder to maintain the alignment of the package substrate 110 with the support substrate 102 as the solder material cools and solidifies. When the plurality of first solder balls 112 solidify, the package substrate 110 may be located above the upper surface 116 of the support substrate 102 at a spacing height of about 0.4 mm to about 0.5 mm, but a larger or smaller spacing height is within the scope of this disclosure.

[0144] After the package substrate 110 is mounted onto the support substrate 102, a third bottom filler material portion 134 can be provided in the space surrounding the plurality of first solder balls 112 and between the lower surface 114 of the package substrate 110 and the upper surface 116 of the support substrate 102, such as... Figure 2 As shown. In various embodiments, the third bottom filler material portion 134 may include an epoxy-based material, which may include a composite of resin and filler material.

[0145] Figure 3 This is a vertical cross-sectional view of another semiconductor package 300 including an integrated fan-out (InFO) package 302 according to various embodiments. The InFO package 302 may include a first semiconductor device 104 embedded within a molding material 304. The InFO package 302 may also include a plurality of redistribution layers 306 formed directly on the molding material 304 and over the surface of the first semiconductor device 104. As shown, a plurality of first bonding pads 308a of the first semiconductor device 104 may be electrically connected to the redistribution layer 306. The redistribution layer 306 may have a fan-out configuration such that a plurality of second bonding pads 308b formed on the side of the redistribution layer 306 opposite to the first semiconductor device 104 may have a second spacing 310b greater than the first spacing 310a of the first bonding pads 308a. Figure 3 As shown, multiple metal bumps (i.e., the ones referenced above) Figure 1 and Figure 2 The described second metal bump 124 can be formed on a plurality of second bonding pads 308b, such that the InFO package 302 can be electrically attached to the package substrate 110 (e.g., see...). Figure 1 and Figure 2 ).

[0146] The InFO package 302 may also include a plurality of molded through-holes (TMVs) 312 formed within the molding material 304. The TMVs 312 may be formed on a first side of the InFO package 302 (i.e., Figure 3 Multiple redistribution layers 306 on the bottom side of the middle and formed on the second side (i.e., Figure 3 Electrical connections are made between multiple electrical contacts (not shown) on the top side of the InFO package 302. At this point, the second semiconductor device 106 can be stacked on the InFO package 302 and can be electrically connected to the TMV 312. Therefore, the semiconductor package 300 can be configured as an integrated fan-out package-on-package (InFO_PoP) structure. In other embodiments, the InFO package 302 may further include an additional redistribution layer (not shown) formed on the top side of the InFO package 302, which can provide additional electrical connections between the InFO package 302 and the second semiconductor device 106.

[0147] As described above, the first semiconductor device 104 and the second semiconductor device 106 can provide their respective functions. For example, the first semiconductor device 104 may be a SoC die stack and the second semiconductor device 106 may be an HBM die stack. Although the semiconductor package 300 includes two semiconductor devices (the first semiconductor device 104 and the second semiconductor device 106), it should be understood that in other embodiments, various numbers of semiconductor devices providing corresponding functions may be included in the semiconductor package. Additional circuitry functions may also be provided by one or more active or passive electrical devices 314, which may be attached to the redistribution layer 306 on the side opposite to the first semiconductor device 104 (i.e., the bottom side of the InFO package 302), such as... Figure 3 As shown. Electrical device 314 may include an integrated passive device (IPD), which may include resistors, capacitors, inductors, diodes, etc. For example, in some embodiments, passive electrical device 314 may include a deep trench capacitor (not shown). In other examples, electrical device 314 may include an active device, which includes logic circuits, memory circuit elements, etc.

[0148] InFO package 302 in Figure 3 The presence of semiconductor package 300 can be eliminated by forming (e.g., see Figure 2To meet the need for separate intermediaries 108 attached to multiple semiconductor devices (first semiconductor device 104, second semiconductor device 106) in the semiconductor package 100, and to provide superior performance compared to... Figure 1 and Figure 2 The advantages of the semiconductor package 100. Furthermore, by forming multiple redistribution layers 306 directly on the first semiconductor device 104, the need for... Figure 1 and Figure 2 The first metal bump 120. This also avoids the first bottom filler material portion 122 of the semiconductor package 100 (see, for example, see...). Figure 2 Therefore, the InFO package 302 can avoid alignment and warpage problems that may occur when a separate intermediary 108 is present in the semiconductor package 100. Furthermore, the InFO package 302 can provide additional advantages by including a TMV 312, which can provide the first side of the InFO package 302 (i.e., Figure 3 The bottom side) and the second side (i.e., Figure 3 The electrical connection between the top side of the InFO package and the top side of the InFO package allows the InFO package 302 to connect with one or more additional packages (e.g., the top side of the InFO package). Figure 3 The second semiconductor device 106) is stacked. See below for reference. Figures 4A to 4F This describes an exemplary process for forming the InFO package 302.

[0149] Figure 4A , Figure 4B and Figure 4C This is a vertical cross-sectional view of corresponding intermediate structures 400a, 400b, and 400c, which can be used to form a semiconductor package 302 according to various embodiments. Intermediate structure 400a may include a carrier substrate 402 on which a seed layer 404 is formed. The seed layer 404 may be formed, for example, by sputtering. Figure 4B The intermediate structure 400b may include patterned photoresist 406 formed on the seed layer 404. The patterned photoresist 406 may include a plurality of openings 408 formed within the patterned photoresist 406. Figure 4C In the intermediate structure 400c, multiple TMV312s can be electroplated with metal filler materials (such as copper, nickel, or a stack of copper and nickel). Figure 4B The intermediate structure 400b is formed in multiple openings 408 of the patterned photoresist 406.

[0150] The metal seed layer 404 may comprise, for example, a stack of titanium barrier layers and copper seed layers. The thickness of the titanium barrier layer may range from 40 nm to 400 nm, and the thickness of the copper seed layer may range from 100 nm to 400 nm. The metal filler material may comprise copper, nickel, or an alloy of copper and nickel. Other suitable metal filler materials are within the scope of this disclosure. After forming multiple TMV312s, the patterned photoresist 406 can be removed by ashing or dissolving in a solvent. A portion of the seed layer 404 can then be etched in the region between the electroplated metal filler material portions to produce multiple TMV312s as a separated structure formed on the carrier substrate 402, such as... Figure 4D As shown.

[0151] Figure 4D This is a vertical cross-sectional view of another intermediate structure 400d that can be used to form a semiconductor package 302 according to various embodiments. As shown, the intermediate structure 400d may include a plurality of TMV312 attached to a carrier substrate 402, which can be referenced above. Figures 4A to 4C The intermediate structure 400d may also include one or more semiconductor devices 104. The one or more semiconductor devices 104 may be attached to the carrier substrate 402 using a temporary adhesive layer (not shown) (e.g., a light-to-heat-conversion release (LTHC) coating or another heat-deactivated adhesive) during the pick-and-place process.

[0152] Figure 4E This is a vertical cross-sectional view of another intermediate structure 400e, which can be used to form a semiconductor package 302 according to various embodiments. The intermediate structure 400e can be formed from the intermediate structure 400d by forming a molding material 304 around one or more semiconductor devices 104 and a plurality of TMV312. The molding material 304 can be an epoxy molding compound (EMC), which can be applied to the gap between the one or more semiconductor devices 104 and the plurality of TMV312. The molding material 304 can be configured to provide mechanical support for the one or more semiconductor devices 104 and the plurality of TMV312. The EMC can include epoxy-containing compounds that can be hardened (i.e., cured) to provide a dielectric portion with sufficient stiffness and mechanical strength. In this respect, the Young's modulus of pure epoxy resin is approximately 3.34 GPa, and by adding additives, the Young's modulus of the molding material 304 can be higher than that of pure epoxy resin. Therefore, the Young's modulus of the molding material 304 can be greater than 3.4 GPa.

[0153] EMC may include epoxy resin, hardener, silica (as a filler material), and other additives. Depending on viscosity and flowability, EMC can be supplied in liquid or solid form. Liquid EMC offers better handleability, good flowability, less voids, better filling, and fewer flow marks. Solid EMC offers reduced curing shrinkage, better stand-off, and reduced die drift. High filler content in EMC (e.g., 84% by weight) can shorten mold time, reduce mold shrinkage, and reduce mold warpage. Uniform filler size distribution in EMC can reduce flow marks and enhance flowability. The curing temperature of EMC can range from 124°C to 140°C. A portion of the molding material 304 covering the horizontal surface (including the top surface of one or more semiconductor devices 104) can be removed by a planarization process (e.g., using chemical mechanical planarization (CMP)).

[0154] Figure 4F This is a vertical cross-sectional view of another intermediate structure 400f that can be used to form a semiconductor package 302 according to various embodiments. (Refer to the above text) Figure 3 The intermediate structure 400f may include one or more redistribution layers 306 formed directly on the molding material 304 and the surface of the first semiconductor device 104. The top surface of the first semiconductor device 104 may include various electrical connections (not shown) configured to be electrically coupled to the one or more redistribution layers 306, such that the one or more redistribution layers 306 are electrically coupled to the first semiconductor device 104. For example, the first semiconductor device 104 may include a plurality of first bonding pads 308a, such as... Figure 3 As shown.

[0155] One or more redistribution layers 306 may be formed on the intermediate structure 400e and may be formed as a two-dimensional array. Specifically, the redistribution layers 306 may be formed within each of a plurality of repeating cell regions (i.e., "repeating cells"). Each repeating cell may correspond to an InFO package 302 to be individually cut (e.g., see [reference]). Figure 3 The associated region. Although Figure 4F The area within the cell region is shown, but it can be understood during manufacturing. Figure 4F The structure shown is repeated in two horizontal directions.

[0156] Each redistribution layer 306 may include multiple redistribution dielectric layers 403 and multiple redistribution wiring interconnects 407. The redistribution dielectric layers 403 may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzo-bisoxazole (PBO). Each redistribution dielectric layer 306 may be formed by spin-coating and drying the dielectric polymer material. The thickness of each redistribution dielectric layer 306 may range from 2 micrometers to 40 micrometers, for example, from 4 micrometers to 20 micrometers. For example, each redistribution dielectric layer 306 may be patterned by applying and patterning a respective photoresist layer thereon, and transferring the pattern in the photoresist layer into the redistribution dielectric layer 306 using an etching process such as anisotropic etching. The photoresist layer may then be removed, for example, by ashing.

[0157] Each redistribution interconnect 407 can be formed by sputtering a metal seed layer (not shown), applying and patterning a photoresist layer (not shown) over the metal seed layer to form an opening pattern through the photoresist layer, electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the metal seed layer located between portions of the electroplated metal filler material. The metal seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The thickness of the titanium barrier layer may range from 50 nm to 300 nm, and the thickness of the copper seed layer may range from 100 nm to 500 nm. The metal filler material used for the redistribution interconnect 407 may include copper, nickel, or copper and nickel. The thickness of the metal filler material deposited for each redistribution interconnect 407 may range from 2 micrometers to 40 micrometers, for example from 4 micrometers to 10 micrometers, but smaller or larger thicknesses may also be used. The total number of wiring levels in each redistribution layer 306 (i.e., the number of levels in the redistribution wiring interconnect 407) can be in the range of 1 to 10.

[0158] The top surface of one or more redistribution layers 306 may include a coating of solder resist (SR) material 409, also referred to as a "solder resist layer". The coating of SR material 409 (e.g., a polymer material) can provide a protective coating for the one or more redistribution layers 306 and any underlying circuit patterns formed on or within the intermediate structure 400e. The SR material 409 coating also inhibits solder material from adhering to the top surface of the one or more redistribution layers 306 during the reflow process. The SR material 409 coating may include a plurality of openings 410 through which a plurality of redistribution bonding pads 412 can be exposed. The plurality of redistribution bonding pads 412 can be formed in the process used to form one or more redistribution layers 306, and thus can be electrically connected to the one or more redistribution layers 306. Additional electrical connections (e.g., bump structures), as described below, can then be formed over a plurality of first bonding pads 308a. Figure 4G A more detailed description.

[0159] Figure 4G This is a vertical cross-sectional view of another intermediate structure 400g that can be used to form a semiconductor package 302 according to various embodiments. As shown, the intermediate structure 400g can be formed by creating a plurality of third metal bumps 414. Figure 4F An intermediate structure 400f is formed. A plurality of third metal bumps 414 can be formed as a microbump structure. The plurality of third metal bumps 414 can be bump structures that can subsequently be used to electrically connect active or passive electrical devices 314 (e.g., integrated passive devices) to subsequently bond to a corresponding one of one or more redistribution layers 306. The metal filler material used for the plurality of third metal bumps 414 can include copper. The plurality of third metal bumps 414 can have a rectangular, rounded rectangular, or circular horizontal cross-sectional shape. Other horizontal cross-sectional shapes are within the scope of this disclosure. The plurality of third metal bumps 414 can be configured for microbump bonding (i.e., C2 bonding) and can have a thickness in the range of 30 micrometers to 100 micrometers, but smaller or larger thicknesses may also be used. In one embodiment, the plurality of third metal bumps 414 can be formed as an array of microbumps (e.g., copper pillars) having a lateral dimension in the range of 10 micrometers to 25 micrometers and a spacing in the range of 20 micrometers to 50 micrometers.

[0160] Figure 5A It is available for forming according to various embodiments. Figure 3 A top view of the wafer-level intermediate structure 500ab of the InFO package 302. Figure 5B According to various embodiments Figure 5A The top perspective view of the repeating unit 502 of the intermediate structure 500ab, which can be used to form the InFO package 302. (See reference above.) Figures 4A to 4DAs described, multiple TMV312s can be formed on the carrier substrate 402. For example... Figure 5A As shown, multiple TMVs 312 can be organized into multiple repeating units 502, which can be separated by multiple cuts 504. As illustrated, multiple conductive vias 312 (i.e., TMVs) can be configured to be arranged in one or more rectangular arrangements around the corresponding periphery of one or more corresponding rectangular regions (rectangular regions 506a, 506b, 506c, and 506d). In this exemplary embodiment, each repeating unit 502 includes four rectangular regions (rectangular regions 506a, 506b, 506c, and 506d). However, in other embodiments, each repeating unit 502 may contain a different number of rectangular regions.

[0161] refer to Figures 5A to 5D Each rectangular region within the repeating unit 502 (e.g., rectangular region 506a, rectangular region 506b, rectangular region 506c, rectangular region 506d) can be used as a region in which one of a plurality of semiconductor devices (e.g., semiconductor device 104) can be attached, as referenced above. Figure 4D A more detailed description follows. At this point, a pick-and-place process can be performed to place individual semiconductor devices within corresponding individual rectangular areas (rectangular areas 506a, 506b, 506c, and 506d). One or more of the plurality of TMV312 can be used as alignment marks (alignment marks 508a and 508b). In this respect, a pick-and-place tool (not shown) can use the alignment marks (alignment marks 508a and 508b) as reference points during the pick-and-place process to correctly align the semiconductor devices (e.g., semiconductor devices 104a, 104b, 104c, and 104d) relative to the rectangular areas (rectangular areas 506a, 506b, 506c, and 506d). As shown, a first type of TMV 508a can be located at a corner of the repeating unit 502, and a second type of TMV 508b can be located at the center portion of the repeating unit 502.

[0162] Figure 5CThis is a top view of a wafer-level intermediate structure 500cd that can be used to form an InFO package 302 according to various embodiments, showing four adjacent repeating units (repeating unit 502a, repeating unit 502b, repeating unit 502c, repeating unit 502d). Each of the plurality of repeating units (repeating unit 502a, repeating unit 502b, repeating unit 502c, repeating unit 502d) can be configured to be located at a predetermined distance from the center 510 of the carrier substrate 402. However, in practice, once the plurality of repeating units (repeating unit 502a, repeating unit 502b, repeating unit 502c, repeating unit 502d) is formed, the positions of the individual repeating units (repeating unit 502a, repeating unit 502b, repeating unit 502c, repeating unit 502d) may have some deviation. In this way, the pick-and-place tool can determine the position of the center of each of the multiple repeating units (repeat unit 502a, repeating unit 502b, repeating unit 502c, repeating unit 502d), and can determine the positioning correction factor that can be used when positioning the corresponding multiple semiconductor devices (semiconductor devices 104a, 104b, 104c, 104d) within the corresponding multiple rectangular areas (rectangular areas 506a, 506b, 506c, 506d). At this point, the center of each repeating unit (repeat unit 502a, repeating unit 502b, repeating unit 502c, repeating unit 502d) can be defined by determining the position of the center TMV508b within each repeating unit (repeat unit 502a, repeating unit 502b, repeating unit 502c, repeating unit 502d). As described in more detail below, each of the plurality of semiconductor devices (semiconductor device 104a, semiconductor device 104b, semiconductor device 104c, semiconductor device 104d) may be a first semiconductor device 104 (e.g., a SoC device). Other semiconductor devices may be used in other embodiments, such as a second semiconductor device 106 (e.g., an HBM device) or other types of semiconductor devices.

[0163] Figure 5D According to various embodiments Figure 5CThe top perspective view of the repeating unit 502 of the intermediate structure 500cd, which can be used to form the InFO package 302. As shown, the positions of the subsequently attached semiconductor devices (semiconductor devices 104a, 104b, 104c, 104d) can be defined relative to the measured positions of the first alignment mark 508a and the second alignment mark 508b. The defined positions may include a position error correction factor based on the actual positions of the alignment marks (alignment marks 508a, 508b) after manufacturing relative to the designed positions of the alignment marks (alignment marks 508a, 508b).

[0164] Figure 6A This is a top perspective view of repeating units 502 that can be used to form an intermediate structure 600 of a semiconductor package 302 according to various embodiments. Figure 6B yes Figure 6A A top view of a portion of the intermediate structure 600, showing details of alignment mark 508a, and Figure 6C yes Figure 6A The vertical cross-sectional view of the repeating unit shows more details of the intermediate structure 600. The intermediate structure 600 can be similar to... Figure 5D The intermediate structure is 500cd, but as Figure 6C As shown, the intermediate structure 600 may also include molding material 304, which is not in Figure 6A As shown in the image, to avoid ambiguity Figure 6A Other details

[0165] The intermediate structure 600 may include multiple semiconductor devices (semiconductor device 104a, semiconductor device 104b, semiconductor device 104c, semiconductor device 104d) placed in a rectangular area defined by multiple TMV312s, as referenced above. Figures 5A to 5D As described above, each repeating unit 502 can be separated from adjacent repeating units by multiple cutting tracks 504 (also called cutting lines or saw marks). As described above, one or more of the plurality of TMV312 can be used as alignment marks (alignment mark 508a, alignment mark 508b). In this regard, as referenced above... Figure 5B As described, multiple TMV312s can be used as corner alignment marks 508a or center alignment marks 508b ( Figures 6A to 6C (Not shown in the image). In another embodiment, one or more TMVs may be formed within one or more cutting paths 504 to form cutting alignment marks 508c.

[0166] like Figure 6BAs shown, the corner alignment mark 508a can be formed as a set of TMVs, which includes a plurality of first TMVs 312a having a first specific size (e.g., a first cylindrical diameter) and a plurality of second TMVs 312b having a second specific size corresponding to and larger than the first specific size (e.g., a second cylindrical diameter). The size and positioning of the plurality of TMVs (first TMVs 312a, second TMVs 312b) used for the alignment marks (alignment mark 508a, alignment mark 508b) can differ from the other plurality of TMVs 312 that can provide circuit connection functions. For example, as Figure 6B As shown, in addition to the plurality of first TMV312a and plurality of second TMV312b used as alignment marks (alignment mark 508a, alignment mark 508b), the intermediate structure 600 may also include a plurality of third TMV312c. As shown, each TMV (first TMV312a, second TMV312b, third TMV312c) may have an axis of symmetry that may be parallel to the thickness direction (i.e., the z-axis).

[0167] Multiple third TMV312cs can be configured to operate in a rectangular area (e.g., Figure 5A A rectangular arrangement surrounding the periphery of regions 506a to 506d, wherein one or more semiconductor devices (e.g., Figure 6B Semiconductor device 104d in the middle). Figure 6B As shown, multiple third TMV312cs can be arranged in multiple parallel rows. In Figure 6B In an exemplary embodiment, there are four parallel rows of third TMV312c arranged along multiple edges of the repeating unit 502. Alternatively, in other embodiments, multiple third TMV312c may be arranged in a single row, for example as... Figures 5A to 5D As shown, and for the sake of simplicity, as Figure 6A As shown. In other embodiments, multiple third TMV312cs can be arranged in two parallel rows, three parallel rows, five parallel rows, etc.

[0168] like Figure 6C As shown, the plurality of first TMV312a of the first alignment mark 508a can have small specific dimensions and be closely spaced. Therefore, they can provide highly accurate reference marks that can be used in pick-and-place operations to precisely place semiconductor devices (semiconductor devices 104a, 104b, 104c, 104d) within the intermediate structure 600. See below for reference. Figures 7A to 7EIn more detail, the plurality of second TMV312b can be “dummy” TMVs (DMYs) that can achieve the purpose of adjusting the spatial distribution of current density during the electroplating process to improve the specific diameter uniformity (SDU) and coplanarity of the TMVs (first TMV312a, second TMV312b, and third TMV312c). Thus, the plurality of second TMV312b themselves can be disregarded for alignment markings when positioning semiconductor devices (semiconductor devices 104a, 104b, 104c, and 104d). The molding material 304 can have a plate geometry having a length direction (i.e., the x-direction), a width direction (i.e., the y-direction), and a thickness direction (i.e., the z-direction). As described above, each TMV (first TMV312a, second TMV312b, and third TMV312c) can have an axis of symmetry (i.e., a cylindrical axis of symmetry) parallel to the thickness direction (i.e., along the z-direction).

[0169] exist Figure 6C In an exemplary embodiment, as shown in the figure, the distribution of multiple TMVs (first TMV 312a, second TMV 312b, and third TMV 312c) includes multiple first TMVs 312a, multiple second TMVs 312b, and a third TMV 312c located in the central region of the repeating unit 502. The third TMV 312c can provide circuit connection functionality, while in other embodiments, the TMV located in the central region of the repeating unit 502 can be configured as a second alignment mark 508b, as referenced above. Figure 5B and Figure 5C As described. At this point, the second alignment mark 508b ( Figure 6C (Not shown) can be configured similarly to the first alignment mark 508a and can include a plurality of first TMV312a and a plurality of second TMV312b. In other embodiments, the second alignment mark may include only the third TMV312c, without including the first TMV312a and the second TMV312b.

[0170] Figure 7A This is a top view of a wafer-level intermediate structure that can be used to form related semiconductor packages. Figure 7B yes Figure 7A A top view of the first part of the intermediate structure, showing a molded through-hole (TMV) 312 that can be used as an alignment mark, and Figure 7C yes Figure 7A A vertical cross-sectional view of the first part of the intermediate structure, which shows the non-uniformity of TMV312. Figure 7D yes Figure 7AA top view of the second part of the intermediate structure, showing a molded through-hole (TMV) that can be used as an alignment mark, and Figure 7E yes Figure 7A A vertical cross-sectional view of the second part of the intermediate structure, which shows the non-uniformity of TMV.

[0171] Figure 7A The wafer-level intermediate structure may include multiple repeating units 502. Figure 7B A top view of the corner of the first repeating unit 502a is shown. Figure 7C A vertical cross-sectional view of multiple TMV312 formed in patterned photoresist 406 near the corner of the first repeating unit 502a is shown. Similarly, Figure 7D The rotation angle of the second repeating unit 502b is shown, and Figure 7E A vertical cross-sectional view of multiple TMV312 formed in patterned photoresist 406 near the corner of the second repeating unit 502b is shown.

[0172] like Figure 7A As shown, the corner of the first repeating unit 502a can be located near the central region of the wafer-level intermediate structure, while the corner of the second repeating unit 502b can be located near the edge of the wafer-level intermediate structure. In this respect, the local environments experienced by the first repeating unit 502a and the second repeating unit 502b may differ. Therefore, during the electroplating process, the spatial distribution of the current density can vary as a function of the location across the wafer-level intermediate structure, allowing certain TMVs to be generated with a higher current density than in regions where other TMVs can be formed.

[0173] Since the electroplating deposition rate depends on the local current density, some TMVs may grow faster than others. Thus, the resulting multiple TMV312s can have a non-uniform height distribution, such as... Figure 7C and Figure 7E As shown. In this respect, the TMV312 in the second repeating unit 502b can be near the edge of the second repeating unit 502b (e.g., in...). Figure 7E Near the left edge, some TMV312ds have a greater height. Furthermore, some TMV312ds can be grown to a height exceeding the height of the patterned photoresist. Thus, some TMV312ds can have a top portion that extends laterally beyond the via diameter. When imaged from above, such a laterally extended TMV312d may appear to have a larger diameter than other TMV312e. Therefore, this variation in the top-view diameter between the various TMVs (TMV312d, TMV312e) can lead to inaccurate alignment when these TMVs (TMV312d, TMV312e) are used as alignment markers.

[0174] Figure 7F This is a top view of another wafer-level intermediate structure that can be used to form a semiconductor package, according to various embodiments. Figure 7G yes Figure 7F A top view of the first part of the intermediate structure, showing details of the first alignment marks containing multiple first TMVs and multiple second TMVs, and Figure 7H yes Figure 7F A vertical cross-sectional view of the first portion of the intermediate structure, showing the improved uniformity of the first TMV. According to various embodiments, Figure 7I yes Figure 7F A top view of the second part of the intermediate structure, which shows details of the second alignment marks containing multiple first TMVs and multiple second TMVs, and Figure 7J yes Figure 7F A vertical cross-sectional view of the second part of the intermediate structure, which shows the improved uniformity of the first TMV.

[0175] like Figure 7H and Figure 7J As shown, the presence of multiple second TMV312b (i.e., "dummy" (DMY) TMVs with larger specific dimensions) can be used to reduce the non-uniformity in the height of the multiple first TMV312a. In this respect, the second TMV312b can be used to control the current density to have a higher uniformity than... Figures 7B to 7E The comparative embodiment has a more uniform spatial distribution. Therefore, although the height of the plurality of first TMV312a of the first repeating unit 502a (i.e., Figure 7H As shown) relative to the second repeating unit 502b, a plurality of first TMV312a (i.e., Figure 7J The height (as shown) may vary, but such height variations may not be noticeable when imaging the corresponding plurality of first TMV312a from above. In this respect, as... Figure 7H and Figure 7J As shown, the height of TMV312a can be controlled so as not to exceed the thickness of the patterned photoresist 406. In this way, the patterned photoresist 406 can constrain the plurality of first TMV312a to have a predetermined diameter, because the first TMV312a is constrained not to extend laterally over the surface of the patterned photoresist 406.

[0176] therefore, Figure 7G and Figure 7H The first alignment mark 508a, the first TMV312a, and Figure 7I and Figure 7J The second alignment mark 508b of the first TMV312a can exhibit better uniformity of specific dimensions (i.e., diameter) and a greater degree of coplanarity. Thus, Figures 7F to 7JThe first TMV312a can provide alignment mark 508a, which can allow for alignment relative to existing alignment mark 312 (such as...). Figures 7A to 7E Those shown in the comparative embodiments (i.e., Figure 7C and Figure 7E The TMV312b in the image increases alignment accuracy. Conversely, multiple second TMV312b can extend over the surface of the patterned photoresist 406 and therefore can extend laterally to any extent beyond the diameter of the corresponding TMV (e.g., ...). Figure 7H and 7J (As shown) may not affect alignment accuracy. This is because such second TMV312b are not used when aligning semiconductor devices (semiconductor devices 104a, 104b, 104c, 104d) with respect to repeating unit 502, but are instead used as "dummy TMVs" because their presence may be beneficial for controlling the current distribution near multiple first TMV312a.

[0177] According to various embodiments, Figure 8A It is a top view including the alignment marks of the first TMV312a and the second TMV312b, and Figure 8B yes Figure 8A An enlarged top view of the alignment marks, which shows the geometric details of the first TMV312a and the second TMV312b. Figure 8C It is a top view of another alignment mark including multiple first TMV312a and a single second TMV312b, and Figure 8D This is a top view of another alignment mark including a single first TMV312a and multiple second TMV312b. (See image) Figure 8A As shown, alignment mark 508 may include a plurality of first TMV312a surrounded by a plurality of second TMV312b. In other embodiments, such as Figure 8C As shown, multiple second TMV312b can be replaced by a single TMV312b having a ring geometry. In another embodiment, as... Figure 8D As shown, multiple first TMV312a can be replaced by a single first TMV312a. For example... Figure 8D As shown, the first TMV312a can be a symmetrical shape (i.e., cross-shaped) with multiple rectangular members. Thus, the first TMV312a can include at least one plane of symmetry (i.e., along the x-axis or along the y-axis in this exemplary embodiment).

[0178] like Figure 8BAs shown, alignment mark 508 may include one or more first TMV 312a located in a first region 802a and one or more second TMV 312b located in a second region 802b surrounding the first region. The first region may have a diameter 804a between 100 micrometers and 1000 micrometers, and the second region may have an annular geometry having an inner diameter 804b between 120 micrometers and 1600 micrometers and an outer diameter 804c between 270 micrometers and 2000 micrometers. Figure 8B As shown, the first region 802a and the second region 802b can be separated from each other by a third region 802c, which also has an annular geometry with a width 804d between 10 micrometers and 300 micrometers. According to various embodiments, each of the plurality of first TMV312a may have a first specific dimension (e.g., a first diameter) between 10 micrometers and 150 micrometers. Similarly, each of the plurality of second TMV312b may have a second specific dimension (e.g., a second diameter) between 100 micrometers and 500 micrometers.

[0179] Figure 9 A top view of various types of TMVs (first TMV 312a, second TMV 312b) according to various embodiments is shown. For example, one or more first TMVs 312a and one or more second TMVs 312b can have the following shapes in a plane perpendicular to the axis of symmetry (i.e., when viewed in the top view): a circle, a triangle, a square, or an n-sided polygon. As shown, for such shapes, the first TMV 312a can have a specific dimension (SD) (e.g., side, width, diameter, etc.) between 10 micrometers and 150 micrometers. Similarly, the second TMV 312b can have an SD corresponding to the SD of the first TMV 312a (e.g., side, width, diameter, etc.). The SD of the second TMV 312b can be between 100 micrometers and 500 micrometers. In other embodiments, the first TMV 312a can be configured into various special shapes. For example, as Figure 9 As shown, each particular shape can be configured to include two or more connected rectangular segments (e.g., cross-shaped, L-shaped, T-shaped, etc.) with a specific size between 10 micrometers and 150 micrometers. In yet another embodiment, the second TMV312b may have a core-shell geometry with an SD between 50 micrometers and 1000 micrometers.

[0180] The spatial arrangement of the first TMV 312a and the second TMV 312b can correspond to a specific pattern density, defined as the percentage of the first region represented by the TMVs (312a, 312b) relative to the second region represented by the surrounding molding material 304. In this regard, one or more first TMVs 312a located in the first region 802a (see, for example, [reference needed]) Figure 8B This can correspond to a first pattern density between 0.5% and 5%, and one or more second TMV312b located in the second region 802b (see, for example, [link to relevant documentation]). Figure 8B This can correspond to a second pattern density between 10% and 100%. Furthermore, according to some embodiments, the ratio of the second pattern density to the first pattern density can be between 20 and 200.

[0181] Figures 10A to 13E Various alternative processes according to various embodiments are shown, including vertical cross-sectional views of a plurality of intermediate structures (intermediate structures 1000a to 1000d, 1100a, 1100b, 1100c, 1100d, 1100e, 1200a, 1200b, 1200c, 1200d, 1300a, 1300b, 1300c, 1300d, and 1300e) that can be used to form semiconductor package 302. In this respect, Figures 10A to 13E The process flow is similar to the one mentioned above. Figures 4A to 4G The process flow is described, but various alternative configurations are provided regarding the orientation of one or more redistribution layers (redistribution layer 306, first redistribution layer 306a, second redistribution layer 306b) and the semiconductor device 104. For example, in Figures 10A to 10D and Figures 11A to 11E In the process flow, multiple semiconductor devices 104 can be oriented in an upward configuration, while Figures 12A to 12D and Figures 13A to 13E In the process flow, multiple semiconductor devices 104 can be oriented in a face-down configuration. Furthermore, according to various embodiments, the semiconductor package 302 may include a single redistribution layer 30 formed over the multiple semiconductor devices 104 (e.g., see...). Figure 4G , Figure 10A and Figure 12D ), or may include a first redistribution layer 306a and a second redistribution layer 306b respectively formed below and above the plurality of semiconductor devices 104 (e.g., see Figure 11E and Figure 13E ).

[0182] exist Figures 10A to 10DIn the process flow, multiple TMVs (first TMV 312a, second TMV 312b, and third TMV 312c) can be first formed on the carrier substrate 402, such as... Figure 10A As shown, and referring to the above. Figures 4A to 4D Describe in more detail. Then, as... Figure 10B As shown and refer to the above. Figure 4D In more detail, multiple semiconductor devices 104 can be attached to the carrier substrate 402 in an upward-facing configuration. Then, they can be... Figure 10B The intermediate structure 1000b is formed with molding material 304 to form Figure 10C The intermediate structure 1000c, as shown above. Figure 4E A more detailed description. The redistribution layer 306 can form in... Figure 10C The intermediate structure above 1000c forms Figure 10D The intermediate structure 1000d, as shown above. Figure 4F and Figure 4G To describe in more detail.

[0183] Figures 11A to 11E The process flow can be similar Figures 10A to 10D The process flow differs from the previous one in that, in the first process operation, a first redistribution layer 306a can be formed on the substrate 402, for example, as shown in the example. Figure 11A As shown. Figures 11B to 11E The remaining process operations shown can be similar. Figures 10A to 10D The corresponding process operations are shown. Figures 12A to 12D The process operation shown can be similar to Figures 10A to 10D In addition to the process operations where multiple semiconductor devices 104 can be attached to the carrier substrate 402 in a face-down configuration, similarly, Figures 13A to 13E The process operations shown can be combined with Figures 11A to 11D The process operation is similar, except that multiple semiconductor devices 104 can be attached to the carrier substrate 402 in a face-down configuration.

[0184] Figure 14This is a flowchart illustrating process operations of a method 1400 for forming a semiconductor package 302 according to various embodiments. In operation 1402, method 1400 may include forming a plurality of conductive vias (conductive via 312, first conductive via 312a, second conductive via 312b) on a substrate 402, the plurality of conductive vias including alignment marks (alignment marks 508a, alignment marks 508b) having the first conductive via 312a and the second conductive via 312b. The first conductive via 312a may have a first specific size (e.g., a cylinder diameter) and the second conductive via 312b may include a second specific size (e.g., a cylinder diameter) corresponding to and larger than the first specific size. In operation 1404, method 1400 may include positioning semiconductor devices (first semiconductor device 104, second semiconductor device 106) on the substrate 402 and aligning the semiconductor devices (first semiconductor device 104, second semiconductor device 106) relative to the alignment marks (alignment marks 508a, alignment marks 508b). In operation 1406, method 1400 may include attaching semiconductor devices (first semiconductor device 104, second semiconductor device 106) to substrate 402. In operation 1408, method 1400 may include forming a molding material 304 around the semiconductor devices (first semiconductor device 104, second semiconductor device 106) and a plurality of conductive vias 312, such that the plurality of conductive vias 312 include a corresponding plurality of TMVs (first TMV 312a, second TMV 312b).

[0185] When forming a plurality of conductive vias 312 according to operation 1402, method 1400 may further include forming a patterned photoresist 406 having a plurality of via openings 408 on a substrate 402, and performing an electroplating process to deposit conductive material in the plurality of via openings 408, thereby forming a plurality of conductive vias 312. In this regard, forming the patterned photoresist 406 may further include forming a plurality of via openings 408, such that a second specific size is between 100 micrometers and 500 micrometers and a first specific size is between 10 micrometers and 150 micrometers.

[0186] When forming a plurality of conductive vias (conductive vias 312, first conductive via 312a, second conductive via 312b) according to operation 1402, method 1400 may further include forming a plurality of conductive vias 312 arranged in a rectangular configuration around the periphery of the first rectangular region 506a. When attaching semiconductor devices (first semiconductor device 104, second semiconductor device 106) to the substrate 402 according to operation 1406, method 1400 may further include positioning, aligning and attaching the semiconductor devices (first semiconductor device 104, second semiconductor device 106) to the substrate 402 within the first rectangular region 506a. In another embodiment, forming a plurality of conductive vias (conductive vias 312, first conductive vias 312a, second conductive vias 312b) according to operation 1402 of method 1400 may further include forming a plurality of conductive vias (conductive vias 312, first conductive vias 312a, second conductive vias 312b) of a plurality of repeating units 502 configured to be separated by a plurality of cutting paths 504, such that each of the plurality of repeating units 502 may include a rectangular arrangement of one or more conductive vias 312, each rectangular arrangement being located around the periphery of a corresponding rectangular region, thereby forming a plurality of rectangular regions (rectangular region 506a, rectangular region 506b, rectangular region 506c, rectangular region 506d). Method 1400 may further include forming one or more first alignment marks 508a to include a first conductive via 312a and a second conductive via 312b in each of the plurality of repeating units 502, and forming one or more second alignment marks 508c to include the first conductive via 312a and the second conductive via 312b in one or more cut channels 504 between corresponding adjacent repeating units 502.

[0187] Referring to all the accompanying drawings and various embodiments disclosed herein, a semiconductor package 302 is provided. The semiconductor package 302 may include semiconductor devices (first semiconductor device 104, second semiconductor device 106), a molding material 304 laterally surrounding the semiconductor devices (first semiconductor device 104, second semiconductor device 106), and alignment marks (alignment marks 508a, alignment marks 508b) including a first TMV 312a and a second TMV 312b respectively formed in the molding material 304. According to various embodiments, the first TMV 312a may include a first specific size, and the second TMV 312b may include a second specific size larger than the first specific size. The semiconductor package 302 may also include a rectangular geometry, and the alignment mark 508a may be located near a corner of the semiconductor package 302.

[0188] Alignment marks (alignment mark 508a, alignment mark 508b) may also include one or more first TMV 312a located in the first region 802a and one or more second TMV 312b located in the second region 802b surrounding the first region 802a. According to various embodiments, the first region 802a may include a diameter 804a between 100 micrometers and 1000 micrometers, and the second region 802b may include an annular geometry having an inner diameter 804b between 120 micrometers and 1600 micrometers and an outer diameter 804c between 270 micrometers and 2000 micrometers. The first region 802a and the second region 802b may be separated from each other by a third region 802c, which may include another annular geometry having a width 804d between 10 micrometers and 300 micrometers. According to various embodiments, one or more first TMV312a located in the first region 802a may have a first pattern density between 0.5% and 5%, and one or more second TMV312b located in the second region 802b may have a second pattern density between 10% and 100%. In some embodiments, the ratio of the second pattern density to the first pattern density may be between 20 and 200. In other embodiments, one or more second TMV312b may comprise a single TMV312b having a ring geometry.

[0189] According to another embodiment, one or more first TMV312a and one or more second TMV312b each have a shape in a plane (i.e., the xy plane) perpendicular to the axis of symmetry (i.e., the z-axis), including a circle, triangle, square, or n-sided polygon. Furthermore, a first specific dimension may be between 10 micrometers and 150 micrometers, and a second specific dimension may be between 100 micrometers and 500 micrometers. In some embodiments, one or more second TMV312b may have a core-shell geometry and a second specific dimension between 50 micrometers and 1000 micrometers. Alternatively, one or more first TMV312a may each have a shape in a plane (i.e., the xy plane) perpendicular to the axis of symmetry (i.e., the z-axis), comprising two or more connected rectangular segments (e.g., see...). Figure 9 The first specific size can be between 10 micrometers and 150 micrometers. In some embodiments, one or more first TMV312a and one or more second TMV312b are each arranged to have at least one plane of symmetry (e.g., with). Figure 8B Spatial configuration (aligned with the y-axis).

[0190] Referring to all the accompanying drawings and various embodiments of this disclosure, yet another semiconductor package 302 is provided. The semiconductor package 302 may include a molding material 304 having a rectangular plate geometry including a length direction (i.e., the x-direction), a width direction (i.e., the y-direction), and a thickness direction (i.e., the z-direction), including alignment marks 508a for a first TMV 312a and a second TMV 312b, both formed in the molding material 304 and having corresponding axes of symmetry (i.e., cylindrical axes) parallel to the thickness direction (i.e., the z-direction). The first TMV 312a may have a first specific dimension, and the second TMV 312b may have a second specific dimension larger than the first specific dimension. The semiconductor package 302 may also include a plurality of third TMVs 312c formed in the molding material 304, each third TMV 312c including another axis of symmetry parallel to the thickness direction (i.e., the z direction), such that the plurality of third TMVs are arranged in a rectangular manner around the periphery of the first rectangular region 506a in a plane spanned by the length and width directions.

[0191] The semiconductor package 302 may further include semiconductor devices (first semiconductor device 104, second semiconductor device 106) located within a first rectangular region 506a and laterally surrounded by molding material 304, such that a first specific dimension is between 10 micrometers and 150 micrometers, and a second specific dimension is between 100 micrometers and 500 micrometers. According to various embodiments, alignment marks 508 may further include one or more first TMV312a having a first pattern density between 0.5% and 5% and one or more second TMV312b having a second pattern density between 10% and 100%. The one or more first TMV312a and one or more second TMV312b may each be arranged to have at least one plane of symmetry (e.g., with...). Figure 8B Spatial configuration (aligned with the y-axis).

[0192] The disclosed embodiments can provide advantages over existing semiconductor packages. In this regard, the semiconductor package 302 may include alignment marks (alignment mark 508a, alignment mark 508b) having a first TMV 312a and a second TMV 312b. The second TMV 312b may have a specific dimension (e.g., side, width, diameter, etc.) larger than that of the first TMV 312a. Both the first TMV 312a and the second TMV 312b can be formed by an electroplating process, and the presence of a larger second TMV 312b can regulate the electroplating current density to achieve a more uniform spatial distribution than would be possible if all TMVs (TMV 312, first TMV 312a, second TMV 312b) had the same size. In this respect, the uniformity and coplanarity of the resulting TMVs' specific diameter can be improved. Therefore, the smaller size of the first TMV312a allows for increased positioning accuracy when used as an alignment mark during pick-and-place operations to position semiconductor devices (first semiconductor device 104, second semiconductor device 106) within the semiconductor package 302.

[0193] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor package, characterized in that, include: Semiconductor devices; Molding material, laterally surrounding the semiconductor device; as well as Alignment marks, including a first molding through-hole and a second molding through-hole, each of the first molding through-hole and the second molding through-hole being formed in the molding material. The first molded through-hole includes a first specific size, and the second molded through-hole includes a second specific size that is larger than the first specific size.

2. The semiconductor package according to claim 1, characterized in that, The semiconductor package includes a rectangular geometry, and the alignment mark is located near a corner of the semiconductor package.

3. The semiconductor package according to claim 1, characterized in that, The alignment mark also includes: One or more first molded through holes located in the first region; and One or more second molded through holes located in a second region surrounding the first region.

4. The semiconductor package according to claim 3, characterized in that: The first region includes a diameter between 100 micrometers and 1000 micrometers; and The second region includes an annular geometry having an inner diameter between 120 micrometers and 1600 micrometers and an outer diameter between 270 micrometers and 2000 micrometers.

5. The semiconductor package according to claim 3, characterized in that, The one or more second molded through holes include a single molded through hole having an annular geometry.

6. The semiconductor package according to claim 3, characterized in that, The one or more first molded through holes and the one or more second molded through holes each have a circular, triangular, square, or n-sided polygonal shape in a plane perpendicular to the axis of symmetry.

7. The semiconductor package according to claim 3, characterized in that: Each of the one or more first molded through holes includes a shape in a plane perpendicular to the axis of symmetry, the shape comprising two or more connected rectangular segments; and The first specific size is between 10 micrometers and 150 micrometers.

8. A semiconductor package, characterized in that, include: Molding material, including a rectangular plate geometry, the rectangular plate geometry including a length direction, a width direction and a thickness direction; Alignment marks, including a first molding through-hole and a second molding through-hole, each of the first molding through-hole and the second molding through-hole being formed in the molding material and having a corresponding axis of symmetry parallel to the thickness direction, wherein the first molding through-hole includes a first specific size and the second molding through-hole includes a second specific size greater than the first specific size; as well as A plurality of third molding through holes are formed in the molding material, each of the plurality of third molding through holes including another axis of symmetry parallel to the thickness direction, wherein the plurality of third molding through holes are arranged in a rectangular manner around the periphery of the first rectangular region in a plane spanned by the length direction and the width direction.

9. The semiconductor package according to claim 8, characterized in that, Also includes: The semiconductor device is located within the first rectangular region and is laterally surrounded by the molding material, wherein: The first specific size is between 10 micrometers and 150 micrometers; as well as The second specific size is between 100 micrometers and 500 micrometers.

10. The semiconductor package according to claim 8, characterized in that, The alignment mark also includes: One or more first molded through-holes, including a first pattern density between 0.5% and 5%; and One or more second molded through-holes, comprising a second pattern density between 10% and 100%, The one or more first molded through holes and the one or more second molded through holes are each arranged in a spatial configuration having at least one plane of symmetry.

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