Joint grain structure

Abstract

Bonded die structures are provided that have fewer defects and higher reliability. A bonded die structure includes a first die and a second die, the first die bonded to the second die at a bonding interface. The bonded die structure includes a sidewall having a non-planar, wavy surface, and a plane that includes the bonding interface and intersects the sidewall. A laser grooving process can be used to "pre-cut" the bonded device structure prior to a final dicing process, and can form a relatively deep groove in the bonded device structure that can extend beyond the bonding interface between the first and second device structures. A final dicing process along the pre-groove can be used to separate individual bonded die structures. Because the dicing is along a deep pre-groove that extends through the bonding interface between the stacked device structures, the dicing blade can not cut through or contact the bonding interface. This can result in reduced mechanical stress to reduce the occurrence of delamination defects between the device structures, providing better reliability and improved yield.

Description

Technical Field

[0001] This disclosure relates to a bonded grain structure. Background Technology

[0002] The semiconductor industry has become quite mature due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.).

[0003] Beyond smaller electronic components, improvements have been developed to enhance component packaging in an effort to provide smaller packages that occupy less area than previous packages. Exemplary methods include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), three-dimensional integrated circuits (3DIC), wafer-level packages (WLP), packages on packages (PoP), system-on-a-chip (SoC), or system-on-integrated-circuit (SoIC) devices. Parts of the fabrication of 3D devices involve placing wafers on top of each other. These 3D devices offer improved integration density and other advantages due to the reduced interconnect lengths between stacked wafers. However, many challenges exist associated with 3D devices. Utility Model Content

[0004] Some embodiments disclosed herein provide a bonded grain structure. The bonded grain structure includes a first grain comprising a first semiconductor substrate and a second grain comprising a second semiconductor substrate, wherein the first grain is bonded to the second grain at a bonding interface. The bonded grain structure includes sidewalls having a non-flat, wavy surface and a plane comprising a bonding interface and intersecting the sidewalls of the bonded grain structure.

[0005] Other embodiments disclosed herein provide a bonding grain structure. The bonding device structure includes a first grain comprising a first semiconductor substrate and a second grain comprising a second semiconductor substrate, wherein the first grain is bonded to the second grain at a bonding interface. The bonding grain structure includes sidewalls having a non-flat, wavy surface, and the bonding interface between the first and second grains is exposed along the sidewalls of the bonding grain structure.

[0006] Further embodiments disclosed herein provide a bonded grain structure. The bonded grain structure includes a first grain comprising a first semiconductor substrate and a second grain comprising a second semiconductor substrate, wherein the first grain is bonded to the second grain at a bonding interface. The bonded grain structure has at least one sidewall, a front side abutting one end of the at least one sidewall, at least one side surface abutting the other end of the at least one sidewall, and a rear side abutting the at least one side surface. The bonded grain structure has a shape that tapers inward along at least one sidewall, with the lateral width of the front side being smaller than the lateral width of the rear side. Attached Figure Description

[0007] The embodiments disclosed herein can be better understood by reading in conjunction with the accompanying drawings. It is worth noting that, according to standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0008] Figure 1 A vertical cross-sectional view of a portion of a first device structure according to various embodiments of the present disclosure is shown;

[0009] Figure 2 A vertical cross-sectional view of a portion of a second device structure according to various embodiments of the present disclosure is shown;

[0010] Figure 3 A vertical cross-sectional view of a second device structure joined to a first device structure to form a joining device structure according to various embodiments of the present disclosure is shown.

[0011] Figure 4 This is a vertical cross-sectional view of a jointing device structure including multiple grooves formed in the jointing device structure according to various embodiments of the present disclosure;

[0012] Figure 5 This is a vertical cross-sectional view of the grain structure according to various embodiments of the present disclosure;

[0013] Figure 6 This is a vertical cross-sectional view of a bonding grain structure according to various embodiments of the present disclosure, and the bonding grain structure includes a plurality of solder balls above the front side of the bonding grain structure;

[0014] Figure 7 A vertical cross-sectional view of the grain structure on the support structure according to various embodiments of the present disclosure is shown;

[0015] Figure 8 A vertical cross-sectional view of a coupling device structure having a plurality of first grooves formed in a coupling device structure according to another embodiment of the present disclosure is shown.

[0016] Figure 9This is a vertical cross-sectional view of a jointing device structure including a plurality of second grooves formed in the jointing device structure according to another embodiment of the present disclosure;

[0017] Figure 10 This is a vertical cross-sectional view of the grain structure according to another embodiment of this disclosure;

[0018] Figure 11 This is a vertical cross-sectional view of a jointing device structure including a plurality of first grooves formed in the jointing device structure according to another embodiment of the present disclosure;

[0019] Figure 12 This is a vertical cross-sectional view of a jointing device structure including a plurality of second grooves formed in the jointing device structure according to another embodiment of the present disclosure;

[0020] Figure 13 This is a vertical cross-sectional view of the grain structure according to another embodiment of this disclosure;

[0021] Figure 14 This is a vertical cross-sectional view of a jointing device structure including a plurality of first grooves formed in the jointing device structure according to another embodiment of the present disclosure;

[0022] Figure 15 This is a vertical cross-sectional view of a jointing device structure including a plurality of second grooves formed in the jointing device structure according to another embodiment of the present disclosure;

[0023] Figure 16 This is a vertical cross-sectional view of the grain structure according to another embodiment of this disclosure;

[0024] Figure 17 A vertical cross-sectional view of a joining device structure according to another embodiment of this disclosure is shown;

[0025] Figure 18 This is a vertical cross-sectional view of a jointing device structure including multiple grooves formed in the jointing device structure according to various embodiments of the present disclosure;

[0026] Figure 19 This is a vertical cross-sectional view of the grain structure according to another embodiment of this disclosure;

[0027] Figure 20 This is a vertical cross-sectional view of a jointing device structure including a plurality of grooves formed in the jointing device structure according to another embodiment of the present disclosure;

[0028] Figure 21 This is a vertical cross-sectional view of the grain structure according to another embodiment of this disclosure;

[0029] Figure 22A vertical cross-sectional view of a bonding device structure according to an embodiment of the present disclosure is shown, and the bonding device structure includes a bonding grain structure disposed on a carrier structure and laterally surrounded by a gap-filling dielectric material.

[0030] Figure 23 This is a vertical cross-sectional view of a joining device structure including multiple grooves formed in a gap-filling dielectric material according to various embodiments of the present disclosure;

[0031] Figure 24 This is a vertical cross-sectional view of the grain structure according to another embodiment of this disclosure; and

[0032] Figure 25 A flowchart illustrating a method for manufacturing a bonded grain structure according to an embodiment of the present disclosure is shown.

[0033] [Symbol Explanation]

[0034] 100: Structure of the first device

[0035] 101: First Semiconductor Substrate

[0036] 102, 202, 302: Front surface

[0037] 103, 203, 303: Rear side surface

[0038] 105: First interconnect structure / interconnect structure

[0039] 106, 206, 208, 306: Dielectric materials

[0040] 107, 207, 307: Metallic characteristics

[0041] 108, 308, 408: Dielectric material layer

[0042] 109: First bonding layer

[0043] 110,110a: First metal bonding feature / metal feature / bonding feature

[0044] 111, 311, 411: Bonding pads

[0045] 113, 213, 313, 413: Connecting through holes

[0046] 114: First TSV / First Through Silicon Via

[0047] 120,220: Joint interface

[0048] 122: Flat upper surface

[0049] 130: slot

[0050] 130a: First slot

[0051] 130b: Second slot

[0052] 131: Sidewall

[0053] 133: Side surface

[0054] 135: Discontinuous ridge features

[0055] 140: First grain

[0056] 150, 160: Bonding device structure / Bonding grain structure / Semiconductor structure

[0057] 155: Carrier Structure

[0058] 157: Supporting Structure

[0059] 200: Structure of the second device

[0060] 201: Second semiconductor substrate

[0061] 205: Second interconnect structure

[0062] 209: Second bonding layer

[0063] 210, 210a: Second metal bonding feature / metal feature

[0064] 211: Bonding Pad / Metal Feature

[0065] 214: Second TSV / Second Through Silicon Via

[0066] 221: Front side / Front surface / Surface / First side

[0067] 222: Rear side / Rear surface / Second side

[0068] 225: Welding ball

[0069] 240: Second grain

[0070] 260: Local Minimum

[0071] 300: Structure of the third device

[0072] 301: Third semiconductor substrate

[0073] 305: Third interconnect structure

[0074] 309: Third bonding layer

[0075] 310, 310a: Third metal bonding characteristics

[0076] 314: Third TSV

[0077] 340: Third grain

[0078] 409: Fourth bonding layer

[0079] 410, 410a: Fourth metal bonding feature

[0080] 501: Dielectric material

[0081] 600: Method

[0082] 601, 603: Steps

[0083] UA: Cell Region Detailed Implementation

[0084] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0085] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “bottom,” “lower,” “upper,” and similar terms may be used herein to describe the relationship between one component or feature and another component or feature as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and therefore the spatial relative descriptive terms used herein may be interpreted accordingly. Unless otherwise explicitly stated, each component with the same reference numerals is considered to have the same material composition and thickness within the same thickness range.

[0086] The various embodiments disclosed herein relate to semiconductor devices, and more specifically to a bonding die structure comprising multiple semiconductor integrated circuit (IC) dies bonded together. The bonded semiconductor IC dies can be, for example, system-on-a-chip (SoIC), chip-on-wafer-on-substrate (chip-on-wafer-on-substrate), etc. Configurations such as chip-on-wafer (CoW) and other chip-on-wafer (COW) stacking can increase the device density occupying a given planar area or "footprint".

[0087] Semiconductor integrated circuits may include a semiconductor material substrate, such as a silicon substrate, having multiple circuit elements and components formed on and / or in the semiconductor material. Semiconductor integrated circuits are typically manufactured by sequentially depositing multiple insulating or dielectric layers, multiple conductive layers, and multiple semiconductor layers on a semiconductor substrate (e.g., a wafer), and patterning the various material layers using photolithography to form the integrated circuit.

[0088] A bonding device structure can be formed by placing a second device structure (e.g., a semiconductor substrate or die, optionally having an integrated circuit formed thereon) onto a first device structure (e.g., a separate semiconductor substrate or die, optionally having an integrated circuit). The bonding process can be configured to bond bonding features on the first device structure to corresponding bonding features on the second device structure. In some embodiments, multiple device structures can be bonded to form a bonding device structure using direct bonding techniques (e.g., metal-to-metal (MM) and dielectric-to-dielectric (DD) bonding techniques). In such bonding techniques, a bonding layer comprising an array of metal bonding pads surrounded by dielectric material can be formed on the structures to be bonded. The bonding layers on the second device structure can be aligned over corresponding bonding layers on the first device structure, and the two bonding layers can be in contact with each other. This allows for chemical pre-bonding between the dielectric materials of the corresponding bonding layers. An annealing process can then be performed to promote bonding of the metal bonding pads of each bonding layer, thereby creating a metal bond extending between the first and second device structures. Other types of bonding processes can also be used, such as fusion bonding between dielectric bonding material layers.

[0089] In some embodiments, a dicing process may be configured to separate multiple portions of a bonding device structure to form individual bonding die structures, wherein each bonding die structure may include a stack of two or more semiconductor IC dies bonded together. The dicing process typically utilizes a metal blade (e.g., a cutting saw) to mechanically cut through the individual layers of the bonding device structure to separate the individual bonding die structures. However, it has been found that the dicing process can cause mechanical stress to accumulate at the bonding interfaces between the bonding device structures. This can lead to delamination defects between the individual device structures, which may result in poor device reliability and reduced device yield of the bonding die structures.

[0090] The various embodiments disclosed herein relate to bonded grain structures and methods of manufacturing thereof that can provide fewer defects and higher reliability. In various embodiments, a laser grooving process can be configured to "pre-cut" the bonded assembly structure prior to a final dicing process. The laser grooving process can form a plurality of relatively deep grooves in the bonded assembly structure, which can extend beyond the bonding interface between the first and second assembly structures. The individual bonded grain structures can then be separated along the plurality of pre-cut grooves using a final dicing process. Because the cutting is performed along the plurality of deep pre-cut grooves extending through the bonding interface between the first and second assembly structures, the cutting blade may not cut through the bonding interface or may not contact the bonding interface. This can result in reduced mechanical stress, which can reduce the occurrence of delamination defects between the assembly structures, thereby providing improved reliability and increased yield.

[0091] The bonded grain structure manufactured using the aforementioned laser grooving process may include a first grain bonded to a second grain at a bonding interface, and a sidewall having a non-flat wavy surface, wherein the plane of the bonding interface between the first grain and the second grain may intersect the sidewall of the bonded grain structure. In some embodiments, the bonding interface may be exposed along the sidewall having the non-flat wavy surface.

[0092] Figures 1 to 7 A vertical cross-sectional view of an intermediate structure during a process of sequentially manufacturing a bonded grain structure according to various embodiments of the present disclosure is shown. Figure 1 This illustration depicts a portion of a first device structure 100 according to various embodiments of the present disclosure. The first device structure 100 may include a first semiconductor substrate 101 (e.g., a semiconductor wafer), which may include elemental semiconductors (e.g., silicon or germanium) and / or compound semiconductors (e.g., silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide, or combinations thereof). Other semiconductor substrate materials are also within the scope of this disclosure. In some embodiments, the first semiconductor substrate 101 may be a semiconductor-on-insulator (SOI) substrate.

[0093] The first semiconductor substrate 101 may include a first main surface (i.e., the front surface 102) and a second main surface (i.e., the rear surface 103). In some embodiments, the thickness of the first semiconductor substrate 101 between the front surface 102 and the rear surface 103 may be between about 100 (micrometer) μm and about 800 μm, but a first semiconductor substrate 101 with a thicker or thinner thickness may also be used.

[0094] In some embodiments, multiple devices ( Figure 1(Not shown) These devices may be disposed on, above, and / or in, the front surface 102 of the first semiconductor substrate 101. These devices may include, for example, active devices, passive devices, or combinations thereof. In some embodiments, the devices disposed on, above, and / or in, the front surface 102 of the first semiconductor substrate 101 may include a plurality of integrated circuit devices. Integrated circuit devices may include, for example, transistors (e.g., field-effect transistors (FETs)), capacitors, resistors, diodes, photodiodes, fuse elements, or other similar devices. In some embodiments, integrated circuit devices may include gate electrodes, source / drain regions, spacers, and isolation trenches, etc.

[0095] The first device structure 100 may also include a first interconnect structure 105 above the front surface 102 of the first semiconductor substrate 101. The first interconnect structure 105 may include metal features 107 (e.g., metal lines, vias, etc.) formed in the dielectric material 106 (e.g., one or more inter-layer dielectric (ILD) layers and / or inter-metal dielectric (IMD) layers), and the metal features 107 may provide connections for various devices located on, above, and / or in the front surface 102 of the first semiconductor substrate 101 and / or connections between various devices.

[0096] In some embodiments, the first device structure 100 may include one or more first through-substrate vias (TSVs) 114 extending through the first semiconductor substrate 101. The first TSVs 114 may provide electrical connections between devices and / or interconnect structures on the front surface 102 and the rear surface 103 of the first semiconductor substrate 101.

[0097] According to various embodiments of this disclosure, the first device structure 100 may further include a first bonding layer 109 located above the first interconnect structure 105. The first bonding layer 109 may include one or more dielectric material layers 108, and the first bonding layer 109 is composed of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, or a dielectric polymer material. Other suitable dielectric materials are also within the scope of this disclosure. In various embodiments, any suitable deposition process may be used to deposit one or more dielectric material layers 108. In this document, "suitable deposition process" may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), low-pressure CVD, metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, or laser ablation, and includes various combinations thereof. The first bonding layer 109 may have a flat upper surface 122, such as... Figure 1 As shown.

[0098] Please continue reading. Figure 1The first bonding layer 109 may further include a plurality of first metal bonding features 110, 110a. The first metal bonding features 110, 110a may include a plurality of bonding pads 111 and a plurality of bonding vias 113. The bonding pads 111 and bonding vias 113 of the first metal bonding features 110, 110a can be formed by forming a plurality of openings in one or more dielectric material layers 108 of the first bonding layer 109 and depositing metal material in the openings, for example by a damascene or dual damascene process. This process may include, for example, performing one or more etching processes by photolithography patterning masking to form openings in one or more dielectric material layers 108 and depositing suitable metal material in the openings to form bonding pads 111 and / or bonding vias 113. An optional planarization process may be used to remove excess conductive material from above the planar upper surface 122 of the first bonding layer 109. The bonding pads 111 and bonding vias 113 of the first metal bonding features 110, 110a may comprise suitable conductive materials, such as copper (Cu), tungsten (W), and aluminum (Al). The bonding pads 111 and bonding vias 113 of the first metal bonding features 110, 110a may be formed using suitable deposition processes, such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (e.g., electroplating), or combinations thereof.

[0099] The dielectric material layer 108 of the first bonding layer 109 may laterally surround the first metal bonding features 110, 110a. At least some bonding pads 111 of the first metal bonding features 110, 110a may be electrically coupled to a plurality of metal features 107 below the first interconnect structure 105 via bonding vias 113.

[0100] Figure 1A unit area (UA) of a first device structure 100 is illustrated. The unit area UA of the first device structure 100 may be a part of the first device structure 100, and this part may subsequently be separated (i.e., partitioned) from the rest of the first device structure 100 to provide an integrated circuit (IC) die, as further described later. The unit area UA may include a group of integrated circuit devices disposed on, above, and / or in, the front surface 102 of the first semiconductor substrate 101, an interconnect structure 105 disposed above the front surface 102 of the first semiconductor substrate 101, and a portion of the first bonding layer 109. In some embodiments, the unit area UA may lack the devices disposed on, above, and / or in, the front surface 102 of the first semiconductor substrate 101, and may instead be configured to form a non-functional or “virtual” die in a multi-die bonded device structure. For example, a non-functional “virtual” die may be used to achieve in-line process structure consistency and / or routing of electrical signals. The first device structure 100 typically includes multiple unit regions UA, each of which can be separated from the first device structure 100 to form a corresponding grain.

[0101] In some embodiments, at least a portion of the first metal bonding feature 110a of the first bonding layer 109 may be located outside the cell region UA ​​of the first device structure 100, for example, around the periphery of the cell region UA ​​and / or between adjacent cell regions UA of the first device structure 100 (e.g., in a scribe groove of the first device structure 100). Therefore, these bonding features 110a may not be present in any individual IC die produced via a dicing process. However, as discussed in further detail later, the first metal bonding feature 110a can aid the subsequent dicing process by preferentially absorbing laser radiation during a laser grooving process, which can be configured to "pre-cut" individual cell regions UA before performing the final dicing process. The first metal bonding feature 110a located outside the cell region UA ​​of the first device structure 100 may be referred to as a "virtual" first metal bonding feature 110a.

[0102] Figure 2 A vertical cross-sectional view of a portion of a second device structure 200 according to various embodiments of the present disclosure is illustrated. The second device structure 200 may include a second semiconductor substrate 201 (e.g., a semiconductor wafer) having a first main surface (i.e., a front surface 202) and a second main surface (i.e., a rear surface 203). Multiple devices ( Figure 2(Not shown) may be disposed on, above, and / or in, the front surface 202 of the second semiconductor substrate 201. The second device structure 200 may further include a second interconnect structure 205 above the front surface 202 of the second semiconductor substrate 201. The second interconnect structure 205 may include a plurality of metal features 207 (e.g., metal lines, vias, bonding pads, etc.) formed in the dielectric material 206. In some embodiments, the second device structure 200 may further include one or more second through-silicon vias (TSVs) 214 extending through the second semiconductor substrate 201. The second semiconductor substrate 201, the second interconnect structure 205, and the second TSV 214 of the second device structure 200 may be associated with the aforementioned... Figure 1 The first semiconductor substrate 101, first interconnect structure 105, and first TSV 114 of the first device structure 100 are similar or identical. Therefore, for the sake of brevity, repeated discussion of similar elements is omitted. The second device structure 200 may include one or more unit regions UA as described above. In various embodiments, each unit region UA ​​of the second device structure 200 may have the same size and shape as the corresponding unit region UA ​​of the first device structure 100.

[0103] The second device structure 200 may further include a second bonding layer 209, which includes one or more dielectric material layers 108, and a plurality of second metal bonding features 210, 210a (i.e., bonding pads 211 and bonding vias 213) are formed in the one or more dielectric material layers 108. The second bonding layer 209 may be located above the rear surface 203 of the second semiconductor substrate 201. At least some of the bonding pads 211 of the second metal bonding features 210, 210a of the second bonding layer 209 may be electrically coupled to a second TSV 214 extending through the second semiconductor substrate 201.

[0104] In various embodiments, the layout of the second metal bonding features 210, 210a of the second bonding layer 209 may correspond to the layout of the first metal bonding features 110, 110a of the first bonding layer 109. At least a portion of the second metal bonding features 210, 210a may be a “virtual” second metal bonding feature 210a, and the “virtual” second metal bonding feature 210a may be located outside the unit region UA ​​of the second device structure 200.

[0105] Figure 3 A vertical cross-sectional view is shown illustrating a second device structure 200 joined to a first device structure 100 to form a joined device structure 150 according to various embodiments of the present disclosure. Figure 3As shown, the second device structure 200 can be aligned above the first device structure 100, such that the second bonding layer 209 on the second device structure 200 faces the first bonding layer 109 on the first device structure 100. Each unit region UA ​​of the second device structure 200 can be aligned above the corresponding unit region UA ​​of the first device structure 100. Each bonding pad 211 of the second metal features 210, 210a of the second bonding layer 209 can be aligned with the corresponding bonding pad 111 of the first metal features 110, 110a of the first bonding layer 109.

[0106] Please continue reading. Figure 3 In various embodiments, the second bonding layer 209 may be bonded to the first bonding layer 109 via metal-to-metal (MM) and dielectric-to-dielectric (DD) direct bonding techniques to mechanically and electrically couple the second device structure 200 to the first device structure 100. In some embodiments, prior to bonding the second device structure 200 to the first device structure 100, the surfaces of the first bonding layer 109 on the first device structure 100 and / or the second bonding layer 209 on the second device structure 200 may optionally undergo a pretreatment process (e.g., a plasma treatment process) to promote surface activation of the first bonding layer 109 and / or the second bonding layer 209 before bonding the second device structure 200 to the first device structure 100. To perform the bonding process, the second device structure 200 and the first device structure 100 may be disposed together such that the second bonding layer 209 of the second device structure 200 contacts the first bonding layer 109 of the first device structure 100. The second device structure 200 and the first device structure 100 can be aligned such that a plurality of bonding pads 211 of the second metal bonding features 210, 210a of the second bonding layer 209 contact the corresponding plurality of bonding pads 111 of the first metal bonding features 110, 110a of the first bonding layer 109, and the dielectric material of the second bonding layer 209 contacts the dielectric material of the first bonding layer 109. In direct bonding processes (e.g., metal-to-metal (MM) and dielectric-to-dielectric (DD) bonding techniques), contacting the first bonding layer 109 and the second bonding layer 209 with each other can induce a pre-bonding process in which chemical bonds (e.g., hydrogen bridges) can be formed at a flat interface between the dielectric materials of the first bonding layer 109 and the second bonding layer 209. In some embodiments, the pre-bonding process can be performed at room temperature (e.g., ~20°C). In other embodiments, the pre-bonding process can be performed at elevated temperatures. In some embodiments, compressive forces can be applied to the second device structure 200 and the first device structure 100 during the pre-bonding process. In other embodiments, no compressive force may be applied during the pre-bonding process.

[0107] Please continue reading. Figure 3In some embodiments, an annealing process may be performed to bond the bonding pads 111 of the first metal features 110, 110a of the first bonding layer 109 to the bonding pads 211 of the second metal features 210, 210a of the second bonding layer 209. The annealing process may be performed at elevated temperatures, such as 100°C or higher, for example, between about 150°C and about 350°C, but lower and higher temperatures may also be used. In some embodiments, compressive forces may be applied to the second device structure 200 and the first device structure 100 during the annealing process. In other embodiments, no compressive force may be applied during the annealing process.

[0108] After the bonding process, the bonding device structure 150 may include a second device structure 200 that is mechanically and electrically coupled to the first device structure 100 at the bonding interface 120. Figure 3 In one embodiment, the bonding device structure 150 includes a configuration in which the rear surface 203 of the second semiconductor substrate 201 of the second device structure 200 is bonded to the front surface of the first device structure 100 (i.e., "back to front"). However, it should be understood that other embodiments of the bonding device structure 150 may have different configurations, such as a front-to-front configuration or a back-to-back configuration. Furthermore, while this disclosure describes metal-to-metal (MM) and dielectric-to-dielectric (DD) direct bonding processes, it should be understood that other bonding processes (e.g., fusion bonding processes) may be used to bond the first device structure 100 and the second device structure 200.

[0109] Figure 4 This is a vertical cross-sectional view of a coupling device structure 150 including a plurality of grooves 130 formed in the coupling device structure according to various embodiments of the present disclosure. Please refer to... Figure 4 A laser grooving process can be performed to remove multiple portions of the bonding device structure 150 from the periphery of the unit region UA. The laser grooving process may include guiding a high-energy laser beam to multiple specific areas of the bonding device structure 150, causing localized heating and evaporation of the irradiated area. In this way, a structure such as... Figure 4 The multiple local grooves or slots 130 shown.

[0110] In one non-limiting embodiment, the laser grooving process may utilize a UV laser source (e.g., a 355nm laser) and this source is directed onto multiple specific regions of the second device structure 200. The laser may be a pulsed laser having a pulse width between about 110 ns and about 120 ns, a beam diameter of 1 μm or greater, and a power between about 5 W and about 10 W. However, it should be understood that other suitable laser sources and laser operating parameters may also be used.

[0111] In various embodiments, the plurality of grooves 130 formed by the laser grooving process can extend through the entire thickness of the second device structure 200, through the bonding interface 120 between the second device structure 200 and the first device structure 100, and into the interior of the second device structure 200. In other words, the laser grooving process can remove portions of the second interconnect structure 205, the second semiconductor substrate 201, the second bonding layer 209, and the first bonding layer 109, and optionally, can further remove portions of the first interconnect structure 105 and the first semiconductor substrate 101. The bonding interface 120 between the second device structure 200 and the first device structure 100 can be exposed along the sidewalls 131 of the grooves 130. In some embodiments, the maximum width of each groove 130 can be between about 50 μm and 200 μm, but grooves 130 with larger and smaller widths are also within the scope of this disclosure.

[0112] The groove 130 can laterally surround the unit region UA ​​of the bonding device structure 150. The laser grooving process can "pre-cut" the individual unit regions UA before performing the final cutting process across the entire thickness of the bonding device structure 150 to form individual bonded grain structures. Pre-cutting the unit regions UA before the final cutting allows for a cleaner cutting process and reduces sawing defects. Furthermore, by providing the groove 130 extending beyond the bonding interface 120 between the second device structure 200 and the first device structure 100, the final cutting process of the remaining portion of the bonding device structure 150 can reduce mechanical stress, thereby reducing the occurrence of delamination defects between the first device structure 100 and the second device structure 200, thus providing better reliability and improving yield.

[0113] Please continue reading. Figure 3 and Figure 4In embodiments where the bonding device structure 150 includes “virtual” first metal bonding features 110a and / or second metal bonding features 210a located outside the unit region UA, the “virtual” first metal bonding features 110a and / or second metal bonding features 210a can be advantageous for laser grooving processes because the metal material of the first metal bonding features 110a and / or second metal bonding features 210a has a relatively high absorption rate to laser radiation compared to the surrounding material (e.g., dielectric and / or semiconductor material) of the bonding device structure 150. Therefore, the presence of “virtual” first metal bonding features 110a and / or second metal bonding features 210a in the scribed groove of the bonding device structure 150 can help form deep grooves that extend beyond the depth of the bonding interface 120 between the first device structure 100 and the second device structure 200. During the laser grooving process, the “virtual” first metal bonding features 110a and / or second metal bonding features 210a can be burned off. However, residues of the “virtual” bonding features 110a, 210a, such as copper ions or other metal ions, may be present along the sidewall 131 of the tank 130. In some embodiments, the sidewall 131 of the tank 130 may include at least about one part per billion (ppb) of copper and / or other metal ions as measured using energy-dispersive X-ray spectroscopy.

[0114] Figure 5 This is a vertical cross-sectional view of the bonded grain structure 160 according to various embodiments of the present disclosure. It is possible to... Figure 4 The structure shown is cut to obtain the following: Figure 5 The shown assembly structure 150. In various embodiments, the cutting process can be a mechanical cutting process, which uses a cutting tool, such as a diamond or carbide blade, to cut (e.g., saw) the assembly structure 150. Cutting can be performed along the aforementioned pre-cut groove 130, allowing individual unit regions UA to be separated from the assembly structure 150 to provide, for example, Figure 5 The shown is a grain-bonding structure 160. Each grain-bonding structure 160 may include a first (i.e., front) side 221 and a second (i.e., rear) side 222. Figure 5In some embodiments, the front side 221 of the bonding die structure 160 may be defined by the upper surface of the second interconnect structure 205. The rear side 222 of the bonding die structure 160 may be defined by the rear surface 103 of the first semiconductor substrate 101. The bonding die structure 160 may have at least one side surface 133 extending from the rear side 222 of the bonding die structure 160 to the front side 221 of the bonding die structure 160, and at least one sidewall 131 extending from the side surface 133 to the bonding die structure 160. The at least one side surface 133 may be a substantially flat surface extending along a vertical direction (i.e., perpendicular to the front side 221 and the rear side 222 of the bonding die structure 160). The at least one sidewall 131 may be a non-flat wavy surface. Figure 4 In some embodiments, at least one sidewall 131 may have a concave-bent shape in a vertical cross-sectional view. The bonding grain structure 160 may have a shape that tapers inward along at least one sidewall 131, and the lateral width of the bonding grain structure 160 on the front side 221 may be smaller than the lateral width of the bonding grain structure 160 on the rear side 222 and along at least one side surface 133 of the bonding grain structure 160.

[0115] Please continue reading. Figure 5 The bonding die structure 160 may include a first die 140 and a second die 240, which may be mechanically and optionally electrically coupled across a bonding interface 120. The first die 140 and the second die 240 may each include any type of die, such as a logic die, memory die, analog die, RF die, integrated passive device (IPD) die, etc., and various combinations thereof. In other embodiments, one or both of the first die 140 and the second die 240 may be a non-functional or “virtual” die that provides on-line process architecture consistency and / or electrical signal routing. In various embodiments, the bonding interface 120 between the first die 140 and the second die 240 may be exposed along the sidewall 131 of the bonding die structure 160. In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonded grain structure 160 on either side of the bonding interface 120 between the first grain 140 and the second grain. As mentioned above, after the laser grooving process, copper ions and / or other metal ions may be located on the sidewall 131 as evidence of the residue of the “virtual” bonding features 110a, 210a that have been burned off.

[0116] The bonding die structure 160 may be located on the carrier structure 155. The carrier structure 155 may include a suitable substrate (e.g., a semiconductor substrate, an organic substrate, a glass substrate, a ceramic substrate, etc.) configured to support the bonding die structure 160. In various embodiments, the rear side 222 of the bonding die structure 160 may be bonded or adhered to the carrier structure 155 by a suitable bonding method (e.g., the aforementioned direct bonding / welding method) and / or using a suitable adhesive. In a non-limiting embodiment, the bonding die structure 160 may be bonded or adhered to a semiconductor (e.g., silicon) carrier wafer, and the portion of the semiconductor carrier wafer to which the bonding die structure 160 is bonded may be separated using a separate dicing process to provide the bonding die structure 160 on the carrier structure 155, such as... Figure 5 As shown.

[0117] Figure 6 This is a vertical cross-sectional view of a bonding grain structure 160 according to various embodiments of the present disclosure, the bonding grain structure 160 including a plurality of solder balls 225 above a front side 221 of the bonding grain structure 160. Please refer to... Figure 6 Multiple solder balls 225 may be disposed on the front side 221 of the bonding die structure 160. Each solder ball 225 may contact a metal feature 211 (e.g., a bonding pad) of the second interconnect structure 205 of the bonding die structure 160.

[0118] Figure 7 A vertical cross-sectional view of the bonding grain structure 160 on the support structure 157 according to various embodiments of this disclosure is shown. Please refer to... Figure 7 The bonded grain structure 160 can be relative to, for example Figure 6 The bonding die structure 160 shown is reversed (i.e., flipped) such that the front side 221 of the bonding die structure 160 faces downward and the rear side of the carrier structure 155 faces upward. The bonding die structure 160 can be aligned above the support structure 157. The support structure 157 may include, for example, a semiconductor wafer, an interposer, and / or a substrate (e.g., a semiconductor, glass, or organic substrate) configured to support the bonding die structure 160. The bonding die structure 160 can be contacted with the support structure 157 such that solder balls 225 can contact corresponding bonding structures (e.g., bonding pads) on the surface of the support structure 157. The bonding die structure 160 can be bonded to the support structure 157 using a reflow soldering process.

[0119] Figure 8A vertical cross-sectional view of a joining device structure 150 according to another embodiment of the present disclosure is shown. In some embodiments, the laser grooving process on the joining device structure 150 may be a multi-stage process, which may include forming a plurality of first grooves 130a in the joining device structure 150 and then forming a plurality of second grooves in the joining device structure 150. See also... Figure 8 An initial laser grooving process can be performed to form a plurality of first grooves 130a around the periphery of the unit region UA. In some embodiments, the initial laser grooving process may include forming a plurality of first grooves 130a in a scribe groove of the joining device structure 150. The plurality of first grooves 130a may be laterally separated from each other. The initial laser grooving process may include simultaneously (e.g., using two different laser sources) or sequentially directing laser radiation to two or more different locations in the scribe groove. Figure 8 An embodiment is illustrated in which a pair of first grooves 130a are formed in a scribed groove surrounding each unit region UA. However, it should be understood that in various embodiments, more than two first grooves 130a or a single first groove 130a may be formed.

[0120] exist Figure 8 In some embodiments, each first trench 130a extends into the second device structure 200, including into the second interconnect structure 205, and optionally through the second interconnect structure 205 and into the second semiconductor substrate 201. In some embodiments, the first trench 130a may extend through the second semiconductor substrate 201 and into the second bonding layer 209. Figure 8 In one embodiment, the first groove 130a does not extend beyond the interface 120 between the first device structure 100 and the second device structure 200. However, in other embodiments, the first groove 130a may extend beyond the interface 120 between the first device structure 100 and the second device structure 200. Figure 8 In the illustrated embodiment, each first groove 130a may have an equal width and may extend into the engagement structure 150 to an equal depth. However, in other embodiments, the first grooves 130a may have inconsistent width and / or depth dimensions. The first grooves 130a may span or laterally surround the “virtual” engagement features 110a, 210a.

[0121] Figure 9 This is a vertical cross-sectional view of a coupling device structure 150 according to another embodiment of the present disclosure, including a plurality of second grooves 130b formed in the coupling device structure 150. Please refer to... Figure 9An additional laser grooving process can be performed to create a second groove 130b surrounding the periphery of the unit region UA. The additional laser grooving process may include directing laser radiation to a location between adjacent pairs of first grooves 130a. The additional laser grooving process can remove material between pairs of first grooves 130a, allowing the pairs of first grooves 130a to connect with each other. The additional laser grooving process can form a second groove 130b between and connected to the first grooves 130a, wherein the second groove 130b may have a depth greater than the depth of the first grooves 130a. In various embodiments, the second groove 130b may extend through the interface 120 between the second device structure 200 and the first device structure 100 and into the first device structure 100.

[0122] In some embodiments, the additional laser grooving process configured to form the second groove 130b may utilize parameters different from those used during the initial laser grooving process (e.g., different laser spot size, different laser power, etc.). In some embodiments, the width dimension of the second groove 130b may be different from the width dimension of the first groove 130a.

[0123] Please see Figure 9 Each pair of adjacent first grooves 130a and a second groove 130b formed between adjacent first grooves 130a can together form a continuous groove 130 that laterally surrounds each unit region UA ​​of the engagement device structure 150. The engagement interface 120 between the second device structure 200 and the first device structure 100 can be exposed along the sidewall 131 of the continuous groove 130. The sidewall 131 of the continuous groove 130 may further include discontinuous ridge features 135, wherein the second groove 130b intersects with the adjacent first groove 130a.

[0124] Figure 10 This is a vertical cross-sectional view of a bonded grain structure 160 according to another embodiment of this disclosure. The bonded grain structure 160 can be related to the aforementioned... Figure 5 The grain structure shown is similar to 160. Therefore, for the sake of brevity, repeated descriptions of similar elements are omitted. Figure 9 The bonding device structure 150 shown can be subjected to the aforementioned cutting process along the groove 130, so that individual unit regions UA can be separated to provide a bonding grain structure 160. Figure 10 The diagram illustrates the bonding grain structure 160 disposed on the aforementioned carrier structure 155.

[0125] Please see Figure 10The bonding grain structure 160 may have at least one side surface 133 extending from the rear side 222 of the bonding grain structure 160 to the front side 221 of the bonding grain structure 160, and at least one sidewall 131 extending from the side surface 133 to the bonding grain structure 160. The at least one side surface 133 may be a substantially flat surface that can extend along a vertical direction (i.e., perpendicular to the front side 221 and rear side 222 of the bonding grain structure 160). The at least one sidewall 131 may be a non-flat, wavy surface. The bonding interface 120 between the first grain 140 and the second grain 240 of the bonding grain structure 160 may be exposed along at least one sidewall 131. Figure 10 In some embodiments, at least one sidewall 131 may have a discontinuous ridge feature 135. In a vertical cross-sectional view, at least one sidewall 131 may have a concave bend shape between the discontinuous ridge feature 135 and the front side 221 of the bonded grain structure 160, and a concave bend shape between the discontinuous ridge feature 135 of the bonded grain structure 160 and the side surface 133. In a vertical cross-sectional view, the discontinuous ridge feature 135 may resemble a geometric cusp. Figure 10 As shown, in some embodiments, the discontinuous ridge feature 135 may form a locally raised region of the sidewall 131, such that the discontinuous ridge feature 135 may be closer to the plane containing the front side 221 of the bonding grain structure 160 than the surrounding portion of the sidewall 131 located on either side of the discontinuous ridge feature 135. In some embodiments, the magnitude of the inclination of at least one sidewall 131 may be initially reduced by moving from the front side 221 of the bonding grain structure 150 toward the rear side 222 of the bonding grain structure 150. Figure 10 As shown, the slope of at least one sidewall 131 can be reduced to zero between the front side 221 and the discontinuous ridge feature 135, and can be zero at the local minimum point 260 between the front side 221 and the discontinuous ridge feature 135.

[0126] exist Figure 10 In one embodiment, the discontinuous ridge feature 135 is located between the front side 221 of the bonded grain structure 160 and the bonding interface 120 between the first grain 140 and the second grain 240 (i.e., the discontinuous ridge feature is adjacent to the second grain 240). In other embodiments, as described in more detail later, the discontinuous ridge feature 135 may be located between the bonding interface 120 and the side surface 133 of the bonded grain structure 160 (i.e., the discontinuous ridge feature 135 is adjacent to the first grain 140).

[0127] In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonded grain structure 160. In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonded grain structure 160 on either side of the bonding interface 120 between the first grain 140 and the second grain 240.

[0128] In some embodiments, such as Figure 10 The shown grain structure 160 can be flipped and mounted to a suitable support structure 157 via solder balls 225, as described above. Figure 6 and Figure 7 As shown.

[0129] Figure 11 This is a vertical cross-sectional view of a coupling device structure 150 according to another embodiment of the present disclosure, including a plurality of first grooves 130a formed in the coupling device structure 150. Please refer to... Figure 11 An initial laser grooving process can be performed to form a first groove 130a around the periphery of the unit region UA ​​of the joining device structure 150. This can be combined with... Figure 8 The initial laser grooving processes shown are different. Figure 11 An embodiment of the initial laser grooving process forms only a single first trench 130a in the scribe groove of each unit region UA. Each first trench 130a may extend into the second device structure 200, including into the second interconnect structure 205, and optionally through the second interconnect structure 205 and into the second semiconductor substrate 201. In some embodiments, the first trench 130a may extend through the second device structure 200. Figure 11 In one embodiment, the first groove 130a does not extend beyond the interface 120 between the first device structure 100 and the second device structure 200. However, in other embodiments, the first groove 130a may extend beyond the interface 120 between the first device structure 100 and the second device structure 200.

[0130] Figure 12 This is a vertical cross-sectional view of a coupling device structure 150 according to another embodiment of the present disclosure, including a plurality of second grooves 130b formed in the coupling device structure 150. Please refer to... Figure 12 Additional laser grooving processes can be performed to create a second groove 130b surrounding the periphery of the unit region UA. The additional laser grooving process may include directing laser radiation to the location of the first groove 130a to form a second groove 130b extending from the bottom surface of the corresponding first groove 130a. In various embodiments, the second groove 130b may extend from the bottom surface of the first groove 130a through the interface 120 between the second device structure 200 and the first device structure 100 and into the first device structure 100.

[0131] In some embodiments, the additional laser grooving process configured to form the second groove 130b may utilize parameters different from those used during the initial laser grooving process (e.g., different laser spot size, different laser power, etc.). In some embodiments, the width of the second groove 130b may differ from the width of the first groove 130a. In some embodiments, the width of the first groove 130a may be greater than the width of the second groove 130b. Forming a relatively wide first groove 130a prior to forming a relatively narrow second groove 130b may help minimize stress on the joining device structure 150 during the laser grooving process.

[0132] Please see Figure 12 Each first groove 130a and a second groove 130b formed in the bottom surface of the first groove 130a can together form a continuous groove 130 that can laterally surround each unit region UA ​​of the joining device structure. The joining interface 120 between the second device structure 200 and the first device structure 100 can be exposed along the sidewall 131 of the continuous groove 130. The sidewall 131 of the continuous groove 130 may further include discontinuous ridge features 135, wherein the second groove 130b intersects with the first groove 130a.

[0133] Figure 13 This is a vertical cross-sectional view of a bonded grain structure 160 according to another embodiment of this disclosure. The bonded grain structure 160 can be associated with the aforementioned... Figure 5 The grain structure shown is similar to 160. Therefore, for the sake of brevity, repeated descriptions of similar elements are omitted. Figure 13 The shown bonded grain structure 150 can be cut along the groove 130 as described above, so that individual unit regions UA can be separated to provide the bonded grain structure 160. Figure 13 The diagram illustrates the bonding grain structure 160 disposed on the aforementioned carrier structure 155.

[0134] Please see Figure 13 The bonding grain structure 160 may have at least one side surface 133 extending from the rear side 222 of the bonding grain structure 160 to the front side 221 of the bonding grain structure 160, and at least one sidewall 131 extending from the side surface 133 to the front side 221 of the bonding grain structure 160. The at least one side surface 133 may be a substantially flat surface that extends along a vertical direction (i.e., perpendicular to the front side 221 and rear side 222 of the bonding grain structure 160). The at least one sidewall 131 may be a non-flat, wavy surface. The bonding interface 120 between the first grain 140 and the second grain 240 of the bonding grain structure 160 may be exposed along at least one sidewall 131. Figure 13In some embodiments, at least one sidewall 131 may have a discontinuous ridge feature 135. In a vertical cross-sectional view, at least one sidewall 131 may have a concave bend shape between the discontinuous ridge feature 135 and the front side 221 of the bonding grain structure 150, and a concave bend shape between the discontinuous ridge feature 135 of the bonding grain structure 160 and the side surface 133. Therefore, in a vertical side view, the discontinuous ridge feature 135 may resemble a geometric cusp. Figure 13 In one embodiment, the discontinuous ridge feature 135 is located between the front side 221 of the bonded grain structure 160 and the bonding interface 120 between the first grain 140 and the second grain 240 (i.e., the discontinuous ridge feature is adjacent to the second grain 240). In other embodiments, the discontinuous ridge feature 135 may be located between the bonding interface 120 of the bonded grain structure 160 and the side surface 133 (i.e., the discontinuous ridge feature is adjacent to the first grain 140).

[0135] In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonded grain structure 160. In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonded grain structure 160 on either side of the bonding interface 120 between the first grain 140 and the second grain.

[0136] In some embodiments, such as Figure 13 The shown grain structure 160 can be flipped and mounted to a suitable support structure 157 via solder balls 225, as described above. Figure 6 and Figure 7 As shown.

[0137] Figure 14 This is a vertical cross-sectional view of a coupling device structure 150 according to another embodiment of the present disclosure, including a plurality of first grooves 130a formed in the coupling device structure 150. Please refer to... Figure 14 An initial laser grooving process can be performed to form a first groove 130a around the periphery of the unit region UA ​​of the joining device structure 150, as described above. Figure 11 Similar to the formation of the first groove 130a described above. It can be compared with... Figure 11 The initial laser grooving processes shown are different. Figure 14 The first groove 130a can extend through the second device structure 200 and the joint interface 120 between the first device structure 100 and the second device structure 200 and into the first device structure 100.

[0138] Figure 15 This is a vertical cross-sectional view of a coupling device structure 150 according to another embodiment of the present disclosure, including a plurality of second grooves 130b formed in the coupling device structure 150. Please refer to... Figure 15Additional laser grooving processes can be performed to create a second groove 130b surrounding the periphery of the unit region UA. The additional laser grooving process may include directing laser radiation to the location of the first groove 130a to form a second groove 130b extending from the bottom surface of the corresponding first groove 130a. In various embodiments, the second groove 130b may extend further into the first device structure 100 than the first groove 130a.

[0139] In some embodiments, the additional laser grooving process configured to form the second groove 130b may utilize parameters different from those used during the initial laser grooving process (e.g., different laser spot size, different laser power, etc.). In some embodiments, the width of the second groove 130b may differ from the width of the first groove 130a. In some embodiments, the width of the first groove 130a may be greater than the width of the second groove 130b. Forming a relatively wide first groove 130a before forming a relatively narrow second groove 130b can help minimize stress on the joining device structure 150 during the laser grooving process.

[0140] Figure 16 This is a vertical cross-sectional view of a bonded grain structure 160 according to another embodiment of this disclosure. The bonded grain structure 160 can be related to the aforementioned... Figure 5 The grain structure shown is similar to 160. Therefore, for the sake of brevity, repeated descriptions of similar elements are omitted. Figure 13 The bonding device structure 150 shown can be subjected to the aforementioned cutting process along multiple grooves 130, so that individual unit regions UA can be separated to provide a bonding grain structure 160. Figure 16 The diagram illustrates the bonding grain structure 160 disposed on the aforementioned carrier structure 155.

[0141] like Figure 16 As shown, the bonding grain structure 160 may have at least one side surface 133 extending from the rear side 222 of the bonding grain structure 160 to the front side 221 of the bonding grain structure 160, and at least one sidewall 131 extending from the side surface 133 to the front side 221 of the bonding grain structure 160. The at least one side surface 133 may be a substantially flat surface that extends along a vertical direction (i.e., perpendicular to the front side 221 and rear side 222 of the bonding grain structure 160). The at least one sidewall 131 may be a non-flat, wavy surface. The bonding interface 120 between the first grain 140 and the second grain 240 of the bonding grain structure 160 may be exposed along at least one sidewall 131. Figure 16In some embodiments, at least one sidewall 131 may have a discontinuous ridge feature 135. In a vertical cross-sectional view, at least one sidewall 131 may have a concave bend shape between the discontinuous ridge feature 135 and the front side 221 of the bonding grain structure 150, and a concave bend shape between the discontinuous ridge feature 135 and the side surface 133 of the bonding grain structure 160. Therefore, in a vertical side view, the discontinuous ridge feature 135 may resemble a geometric cusp. Figure 16 In one embodiment, the discontinuous ridge feature 135 is located between the rear side 222 of the bonded grain structure 160 and the bonding interface 120 between the first grain 140 and the second grain 240 (i.e., the discontinuous ridge feature 135 is adjacent to the first grain 140).

[0142] In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonded grain structure 160. In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonded grain structure 160 on either side of the bonding interface 120 between the first grain 140 and the second grain.

[0143] In some embodiments, such as Figure 16 The shown grain structure 160 can be flipped and mounted to a suitable support structure 157 via solder balls 225, as described above. Figure 6 and Figure 7 As shown.

[0144] Figure 17 A vertical cross-sectional view of a joining device structure 150 according to another embodiment of the present disclosure is shown. Figure 17 The joint structure 150 and Figure 3 The joint device structure is similar to 150, and Figure 17 The joining device structure 150 includes a first device structure 100 joined to the second device structure 200 via corresponding first joining layer 109 and second joining layer 209. Therefore, for the sake of brevity, repeated descriptions of similar features are omitted. The joining device structure 150 and... Figure 3 The engagement device structure 150 is different, and the difference is that the engagement device structure 150 includes a third device structure 300 that is engaged to the second device structure 200.

[0145] Please see Figure 17 The third device structure 300 may be similar to the first device structure 100 and the second device structure 200. The third device structure 300 may include a third semiconductor substrate 301 (i.e., a semiconductor wafer) having a first main surface (i.e., a front surface 302) and a second main surface (i.e., a rear surface 303), and a plurality of devices (not shown) disposed on, above, and / or in, the front surface 302 of the third semiconductor substrate 301. Figure 17The third device structure 300 includes a third interconnect structure 305 located above the front surface 302 of the third semiconductor substrate 301, wherein the third interconnect structure 305 may include metal features 307 (e.g., metal lines, vias, pads, etc.) formed in the dielectric material 306. In some embodiments, the third device structure 300 may further include one or more second through-silicon vias (TSVs) 314 extending through the third semiconductor substrate 301. The third device structure 300 may include one or more cell regions UA as described above. In various embodiments, each cell region UA ​​of the third device structure 300 may have the same size and shape as the corresponding cell regions UA of the first device structure 100 and the second device structure 200.

[0146] In various embodiments, a third bonding layer 309 comprising one or more dielectric material layers 308 may be formed over the second interconnect structure 205 on the second device structure 200. The third bonding layer 309 has third metal bonding features 310, 310a (i.e., bonding pads 311 and bonding vias 313) formed in the one or more dielectric material layers 308 of the third bonding layer 309. At least some of the bonding pads 311 of the third metal bonding features 310, 310a of the third bonding layer 309 may be electrically coupled to a plurality of metal features 207 of the second interconnect structure 205.

[0147] A fourth bonding layer 409 comprising one or more dielectric material layers 408 is formed above the rear surface 303 of the third semiconductor substrate 301 of the third device structure 300. The fourth bonding layer 409 has fourth metal bonding features 410, 410a (i.e., bonding pads 411 and bonding vias 413) formed in the one or more dielectric material layers 408 of the fourth bonding layer 409. At least some of the bonding pads 411 of the fourth metal bonding features 410, 410a of the fourth bonding layer 409 can be electrically coupled to a third TSV 314 extending through the third semiconductor substrate 301.

[0148] In various embodiments, the layout of the third metal bonding features 310, 310a of the third bonding layer 309 may correspond to the layout of the fourth metal bonding features 410, 410a of the fourth bonding layer 409. At least a portion of the third metal bonding features 310, 310a and / or the fourth metal bonding features 410, 410a may be “virtual” third metal bonding features 310, 310a and / or the fourth metal bonding features 410, 410a, which may be located outside the unit regions UA of the second device structure 200 and the third device structure 300.

[0149] Please continue reading. Figure 17The third bonding layer 309 on the second device structure 200 can be bonded to the fourth bonding layer 409 on the third device structure 300 using bonding processes (e.g., metal-to-metal (MM) and dielectric-to-dielectric (DD) direct bonding processes as described above). After the bonding process, one side of the second device structure 200 can be mechanically and electrically coupled to the first device structure 100 at the first bonding interface 120, and the opposite side of the second device structure 200 can be mechanically and electrically coupled to the third device structure 300 at the second bonding interface 220.

[0150] Figure 18 This is a vertical cross-sectional view of a coupling device structure 150 including a plurality of grooves 130 formed in the coupling device structure 150 according to various embodiments of the present disclosure. Please refer to... Figure 18 The laser grooving process described above can be performed to form a plurality of grooves 130 around the periphery of the unit region UA. In various embodiments, the plurality of grooves 130 may extend through the third device structure 300 and the second mating interface 220 and into the second device structure 200. Figure 18 In some embodiments, the plurality of grooves 130 do not extend into or beyond the first mating interface 120. In some embodiments, the plurality of grooves 130 can be formed by a single laser irradiation of a plurality of scribed grooves surrounding a unit region UA ​​of the mating device structure 150. Alternatively, the laser grooving process can be a multi-stage process, including multiple laser irradiations to form a plurality of grooves in each scribed groove, as described above. Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 14 and Figure 15 As stated above.

[0151] Figure 19 This is a vertical cross-sectional view of the bonded grain structure 160 according to another embodiment of this disclosure. In various embodiments, Figure 19 Yes, the bonded grain structure 160 can be cut along the aforementioned cutting process along multiple grooves 130, so that individual unit regions UA can be separated to provide the bonded grain structure 160. Figure 19 The diagram illustrates the bonding grain structure 160 disposed on the aforementioned carrier structure 155.

[0152] Please see Figure 19The die-bonding structure 160 may include a first die 140, a second die 240, and a third die 340. The first die 140 and the second die 240 may be mechanically coupled across a first bonding interface 120 and optionally electrically coupled, and the second die 240 and the third die 340 may be mechanically coupled across a second bonding interface 220 and optionally electrically coupled. The first die 140, the second die 240, and the third die 340 may each include any type of die, including functional dies (e.g., logic dies, memory dies, analog dies, RF dies, integrated passive device (IPD) dies, etc., including various combinations thereof). In other embodiments, one or more of the first die 140, the second die 240, and the third die 340 may be non-functional or “virtual” dies providing consistency in the through-hole process structure and / or routing for electrical signals.

[0153] The bonding die structure 160 may include a front side 221 defined by the upper surface of the third interconnect structure 305 and a rear side 222 defined by the rear side surface 103 of the first semiconductor substrate 101. The bonding die structure 160 may have at least one side surface 133 extending from the rear side 222 of the bonding die structure 160 to the front side 221 of the bonding die structure 160, and at least one sidewall 131 extending from the side surface 133 of the bonding die structure 160 to the front side 221. The at least one side surface 133 may be a substantially flat surface that extends along a vertical direction (i.e., perpendicular to the front side 221 and rear side 222 of the bonding die structure 160). The at least one sidewall 131 may be a non-flat, wavy surface. Figure 19 In some embodiments, at least one sidewall 131 may have a concave curved shape in a vertical cross-sectional view. In embodiments utilizing a multi-stage laser grooving process, at least one sidewall 131 of the bonded grain structure 160 may include, for example... Figure 10 , Figure 13 and Figure 16 The discontinuous ridge feature 135 is shown. The bonding grain structure 160 may have a shape that tapers inward along at least one sidewall 131, such that the lateral width of the bonding grain structure 160 on the front surface 221 may be smaller than the lateral width of the bonding grain structure 160 on the rear surface 222 and along at least one side surface 133 of the bonding grain structure 160.

[0154] In various embodiments, the second bonding interface 220 between the third grain 340 and the second grain 240 may be exposed along the sidewall 131 of the bonding grain structure 160. Figure 19In some embodiments, the first bonding interface 120 between the second grain 240 and the first grain 140 may be exposed along the side surface 133 of the bonding grain structure 160. In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonding grain structure 160. In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonding grain structure 160 on either side of the second bonding interface 220 between the third grain 340 and the second grain 340.

[0155] In some embodiments, such as Figure 19 The shown grain structure 160 is flipped and mounted to a suitable support structure 157 via solder balls 225, as described above. Figure 6 and Figure 7 As shown.

[0156] Figure 20 This is a vertical cross-sectional view of a coupling device structure 150 including a plurality of grooves 130 formed in the coupling device structure 150 according to another embodiment of the present disclosure. Figure 20 The coupling device structure 150 can be coupled with, for example, Figure 17 and Figure 18 The connecting device structure shown is similar to 150. Therefore, for the sake of brevity, repeated descriptions of similar features have been omitted. Figure 20 The coupling device structure 150 can be coupled with Figure 17 and Figure 18 The joining device structure 150 differs from the first device structure 100 in that the plurality of grooves 130 can extend through the third device structure 300 and the second device structure 200 and enter the first device structure 100. The second joining interface 220 between the third device structure 300 and the second device structure 200 and the first joining interface 120 between the second device structure 200 and the first device structure 100 can both be exposed along the sidewalls 131 of the plurality of grooves 130. In some embodiments, the plurality of grooves 130 can be formed using a single laser irradiation of a scribe groove surrounding a unit region UA ​​of the joining device structure 150. Alternatively, the laser grooving process can be a multi-stage process, including multiple laser irradiations to form a plurality of grooves in each scribe groove, as described above. Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 14 and Figure 15 As shown.

[0157] Figure 21 This is a vertical cross-sectional view of a bonding grain structure 160 according to another embodiment of this disclosure. In various embodiments, the bonding device structure 160 can perform the aforementioned cutting process along a plurality of grooves 130, allowing individual unit regions UA to be separated to provide, for example... Figure 21 The shown is a bonded grain structure 160. Figure 21 The diagram illustrates the bonding grain structure 160 disposed on the aforementioned carrier structure 155.

[0158] Please continue reading. Figure 21 The bonding grain structure 160 may have at least one side surface 133 extending from the rear side 222 of the bonding grain structure 160 to the front side 221 of the bonding grain structure 160, and at least one sidewall 131 extending from the side surface 133 to the front side 221 of the bonding grain structure 160. The at least one side surface 133 may be a substantially flat surface that extends along a vertical direction (i.e., perpendicular to the front side 221 and rear side 222 of the bonding grain structure 160). The at least one sidewall 131 may be a non-flat, wavy surface. Figure 21 In some embodiments, at least one sidewall 131 may have a concave curved shape in a vertical cross-sectional view. In embodiments utilizing a multi-stage laser grooving process, at least one sidewall 131 of the bonded grain structure 160 may include, for example... Figure 10 , Figure 13 and Figure 16 The discontinuous ridge feature shown is 135.

[0159] In various embodiments, the second bonding interface 220 between the third grain 340 and the second grain 240, and the first bonding interface 120 between the second grain 240 and the first grain 140, may be exposed along the sidewall 131 of the third grain 340. In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewall 131 of the bonding grain structure 160. In some embodiments, at least about 1 ppb of copper ions and / or other metal ions may be present on the sidewalls 131 on both sides of the second bonding interface 220 and on both sides of the first bonding interface 120.

[0160] In some embodiments, such as Figure 21 The shown grain structure 160 is flipped and mounted to a suitable support structure 157 via solder balls 225, as described above. Figure 6 and Figure 7 As shown.

[0161] Figure 22 The diagram illustrates a vertical cross-sectional view of a bonding device structure 160 according to an embodiment of the present disclosure. The bonding device structure 160 includes a bonding grain structure 160 disposed on a carrier structure 155 and laterally surrounded by a gap-filling dielectric material 501. Please refer to... Figure 22 A bonding grain structure 160, comprising a first grain 140 bonded to the second grain 240 via a bonding interface 120, can be provided on the carrier structure 155. The bonding grain structure 160 and the carrier structure 155 can be similar to either of the aforementioned bonding grain structure 160 and carrier structure 155. Figure 22 In the embodiments shown, the bonding grain structure 160 has a flat side surface extending vertically between the front side 221 and the rear side 222 of the bonding grain structure 160. However, it should be understood that the side surface of the bonding grain structure 160 may have the same characteristics as described above. Figure 5 , Figure 10 , Figure 13 , Figure 16 , Figure 19 and / or Figure 21 Similar shape to any embodiment. In some embodiments, a plurality of bonding die structures 160 may be disposed on a carrier structure 155, which may be, for example, a semiconductor wafer. The bonding die structures 160 may be laterally spaced from each other.

[0162] Interval-filling dielectric material 501 can be deposited on the carrier structure 155, including within the gaps between adjacent bonding grain structures 160. Interval-filling dielectric material 501 may include suitable dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, low-k dielectric materials, and extremely low-k (ELK) dielectric materials, undoped silicon glass (USG), fluorosilicate glass (FSG), phosphor-silicate glass (PSG), etc., including combinations thereof. Other suitable dielectric materials disposed in interval-filling dielectric material 501 are also within the scope of this disclosure. Suitable deposition processes can be used to deposit the gap-filling dielectric layer 501, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), low-pressure CVD, metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), sputtering, or laser ablation. In some embodiments, the gap-filling dielectric material 501 can be deposited in the gap between the bonded grain structure 150 and the bonded grain structure 160, and a planarization process (e.g., chemical mechanical planarization (CMP)) can be configured to remove excess gap-filling dielectric material 501 from the front surface 221 of the bonded grain structure 160.

[0163] Figure 23 This is a vertical cross-sectional view of a bonding device structure including a plurality of grooves 130 formed in a gap-filling dielectric material 501, according to various embodiments of the present disclosure. Please refer to... Figure 23A laser grooving process can be performed to remove multiple portions of the gap-filling dielectric material 501, thereby forming a plurality of grooves 130 in the gap-filling dielectric material 501 around the periphery of each bonded grain structure 160. The plurality of grooves 130 can be laterally offset from multiple peripheral edges of the bonded grain structure 160. In various embodiments, the plurality of grooves 130 can extend to a depth below the plane containing the bonding interface 120 between the first grain 140 and the second grain 240.

[0164] In some embodiments, a single laser irradiation of the gap-filling dielectric material 501 surrounding the bonding grain structure 160 can be used to form a plurality of trenches 130. Alternatively, the laser grooving process can be a multi-stage process, including multiple laser irradiations to form a plurality of trenches surrounding each bonding grain structure 160, as described above. Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 14 and Figure 15 As shown.

[0165] The bonding die structure 160 may include a front side 221 defined by the upper surface of the second interconnect structure 205 and the upper surface of the gap-filling dielectric material 501, and a rear side 222 defined by the back side 103 of the first semiconductor substrate 101 and the bottom surface of the gap-filling dielectric material 501. The bonding die structure 160 may have at least one side surface 133 extending from the rear side 222 of the bonding die structure 160 to the front side 221 of the bonding die structure 160, and at least one sidewall 131 extending from the side surface 133 of the bonding die structure 160 to the front side 221. The at least one side surface 133 may be a substantially flat surface that can extend along a vertical direction (i.e., perpendicular to the front side 221 and the rear side 222 of the bonding die structure 160). In some embodiments, the at least one side surface 133 may be continuous with a corresponding side surface of the carrier structure 155. The at least one sidewall 131 may be a non-flat wavy surface. Figure 23 In some embodiments, at least one sidewall 131 may have a concave curved shape in a vertical cross-sectional view. In embodiments utilizing a multi-stage laser grooving process, at least one sidewall 131 of the bonded grain structure 160 may include, for example... Figure 10 , Figure 13 and Figure 16 The discontinuous ridge feature 135 is shown. In various embodiments, at least one side surface 133 and at least one sidewall 131 of the bonded grain structures 150, 160 can be formed by filling the gaps between the first grain 140 and the second grain 240 laterally with dielectric material 501. In various embodiments, the plane comprising the bonding interface 120 between the first grain 140 and the second grain 240 may intersect at least one sidewall 131 of the bonded grain structures 150, 160.

[0166] In some embodiments, Figure 24 The bonding grain structure 160 can be inverted and mounted to a suitable support structure 157 via solder balls 225, as described above. Figure 6 and Figure 7 As shown.

[0167] Figure 25 A flowchart illustrating a method for manufacturing bonded grain structures 150, 160 according to an embodiment of this disclosure is provided. Please refer to [link / reference]. Figure 4 , Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 14 , Figure 15 , Figure 18 , Figure 20 , Figure 23 and Figure 25 In step 601 of method 600, a laser grooving process may be performed to form a groove 130 in surface 221 of semiconductor structures 150, 160, and includes bonding the first device structure 100 to the second device structure 200 at a bonding interface 120, wherein the groove 130 extends from surface 221 to a depth beyond a plane including the bonding interface 120. See also... Figure 5 , Figure 10 , Figure 13 , Figure 16 , Figure 19 , Figure 21 , Figure 24 and Figure 25 In step 603 of method 600, a dicing process may be performed along trench 130 to pass through semiconductor structure 150 to provide a bonded grain structure 150, 160 including a first grain 140 bonded to a second grain 240.

[0168] Referring to all the accompanying drawings and various embodiments disclosed herein, the bonding die structures 150 and 160 include a first die 140 comprising a first semiconductor substrate 101 and a second die 240 comprising a second semiconductor substrate 201, wherein the first die 140 is bonded to the second die 240 at a bonding interface 120. The bonding die structures 150 and 160 include a sidewall 131 having a non-flat, wavy surface and a plane comprising the bonding interface 120 and intersecting with the sidewall 131 of the bonding die structure 160.

[0169] In another embodiment, the bonded grain structures 150, 160 include a first side 221 and a second side 222, a flat side surface 133 extending from the second side 222 to the first side 221, and a sidewall 131 having a non-flat wavy surface and extending between the flat side surface 133 and the first side 221 of the bonded grain structures 150, 160.

[0170] In another embodiment, the bonding grain structures 150, 160 include an inwardly tapering shape along the sidewall 131, such that the lateral width of the bonding grain structures 150, 160 on the first side 221 is smaller than the lateral width along the side surface 133 of the bonding grain structures 150, 160 and located on the second side 222 of the bonding grain structures 150, 160.

[0171] In another embodiment, in a vertical cross-sectional view, the sidewall 131 has a concave-bend shape between the side surface 133 of the bonded grain structures 150, 160 and the first side 221.

[0172] In another embodiment, the sidewall 131 has a discontinuous ridge feature 135, and in a vertical cross-sectional view, the sidewall 131 has a concave bending shape between the discontinuous ridge feature 135 and the first side 221 of the bonded grain structures 150, 160, and a concave bending shape between the discontinuous ridge feature 135 of the bonded grain structures 150, 160 and the side surface 133.

[0173] In another embodiment, the discontinuous ridge feature 135 is located between the plane including the bonding interface 120 and the first side 221 of the bonding grain structure 150, 160.

[0174] In another embodiment, the discontinuous ridge feature 135 is located between the plane including the bonding interface 120 and the side surface 133 of the bonding grain structures 150, 160.

[0175] In another embodiment, the bonding grain structures 150, 160 further include a third grain 340, which includes a third semiconductor substrate 301, wherein the third grain 340 is bonded to the second grain 240 via a second bonding interface.

[0176] In another embodiment, the plane containing the second bonding interface 220 intersects with the sidewall 131 of the bonding grain structures 150, 160.

[0177] In another embodiment, the bonding grain structures 150, 160 further include a gap-filling dielectric material 501 that laterally surrounds the first grain 140 and the second grain 240, wherein the gap-filling dielectric material 501 forms the sidewalls 131, side surfaces 133, a portion of the first side 221, and a portion of the second side 222 of the bonding grain structures 150, 160.

[0178] Another embodiment relates to a bonding die structure 150, 160, which includes a first die 140 comprising a first semiconductor substrate 101 and a second die 240 comprising a second semiconductor substrate 201, wherein the first die 140 is bonded to the second die 240 at a bonding interface 120, the bonding die structure 150, 160 includes a sidewall 131 having a non-flat wavy surface, and the bonding interface 120 located between the first die 140 and the second die 240 is exposed along the sidewall 131 of the bonding die structure 150, 160.

[0179] In one embodiment, at least 1 ppb of metal ions are present on the sidewalls 131 of the bonded grain structures 150, 160.

[0180] In another embodiment, at least 1 ppb of copper ions are present on the sidewall 131 of the bonding grain structures 150, 160 on either side of the bonding interface 120.

[0181] In another embodiment, in a vertical cross-sectional view, the sidewall 131 includes a discontinuous ridge feature 135 with a geometric cusp shape.

[0182] Another embodiment relates to a method of manufacturing bonded grain structures 150, 160, the method comprising performing a laser grooving process to form a groove 130 in a surface 221 of the semiconductor structures 150, 160, and including bonding a first device structure 100 to a second device structure 200 at a bonding interface 120, wherein the groove 130 extends from the surface 221 to a depth beyond a plane including the bonding interface 120; and performing a dicing process along the groove 130 through the semiconductor structures 150, 160 to provide bonded grain structures 150, 160 including a first grain 140 bonded to a second grain 240.

[0183] In one embodiment, the method includes forming a first bonding layer 109, the first bonding layer 109 including a plurality of first metal bonding features 110, 110a formed in a dielectric material layer 108 on a first device structure 100; forming a second bonding layer 209, the second bonding layer 209 including a plurality of second metal bonding features 210, 210a formed in a dielectric material 208 on a second device structure 200; and bonding the first bonding layer 109 to the second bonding layer 209, wherein a bonding interface 120 between the first bonding layer 109 and the second bonding layer 209 bonds the first device structure 100 to the second device structure 200, wherein a trench 130 is formed as passing through either a virtual first metal bonding feature 110a or a virtual second metal bonding feature 210a in a scribe trench located in semiconductor structures 150, 160.

[0184] In another embodiment, forming a trench 130 in the semiconductor structure 150 includes forming a first trench 130a in the semiconductor structures 150 and 160 and subsequently forming a second trench 130b that is continuous with the first trench 130a.

[0185] In another embodiment, forming a trench 130 in the semiconductor structures 150, 160 includes forming a pair of first trenches 130a laterally spaced from each other in the surface 221 of the semiconductor structures 150, 160 and a second trench 130b formed between the pair of first trenches 130a.

[0186] In another embodiment, forming a trench 130 in the semiconductor structures 150, 160 includes forming a first trench 130a in the surface 221 of the semiconductor structures 150, 160, wherein the first trench 130a does not extend to the plane containing the bonding interface 120, and a second trench 130b is formed to extend through the bottom surface of the first trench 130a to beyond the plane containing the bonding interface.

[0187] In another embodiment, forming a trench 130 in the semiconductor structures 150, 160 includes forming a first trench 130a at a depth in the surface 221 of the semiconductor structures 150, 160 extending beyond the plane containing the bonding interface 120, and forming a second trench 130b through the bottom surface of the semiconductor structures 150, 160.

[0188] Further embodiments disclosed herein provide a bonded grain structure. The bonded grain structure includes a first grain comprising a first semiconductor substrate and a second grain comprising a second semiconductor substrate, wherein the first grain is bonded to the second grain at a bonding interface. The bonded grain structure has at least one sidewall, a front side abutting one end of the at least one sidewall, at least one side surface abutting the other end of the at least one sidewall, and a rear side abutting the at least one side surface. The bonded grain structure has a shape that tapers inward along at least one sidewall, with the lateral width of the front side being smaller than the lateral width of the rear side.

[0189] In another embodiment, the sidewall has a discontinuous ridge feature. In a vertical cross-sectional view, the sidewall has a concave bend shape between the discontinuous ridge feature and the front side of the bonded grain structure, and a concave bend shape between the discontinuous ridge feature of the bonded grain structure and the side surface 133.

[0190] In another embodiment, the bonding grain structure further includes a third grain comprising a third semiconductor substrate, and the third grain is bonded to the second grain via a second bonding interface.

[0191] In another embodiment, the plane containing the second bonding interface intersects with the sidewall of the grain structure.

[0192] The various embodiments disclosed herein can provide bonded grain structures and methods for forming them, offering reduced defects and higher reliability. A laser grooving process can be configured to "pre-cut" the bonded assembly structure prior to a final dicing process. The laser grooving process can form relatively deep grooves in the bonded assembly structure that extend beyond the bonding interface between the first and second assembly structures. A final dicing process along the pre-cut grooves can be configured to separate individual bonded grain structures. Because the cutting is performed along deep pre-cut grooves extending through the bonding interface between the stacked assembly structures, the cutting blade may not cut through the bonding interface or may not contact the interface. This reduces mechanical stress, thereby reducing delamination defects between the assembly structures, thus providing better reliability and improved yield.

[0193] This disclosure outlines various embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A grain-bonding structure, characterized in that, include: A first die, comprising a first semiconductor substrate; as well as A second grain includes a second semiconductor substrate, wherein the first grain is bonded to the second grain at a first bonding interface, and the bonded grain structure includes a sidewall having a non-flat wavy surface and a plane including the first bonding interface and intersecting the sidewall of the bonded grain structure.

2. The grain structure as described in claim 1, characterized in that, The bonded grain structure includes a first side and a second side, a flat side surface extending from the second side to the first side, and a sidewall having the non-flat wavy surface and extending between the flat side surface and the first side of the bonded grain structure.

3. The grain structure as described in claim 2, characterized in that, The bonded grain structure includes an inwardly tapering shape along the sidewall, such that a lateral width of the bonded grain structure on the first side is smaller than a lateral width along the side surface of the bonded grain structure and located on the second side of the bonded grain structure.

4. The grain structure as described in claim 2, characterized in that, Further includes: A gap-filled dielectric material is laterally surrounding the first grain and the second grain, wherein the gap-filled dielectric material forms the sidewall, the side surface, a portion of the first side, and a portion of the second side of the bonded grain structure.

5. A grain-bonding structure, characterized in that, include: A first die, comprising a first semiconductor substrate; and A second die includes a second semiconductor substrate, wherein the first die is bonded to the second die at a bonding interface, the bonding die structure includes a sidewall having a non-flat wavy surface, and the bonding interface located between the first die and the second die is exposed along the sidewall of the bonding die structure.

6. The grain structure as described in claim 5, characterized in that, In the vertical cross-sectional view, the sidewall includes a discontinuous ridge feature of a shape with a geometric apex.

7. A grain-bonding structure, characterized in that, include: A first die, comprising a first semiconductor substrate; and A second die, comprising a second semiconductor substrate, wherein the first die is bonded to the second die at a first bonding interface. The bonded grain structure has at least one sidewall, a front side adjacent to one end of the at least one sidewall, at least one side surface adjacent to the other end of the at least one sidewall, and a rear side adjacent to the at least one side surface. The bonded grain structure has a shape that tapers inward along at least one sidewall, and the lateral width of the front side is smaller than the lateral width of the rear side.

8. The grain structure as described in claim 7, characterized in that, The sidewall has a discontinuous ridge feature, and In the vertical cross-sectional view, the sidewall has a concave curved shape between the discontinuous ridge feature and the front side of the bonded grain structure, and a concave curved shape between the discontinuous ridge feature of the bonded grain structure and the side surface.

9. The grain structure as described in claim 7, characterized in that, Further includes: A third die, comprising a third semiconductor substrate, wherein the third die is bonded to the second die via a second bonding interface.

10. The grain structure as described in claim 9, characterized in that, A plane containing the second bonding interface intersects the sidewall of the bonding grain structure.

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