A half-bridge circuit package structure

Abstract

The utility model relates to a kind of half-bridge circuit package structure, including package substrate, half-bridge semiconductor circuit structure and package shell;Wherein, the half-bridge semiconductor circuit structure includes upper bridge circuit and lower bridge circuit in series on the package substrate, and the upper bridge circuit and lower bridge circuit each are provided with a group of chip, and share an electrode D / S.The utility model has the beneficial effects that: compared with single tube with same chip performance, volume is reduced by 25%, cost is reduced by more than 20%, can withstand power in unit volume is big, that is, power density is greater;It also has the advantages of small high-frequency switching loss of silicon carbide, high-voltage resistance, high-temperature resistance, low power consumption, etc., paving the way for large-scale application of medium and high power silicon carbide;And, the package structure of the product is also used for the packaging of next-generation semiconductor (fourth generation) gallium oxide and diamond chip, and has broad market prospects.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging, specifically to a half-bridge circuit packaging structure. Background Technology

[0002] In practical circuit applications, the full-bridge structure is a mature and stable high-power inverter circuit, characterized by high efficiency, high reliability, and flexibility. Currently, high-power silicon carbide MOSFETs are widely packaged in discrete forms, such as the SOT-227 package, a common packaging form for third-generation silicon carbide semiconductor devices. Its structure includes a metal substrate, insulating layer, chip soldering area, and external terminals. Although this package has certain heat dissipation capabilities and electrical performance, it still has many problems in high-power applications. Its internal structure is complex, and the actual manufacturing process is also very complex, resulting in packaging costs that are even higher than the price of the chip itself. For example, if a single Vds>1200V silicon carbide chip costs 30 yuan / pcs, the packaging cost is approximately 40 yuan / pcs. Such a high packaging price hinders the speed and progress of silicon carbide MOSFETs replacing traditional IGBT devices on a large scale. To solve the problem of excessively high costs for four individual transistors (Q1, Q2, Q3, and Q4), the applicant packages Q1 and Q2 into a single unit, generally referred to as a half-bridge structure. Utility Model Content

[0003] In view of the shortcomings of the prior art, the present invention aims to provide a high power density half-bridge package structure with reduced size, thereby saving packaging costs.

[0004] To achieve the above objectives, this case provides the following technical solution:

[0005] A half-bridge circuit packaging structure includes a packaging substrate, a half-bridge semiconductor circuit structure, and a packaging housing; wherein the half-bridge semiconductor circuit structure includes an upper bridge circuit and a lower bridge circuit connected in series on the packaging substrate, each of the upper bridge circuit and the lower bridge circuit having a set of chips and sharing a common electrode D / S.

[0006] Furthermore, the upper bridge circuit and the lower bridge circuit are respectively provided with electrode D1 and electrode S2 on both sides of electrode D / S; the upper bridge circuit and the lower bridge circuit also include electrode G and electrode KS, which are arranged parallel to electrode D1, electrode D / S and electrode S2.

[0007] Furthermore, the package housing is provided with electrode terminals, the package substrate is fixedly connected to the package housing, and the half-bridge semiconductor circuit structure is electrically connected to the electrode terminals.

[0008] Furthermore, the packaging substrate is an AMB ceramic substrate with copper plating on both sides, and the chip is soldered onto the packaging substrate; the upper bridge circuit and the lower bridge circuit are bonded together by aluminum wire or copper wire and electrically connected through the AMB ceramic substrate.

[0009] Furthermore, the chip is soldered onto the packaging substrate; the upper bridge circuit and the lower bridge circuit are bonded together by aluminum or copper wires and electrically connected through the AMB ceramic substrate.

[0010] Furthermore, the electrodes G and KS are screw fasteners or copper plug structures.

[0011] The beneficial effects of this invention are: compared with a single transistor of the same chip performance, the volume is reduced by 25%, the cost is reduced by more than 20%, and the power that can be handled per unit volume is greater, meaning a higher power density. It also retains the advantages of silicon carbide, such as low high-frequency switching losses, high voltage resistance, high temperature resistance, and low power consumption, paving the way for the large-scale application of medium- and high-power silicon carbide. Furthermore, the packaging structure of this product can also be used for the packaging of next-generation semiconductor (fourth-generation) gallium oxide and diamond chips, showing broad market prospects. Attached Figure Description

[0012] Figure 1 This is a side view of a half-bridge circuit package structure according to this application.

[0013] Figure 2 This is a top perspective view of a half-bridge circuit package according to this application.

[0014] Figure 3 This is a top perspective view of another embodiment of a half-bridge circuit package according to this application.

[0015] Figure 4 This is the circuit schematic of the half-bridge circuit in this application. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to the embodiments, so that those skilled in the art can implement it based on the description.

[0017] This invention provides, for example Figure 1-4 The illustrated half-bridge circuit packaging structure includes a packaging substrate 2, a half-bridge semiconductor circuit structure 3, and a packaging housing 1. The half-bridge semiconductor circuit structure 3 includes an upper bridge circuit 4 and a lower bridge circuit 5 connected in series on the packaging substrate. Each of the upper bridge circuit 4 and the lower bridge circuit 5 has a set of chips 6, and they share a common electrode D (drain) / S (source) (corresponding to...). Figure 2 and 3 S1(D2)).

[0018] In this embodiment, as Figure 2 and3 As shown, the upper bridge circuit 4 and the lower bridge circuit 5 are distributed left and right. The source S1 (drain D2) is located in the middle, and the drain D1 and source S2 are respectively arranged on both sides of it. The gate G1 and Kelvin KS1 and the gate G2 and Kelvin KS2 are arranged parallel to D1, S1 (D2) and D2 below them.

[0019] In this embodiment, electrode terminals 7 are provided on the package housing, the package substrate 2 is fixedly connected to the package housing 1, and the half-bridge semiconductor circuit structure 3 is electrically connected to the electrode terminals 7. The chip 6 is a silicon carbide MOS chip, composed of a SiC MOSFET chip and a SiC SBD chip. Furthermore, the packaging structure of this application is also applicable to the packaging of next-generation semiconductor (fourth-generation) gallium oxide and diamond chips.

[0020] The packaging substrate 2 is an AMB ceramic substrate with copper plating on both sides; the chip 6 is soldered onto the packaging substrate 2; as shown below. Figure 4 As shown, the upper bridge circuit 4 and the lower bridge circuit 5 are bonded together via aluminum or copper wires and electrically connected through the AMB ceramic substrate. This application packages the chip into the smallest SiC module currently available. Thanks to the shared ceramic and copper substrates for both chips, and the identical manufacturing processes for both chips, not only can the system be miniaturized, but the packaging structure of this application can achieve a length of only 53mm, a width of 28.25mm, and a height (excluding screws) of only 12.8mm, while simultaneously reducing the packaging system cost by at least 20%.

[0021] like Figure 2 and 3 As shown, the gate G1, Kelvin electrode KS1 and gate G2, Kelvin electrode KS2 can be screw fasteners or copper plug structures, with flexible and varied structures and a wide range of applications.

[0022] Although the embodiments of this utility model have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for this utility model. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, this utility model is not limited to the specific details.

Claims

1. A half-bridge circuit package structure, characterized in that, It includes a packaging substrate, a half-bridge semiconductor circuit structure, and a packaging housing; wherein, the half-bridge semiconductor circuit structure includes an upper bridge circuit and a lower bridge circuit connected in series on the packaging substrate, each of the upper bridge circuit and the lower bridge circuit having a set of chips, and sharing a common electrode D / S.

2. The half-bridge circuit packaging structure according to claim 1, characterized in that, The upper bridge circuit and the lower bridge circuit are respectively provided with electrode D1 and electrode S2 on both sides of electrode D / S; the upper bridge circuit and the lower bridge circuit also include electrode G and electrode KS, which are arranged in parallel with electrode D1, electrode D / S and electrode S2.

3. The half-bridge circuit packaging structure according to claim 1, characterized in that, The packaging housing is provided with electrode terminals, the packaging substrate is fixedly connected to the packaging housing, and the half-bridge semiconductor circuit structure is electrically connected to the electrode terminals.

4. The half-bridge circuit packaging structure according to claim 3, characterized in that, The packaging substrate is an AMB ceramic substrate with copper plating on both sides, and the chip is soldered onto the packaging substrate; the upper bridge circuit and the lower bridge circuit are bonded by aluminum wire or copper wire and electrically connected through the AMB ceramic substrate.

5. The half-bridge circuit packaging structure according to claim 2, characterized in that, The electrodes G and KS are screw fasteners or copper plug structures.

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