An optical module
By rationally arranging the via array on the multi-layer circuit board and optimizing the via current density, the problem of uneven via current density in the optical module was solved, a stable power supply was achieved, and the normal operation of the load chip was ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HISENSE BROADBAND MULTIMEDIA TECH
- Filing Date
- 2025-07-31
- Publication Date
- 2026-07-24
Smart Images
Figure CN224553540U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of optical communication technology, and in particular to an optical module. Background Technology
[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve. Utility Model Content
[0003] In some embodiments, an optical module is provided that optimizes the via current density by rationally arranging interlayer vias, thereby providing a stable power supply to the load chip.
[0004] In some embodiments, an optical module is provided, comprising:
[0005] Multilayer circuit boards, including:
[0006] First layer;
[0007] Second layer;
[0008] The third layer, with the second layer located between the first layer and the third layer;
[0009] A first via array connects the top surfaces of the first layer and the second layer to electrically connect the first layer and the second layer;
[0010] The second via array connects the bottom surface of the second layer to the third layer for electrical connection; the projection of the first via array onto the top surface of the second layer is arranged around at least two outer peripheries of the projection of the second via array onto the top surface of the second layer; vias corresponding to the second via array are projected onto the bottom surface of the second layer along a first direction of the first via array; vias corresponding to the second via array are projected onto the bottom surface of the second layer along a second direction of the first via array.
[0011] The above technical solution has the following advantages or beneficial effects: The optical module includes a multilayer circuit board, a first via array, and a second via array. The multilayer circuit board includes a first layer, a second layer, and a third layer. The second layer is located between the first layer and the third layer. The first via array connects the top surfaces of the first layer and the second layer to electrically connect the first layer and the second layer. The second via array connects the bottom surface of the second layer and the third layer to electrically connect the second layer and the third layer. The projection of the first via array on the top surface of the second layer is arranged around at least two outer peripheries of the projection of the second via array on the top surface of the second layer, forming a semi-enclosed or enclosed relationship. A via corresponding to the second via array exists on the projection of the first via array onto the bottom surface of the second layer along a first direction, and a via corresponding to the second via array exists on the projection of the first via array onto the bottom surface of the second layer along a second direction. Therefore, the vias in the second via array can include adjacent vias and non-adjacent vias. Adjacent vias are those adjacent to the first via array, and non-adjacent vias are those other than adjacent vias. For adjacent vias, the spacing between them and their corresponding vias in the first via array is small. For non-adjacent vias, the spacing between them and their corresponding vias in the first via array is also smaller compared to other arrangements in the two via arrays. This allows each via in the first via array to simultaneously maintain electrical connection with vias in the second via array, preventing excessive current concentration in any single via and thus avoiding excessively high local via current density. This optimizes the via current density of each via and provides a stable power connection for the load.
[0012] In some embodiments, the projection area of the first via array on the top surface of the second layer does not overlap with the projection area of the second via array on the top surface of the second layer.
[0013] The above technical solution has the following advantages or beneficial effects: the projection area of the first via array on the top surface of the second layer does not overlap with the projection area of the second via array on the top surface of the second layer, so there is no intersection between the two projection areas, thus avoiding the situation where the relative gap between some vias in the first via array and the vias in the second via array is small, thereby avoiding the situation where the current density of some vias is too high.
[0014] In some embodiments, the projection area of the first via array on the top surface of the second layer is located outside the projection area of the second via array on the top surface of the second layer.
[0015] The above technical solution has the following advantages or beneficial effects: the projection area of the first via array on the top surface of the second layer is outside the projection area of the second via array on the top surface of the second layer. The first via array is arranged around the outer periphery of the second via array. Each via in the first via array can also be electrically connected to the vias in the second via array, increasing the dispersion and uniformity of the arrangement of each via in the first via array. This avoids the current passing through a certain via being too concentrated, thereby avoiding excessively high local via current density, optimizing the via current density of each via, and providing a stable power connection for the load.
[0016] In some embodiments, the spacing between the vias in the second via array and at least two vias in the first via array satisfies a preset spacing.
[0017] The above technical solution has the following advantages or beneficial effects: the spacing between the vias in the second via array and at least two vias in the first via array meets the preset spacing, so the via electrical connection selection in the second via array can be at least two, and the vias in the second via array can select one of the vias that meets the preset spacing for power supply connection, thereby avoiding excessive current concentration in a certain via, thereby optimizing the via current density of each via and providing a stable power supply for the load chip.
[0018] In some embodiments, the vias in the second via array have the same spacing as the two vias in the first via array.
[0019] The above technical solution has the following advantages or beneficial effects: the vias in the second via array have the same spacing as the two vias in the first via array. The vias in the second via array can be connected to the power supply by selecting one of the vias that meets the preset spacing, or the current can be shared by the two vias, thereby balancing the via current density, optimizing the via current density of each via, and providing a stable power supply for the load chip.
[0020] In some embodiments, an optical module is provided, comprising:
[0021] Multilayer circuit boards, including:
[0022] First layer;
[0023] Second layer;
[0024] The third layer, with the second layer located between the first layer and the third layer;
[0025] A first via array connects the top surfaces of the first layer and the second layer to electrically connect the first layer and the second layer;
[0026] A second via array connects the bottom surface of the second layer to the third layer to establish an electrical connection between the second layer and the third layer; the projection of the second via array onto the top surface of the second layer is arranged around at least two outer peripheries of the projection of the first via array onto the top surface of the second layer; vias corresponding to the first via array are projected onto the bottom surface of the second layer along a first direction of the second via array; vias corresponding to the first via array are projected onto the bottom surface of the second layer along a second direction of the second via array.
[0027] The above technical solution has the following advantages or beneficial effects: The optical module includes a multilayer circuit board, a first via array, and a second via array. The multilayer circuit board includes a first layer, a second layer, and a third layer. The second layer is located between the first layer and the third layer. The first via array connects the top surfaces of the first layer and the second layer to electrically connect the first layer and the second layer. The second via array connects the bottom surface of the second layer and the third layer to electrically connect the second layer and the third layer. The projection of the second via array on the top surface of the second layer is arranged around at least two outer peripheries of the projection of the first via array on the top surface of the second layer, forming a semi-enclosed or enclosed relationship. A via corresponding to the first via array exists on the projection of the second via array onto the bottom surface of the second layer along a first direction, and a via corresponding to the first via array exists on the projection of the second via array onto the bottom surface of the second layer along a second direction. Therefore, the vias in the first via array can include adjacent vias and non-adjacent vias. Adjacent vias are those adjacent to the second via array, and non-adjacent vias are those other than adjacent vias. For adjacent vias, the spacing between them and their corresponding vias in the second via array is small. For non-adjacent vias, the spacing between them and their corresponding vias in the second via array is also smaller compared to other arrangements in the two via arrays. This allows each via in the second via array to simultaneously maintain electrical connection with the vias in the first via array, preventing excessive current concentration in any single via and thus avoiding excessively high local via current density. This optimizes the via current density of each via and provides a stable power connection for the load.
[0028] In some embodiments, the projection area of the first via array on the top surface of the second layer does not overlap with the projection area of the second via array on the top surface of the second layer.
[0029] The above technical solution has the following advantages or beneficial effects: the projection area of the first via array on the top surface of the second layer does not overlap with the projection area of the second via array on the top surface of the second layer, so there is no intersection between the two projection areas, thus avoiding the situation where the relative gap between some vias in the first via array and the vias in the second via array is small, thereby avoiding the situation where the current density of some vias is too high.
[0030] In some embodiments, the projection area of the second via array on the top surface of the second layer is located outside the projection area of the first via array on the top surface of the second layer.
[0031] The above technical solution has the following advantages or beneficial effects: the projection area of the second via array on the top surface of the second layer is outside the projection area of the first via array on the top surface of the second layer. Therefore, the second via array is arranged around the outer periphery of the first via array. Each via in the second via array can also be electrically connected to the vias in the first via array, increasing the dispersion and uniformity of the via arrangement in the second via array. This avoids the current passing through a certain via being too concentrated, thereby avoiding excessively high local via current density, optimizing the via current density of each via, and providing a stable power connection for the load.
[0032] In some embodiments, the spacing between the vias in the first via array and at least two vias in the second via array satisfies a preset spacing.
[0033] The above technical solution has the following advantages or beneficial effects: the spacing between the vias in the first via array and at least two vias in the second via array meets the preset spacing, so the via electrical connection selection in the first via array can be at least two, and the vias in the first via array can select one of the vias that meets the preset spacing for power supply connection, thereby avoiding excessive current concentration in a certain via, thereby optimizing the via current density of each via and providing a stable power supply for the load chip.
[0034] In some embodiments, the vias in the first via array have the same spacing as the two vias in the second via array.
[0035] The above technical solution has the following advantages or beneficial effects: the vias in the first via array have the same spacing as the two vias in the second via array. The vias in the first via array can be connected to the power supply through one of the vias that meets the preset spacing, or the current can be shared through the two vias, thereby balancing the via current density, optimizing the via current density of each via, and providing a stable power supply for the load chip. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0037] Figure 1 This is a partial architecture diagram of an optical communication system according to some embodiments;
[0038] Figure 2 This is a partial structural diagram of a host computer according to some embodiments;
[0039] Figure 3 This is a structural diagram of an optical module according to some embodiments;
[0040] Figure 4 An exploded view of an optical module according to some embodiments;
[0041] Figure 5 This is a structural diagram of the internal structure of an optical module according to some embodiments;
[0042] Figure 6 This is an exploded view of the interior of an optical module according to some embodiments;
[0043] Figure 7 This is a diagram showing the arrangement of a first via array and a second via array according to some embodiments;
[0044] Figure 8 for Figure 7 Another perspective on the layout;
[0045] Figure 9 A projection arrangement of a first via array and a second via array according to some embodiments. Figure 1 ;
[0046] Figure 10 A projection arrangement of a first via array and a second via array according to some embodiments. Figure 2 ;
[0047] Figure 11 This is a projection layout of another first via array and a second via array according to some embodiments;
[0048] Figure 12 This is a projection layout diagram of a first via array and a second via array according to some embodiments. Detailed Implementation
[0049] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0050] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.
[0051] In optical communication technology, to establish information transmission between information processing devices, information is loaded onto light, and the speed of light propagation is used to transmit the information. This light carrying information is called an optical signal. When optical signals are transmitted in optical information transmission equipment, optical power loss can be reduced, enabling long-distance transmission of optical signals. At the same time, the cost of optical information transmission equipment such as optical fibers is lower than that of electrical information transmission equipment such as copper wires. Therefore, optical communication technology can achieve high-speed, long-distance, and low-cost information transmission.
[0052] Information processing equipment typically includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., while optical information transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can only recognize and process electrical signals, while optical communication technology uses optical signals for transmission, requiring optical modules to convert between optical and electrical signals.
[0053] An optical module enables the conversion between optical signals and electrical signals between information processing equipment and optical information transmission equipment. In some embodiments, at least one of the optical signal input or output terminals of the optical module is connected to an optical fiber, and at least one of the electrical signal input or output terminals of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber.
[0054] Since multiple information processing devices can transmit information via electrical signals, at least one of these devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is also referred to as the host computer of the optical module. Furthermore, the optical signal input or output terminal of the optical module is called the optical port, and the electrical signal input or output terminal is called the electrical port.
[0055] Figure 1 This is a partial structural diagram of an optical communication system according to some embodiments. Figure 1 As shown, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100 for optical modules, an optical module 200, an optical fiber 101, and a network cable 103. Among them, the optical fiber 101 is an optical information transmission device, and the network cable 103 is an electrical information transmission device.
[0056] In some embodiments, one end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200. The optical signal can undergo total internal reflection in the optical fiber 101, and the propagation of the optical signal in the direction of total internal reflection can almost maintain the original optical power. The optical signal undergoes multiple total internal reflections in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance information transmission based on low power loss.
[0057] The optical communication system includes one or more optical fibers 101. In some embodiments, the optical fiber 101 is detachably connected to the optical module 200; in some embodiments, the optical fiber 101 is non-detachably connected to the optical module 200.
[0058] The host computer 100 is configured to provide data signals to the optical module 200, or receive data signals from the optical module 200, or monitor or control the working status of the optical module 200.
[0059] The host computer 100 includes a housing for accommodating the optical module 200, and an optical module interface 102 disposed on the housing. The optical module 200 is inserted into the housing through the optical module interface 102 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.
[0060] The host computer 100 also includes an external power interface that can connect to an electrical signal network. In some embodiments, the external power interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to connect a network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103.
[0061] One end of the network cable 103 is connected to the local information processing device 2000, and the other end is connected to the host computer 100, so as to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103. In some embodiments, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is transmitted in the optical fiber 101 to the remote information processing device 1000.
[0062] In some embodiments, a first optical signal from a remote information processing device 1000 is transmitted through an optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted to an optical module 200. The optical module 200 converts the first optical signal into a first electrical signal, and transmits the first electrical signal to a host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to a local information processing device 2000.
[0063] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.
[0064] In addition to optical network terminals, the host computer 100 also includes optical line terminals (OLTs), optical network equipment (ONTs), or data center servers.
[0065] Figure 2 This is a partial structural diagram of a host computer according to some embodiments. To clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structure of the host computer 100 related to the optical module 200 is shown. For example... Figure 2As shown, in some embodiments, the host computer 100 further includes a PCB circuit board 105 disposed in the receiving cavity, and a cage 106 disposed on the surface of the PCB circuit board 105; the optical module 200 is inserted into the cage 106 and fixed by the cage 106.
[0066] In some embodiments, a heat sink 107 is provided on the cage 106 to dissipate heat for the optical module; in some embodiments, the heat sink 107 has protruding structures such as fins to increase the heat dissipation area.
[0067] In some embodiments, an electrical connector is provided inside the cage 106, which is configured to connect to the electrical port of the optical module 200.
[0068] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the cage 106 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 106 and then diffused through the heat sink 107.
[0069] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106, thereby establishing an electrical signal connection between the optical module 200 and the host computer 100.
[0070] In some embodiments, the optical port of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.
[0071] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a shell, which comprises an upper shell 201 and a lower shell 202. The upper shell 201 covers the lower shell 202, forming two openings 204 and 205, one of which is an electrical port and the other is an optical port. In some embodiments, the shell forms an opening that serves as both an electrical port and an optical port.
[0072] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.
[0073] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of the circuit board 300, the light emitting component 400, the light receiving component 500, etc. into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the above-mentioned devices.
[0074] The direction of the line connecting the two openings 204 and 205 can be consistent with or inconsistent with the length direction of the optical module 200. For example, opening 204 is located at the end of the optical module 200. Figure 3 The opening 205 is also located at the end of the optical module 200 (right end). Figure 3 (The left end). Alternatively, opening 204 is located at the end of optical module 200, while opening 205 is located on the side of optical module 200.
[0075] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.
[0076] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.
[0077] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.
[0078] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into an electrical connector in the cage 106 of the host computer 100.
[0079] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.
[0080] In some embodiments, the circuit board further includes gold fingers formed on its end surface, the gold fingers consisting of a plurality of independent pins.
[0081] In some implementations, the gold fingers 301 are disposed on one side of the surface of the circuit board 300 (e.g., Figure 4 (as shown on the upper surface); In some implementations, the gold fingers 301 are disposed on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to situations where the number of pins is required.
[0082] In some implementations, the gold fingers of the circuit board extend from the opening 204 and are inserted into the electrical connector of the host computer 100; the circuit board is inserted into the cage 106, and the gold fingers 301 are connected to the electrical connector inside the cage 106. The gold fingers 301 are configured to establish an electrical connection with the host computer, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.
[0083] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.
[0084] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the host computer, so as to release the fixation between the optical module 200 and the host computer, thereby allowing the optical module 200 to be pulled out of the cage 106.
[0085] In some embodiments, the optical module includes a light emitting component 400. In some embodiments, the optical module includes a light receiving component 500.
[0086] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold finger 301.
[0087] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.
[0088] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.
[0089] Figure 5 This is a diagram illustrating the internal structure of an optical module according to some embodiments. Figure 6 This is an exploded view of the interior of an optical module according to some embodiments. Figure 5 and Figure 6 As shown, in some embodiments, the optical module may include a substrate 700 to support and carry the light emitting component 400. The substrate 700 has good thermal conductivity, which is beneficial for heat dissipation of the light emitting component 400 and ensures that the light emitting component 400 can operate normally.
[0090] In some embodiments, a notch 302 is formed on the surface of the circuit board 300 to embed the substrate 700. If the size of the notch 302 is smaller than the area of the substrate 700, the outer periphery of the substrate 700 supports the circuit board 300.
[0091] In some embodiments, the light emitting component 400 may include a laser 410. The laser 410 is located on the surface of the substrate 700. The laser 410 may emit light along its sides without modulating the optical signal, so that the light emitted by the laser 410 does not carry an optical signal. Exemplarily, the laser 410 is a DFB laser.
[0092] In some embodiments, the light emitting component 400 may include a lens 420. The lens 420 is located on the surface of the substrate 700. The lens 420 is located in the light output path of the laser 410. The lens 420 may be a converging lens to converge the diverging light emitted by the laser 410.
[0093] In some embodiments, the light emitting component 400 may include an isolator 430. The isolator 430 is located on the surface of the substrate 700. The isolator 430 is located in the light output path of the lens 420 to reduce the amount of light emitted by the laser 410 returning to the laser 410, thereby ensuring the light output quality of the laser 410.
[0094] In some embodiments, the light emitting component 400 may include an optical modulation chip 440. The optical modulation chip 440 is located on the surface of the substrate 700. The optical modulation chip 440 is located in the light output path of the isolator 430 and receives the light output from the isolator 430. The optical modulation chip 440 modulates the signal phase of the light output from the isolator 430 to generate an optical signal.
[0095] In some embodiments, the optical modulation chip 440 integrates an MZ modulator to modulate the optical signal and transmit it. Exemplarily, the optical modulation chip 440 can be a silicon photonics chip, a thin-film lithium niobate chip, or a III-V group photonics chip.
[0096] In some embodiments, the light emitting component 400 may include an optical fiber array 450. The optical fiber array 450 is located on the surface of the substrate 700. The optical fiber array 450 is end-face coupled to the optical modulation chip 440. The optical fiber array 450 is located in the light output path of the optical modulation chip 440 to transmit the optical signal modulated by the optical modulation chip 440 to the outside.
[0097] In some embodiments, the light emitted by the laser 410 is transmitted to the optical modulation chip 440, where it is modulated to generate an optical signal. The optical signal is then output from the optical modulation chip 440 and transmitted through the fiber array 450.
[0098] In some embodiments, the laser 410, lens 420, and isolator 430 are located in the incident optical path of the optical modulation chip 440, providing the light source to be modulated to the optical modulation chip 440. The fiber array 450 is coupled to the output optical port of the optical modulation chip 440. Since the incident and output ports of the optical modulation chip 440 are formed on the same side, the laser 410, lens 420, isolator 430, and fiber array 450 are located on the same side of the optical modulation chip 440.
[0099] In some embodiments, a DSP chip 303 is provided on the surface of the circuit board 300. The DSP chip 303 provides a modulation drive signal to the optical modulation chip 440 to drive the optical modulation chip 440 to modulate the optical signal.
[0100] In some embodiments, as the optical module transmission rate increases, the current required by load chips such as the DSP chip 303 also increases. Stable output of high current is crucial for the normal operation of load chips such as the DSP chip 303.
[0101] In some embodiments, power is supplied to the load chip by utilizing the space between the circuit board layers and connecting them via interlayer vias. The arrangement of these interlayer vias affects the via current density; excessively high current density leads to a significant increase in temperature in and around the vias. Furthermore, under DC or high-current pulse conditions, excessively high current density drives metal ions to migrate along the direction of electron flow, which, over time, can cause voids, increase resistance, and even open circuits. Via current density refers to the magnitude of the current flowing through the cross-section of the via per unit area.
[0102] In some embodiments, the interlayer vias are arranged in a reasonable manner to allocate large current transmission, optimize via current density, and provide a stable power supply for the load chip.
[0103] Figure 7 This is a diagram showing the arrangement of a first via array and a second via array according to some embodiments. Figure 8 for Figure 7 A layout diagram from another perspective. For example... Figure 7-8 As shown, in some embodiments, the circuit board 300 is a multilayer circuit board, and power transmission is achieved through interlayer vias.
[0104] In some embodiments, the multilayer circuit board may include a first layer 311.
[0105] In some embodiments, the multilayer circuit board may include a second layer 312.
[0106] In some embodiments, the multilayer circuit board may include a third layer 313.
[0107] In some embodiments, the second layer 312 is located between the first layer 311 and the third layer 313.
[0108] In some embodiments, the first layer 311 may be the upper surface layer of a multilayer circuit board, the second layer 312 may be the inner layer of the multilayer circuit board, and the third layer 313 may be the inner layer or the lower surface layer of the multilayer circuit board.
[0109] In some embodiments, the first layer 311 may be an inner layer of a multilayer circuit board, the second layer 312 may be an inner layer of a multilayer circuit board, and the third layer 313 may be an inner layer or a lower surface layer of a multilayer circuit board.
[0110] In some embodiments, a first via array 304 is connected between the top surfaces of the first layer 311 and the second layer 312 to establish an electrical connection between the first layer 311 and the second layer 312.
[0111] In some embodiments, a second via array 305 is connected between the bottom surface of the second layer 312 and the third layer 313 to establish an electrical connection between the second layer 312 and the third layer 313. The second layer 312 serves as a transition layer between the first via array 304 and the second via array 305, and power supply relay is performed on the second layer 312.
[0112] In some embodiments, Figure 7 From the perspective of looking along the direction perpendicular to the paper, that is, along the depth direction, the first via array 304 has vias on the projection of the bottom surface of the second layer 312 located outside the second via array 305, and there are also vias in the first via array 304 located inside the second via array 305.
[0113] In some embodiments, Figure 8 The perspective can be Figure 7 Rotate your perspective by a certain angle and look along a direction perpendicular to the paper, that is, along the depth direction. Figure 7 The vias located inside the second via array 305 in the first via array 304, in Figure 8 From the perspective of [the viewpoint], it is located outside the second via array 305.
[0114] In some embodiments, the first via array 304 includes a set of vias in direction a and a set of vias in direction b. Direction a can be a column direction, and direction b can be a row direction. Figure 7 From a certain perspective, a set of vias in direction a is located outside the second via array 305, and a set of vias in direction b is located inside the second via array 305. Figure 8 From the perspective of viewpoint b, a set of vias is located outside the second via array 305.
[0115] Figure 9 A projection arrangement of a first via array and a second via array according to some embodiments. Figure 1 .like Figure 9 As shown, in some embodiments, the first via array 304 is used to electrically connect the first layer 311 and the second layer 312, and the second via array 305 is used to electrically connect the second layer 312 and the third layer 313. The current transmitted to the load, such as the DSP chip 303, flows through the first via array 304 and the second via array 305 respectively. Figure 9 In the diagram, vias 1-2 represent vias that electrically connect the first layer 311 and the second layer 312, and vias 2-3 represent vias that electrically connect the second layer 312 and the third layer 313.
[0116] In some embodiments, the first via array 304 may be located above the second via array 305. The projection of the first via array 304 on the top surface of the second layer 312 is arranged around at least two outer peripheries of the projection of the second via array 305 on the top surface of the second layer 312, forming a semi-enclosed or enclosed relationship.
[0117] In some embodiments, a via corresponding to a second via array 305 is projected onto the bottom surface of the second layer 312 along the first direction of the first via array 304, and a via corresponding to a second via array 305 is projected onto the bottom surface of the second layer 312 along the second direction of the first via array 304. The vias in the second via array 305 can include adjacent vias and non-adjacent vias. Adjacent vias are those adjacent to the first via array 304, and non-adjacent vias are those other than adjacent vias. For adjacent vias, the spacing between them and their corresponding vias in the first via array 304 is small. For non-adjacent vias, the spacing between them and their corresponding vias in the first via array 304 is also small compared to other arrangements of the two via arrays. Each via in the first via array 304 can simultaneously provide electrical connection to the vias in the second via array 305, preventing excessive current concentration in any single via and thus avoiding excessively high local via current density. This optimizes the via current density of each via and provides a stable power connection to the load. The first direction along the first via array 304 can be along the row direction of the first via array 304, and the second direction along the first via array 304 can be along the column direction of the first via array 304.
[0118] In some embodiments, at least one via corresponding to the second via array 305 is projected onto the bottom surface of the second layer 312 along the first direction of the first via array 304, and at least one via corresponding to the second via array 305 is projected onto the bottom surface of the second layer 312 along the second direction of the first via array 304.
[0119] In some embodiments, the projection area of the first via array 304 on the top surface of the second layer 312 does not overlap with the projection area of the second via array 305 on the top surface of the second layer 312. Therefore, there is no intersection between the two projection areas, which avoids the situation where the relative gap between some vias in the first via array 304 and the vias in the second via array 305 is small, thereby avoiding the situation where the current density of some vias is too high.
[0120] In some embodiments, the projection area of the first via array 304 on the top surface of the second layer 312 is located outside the projection area of the second via array 305 on the top surface of the second layer 312. In this case, the first via array 304 is arranged around the outer periphery of the second via array 305. Each via in the first via array 304 can also be electrically connected to the vias in the second via array 305, increasing the dispersion and uniformity of the via arrangement in the first via array 304. This avoids excessive current concentration in any single via, thus preventing excessively high local via current density, optimizing the via current density of each via, and providing a stable power connection for the load. The first via array 304 can be located above the second via array 305, in which case the projection area of the first via array 304 on the top surface of the second layer 312 partially surrounds or encloses the projection area of the second via array 305 on the top surface of the second layer 312, i.e., an upper-enclosing structure.
[0121] In some embodiments, if the spacing between the vias in the second via array 305 and at least two vias in the first via array 304 satisfies a preset spacing, then at least two via electrical connections can be selected in the second via array 305. The vias in the second via array 305 can select one of the vias that satisfies the preset spacing for power supply connection, thereby avoiding excessive current concentration in a certain via, thus optimizing the via current density of each via and providing a stable power supply for the load chip.
[0122] In some embodiments, the vias in the second via array 305 have the same spacing as the two vias in the first via array 304. The vias in the second via array 305 can be selected to power supply one of the vias that meets the preset spacing, or the current can be shared between the two vias, thereby balancing the via current density, optimizing the via current density of each via, and providing a stable power supply for the load chip.
[0123] In some embodiments, at least one set of vias in the second via array 305 has an axis parallel to the axis of a set of vias in the first via array 304. This shortens the spacing between the corresponding set of vias in the second via array 305 and the corresponding set of vias in the first via array 304, and balances the spacing between these two sets of vias. This achieves distributed power supply connection between vias, thereby avoiding excessively high local via current density, optimizing the via current density of each via, and providing a stable power supply to the load chip. For example, the rows of vias in the second via array 305 are parallel to each other, with the axis of one row of vias being parallel to the axis of one row of vias in the first via array 304. This parallel arrangement helps to further balance the current distribution between vias, ensuring the stability and efficiency of current transmission.
[0124] In some embodiments, in order to further optimize the via current density, the vias in the second via array 305 and the vias in the first via array 304 can be arranged in an alternating manner so that the current is more dispersed during transmission, avoiding concentration in a certain via or a certain area, thereby effectively reducing the temperature of the via and its surrounding area.
[0125] Figure 10 A projection arrangement of a first via array and a second via array according to some embodiments. Figure 2 .like Figure 10 As shown, in some embodiments, the first via array 304 is used to electrically connect the first layer 311 and the second layer 312, and the second via array 305 is used to electrically connect the second layer 312 and the third layer 313. The current transmitted to the load, such as the DSP chip 303, flows through the first via array 304 and the second via array 305 respectively. Figure 9 In the diagram, vias 1-2 represent vias that electrically connect the first layer 311 and the second layer 312, and vias 2-3 represent vias that electrically connect the second layer 312 and the third layer 313.
[0126] In some embodiments, the first via array 304 may be located above the second via array 305. The projection of the second via array 305 on the top surface of the second layer 312 is arranged around at least two outer peripheries of the projection of the first via array 304 on the top surface of the second layer 312, forming a semi-enclosed or enclosed relationship.
[0127] In some embodiments, the projection area of the second via array 305 on the top surface of the second layer 312 is outside the projection area of the first via array 304 on the top surface of the second layer 312. The second via array 305 is arranged around the outer periphery of the first via array 304. Each via in the second via array 305 can also be electrically connected to the vias in the first via array 304, increasing the dispersion and uniformity of the via arrangement in the second via array 305. This avoids excessive current concentration in any single via, thus preventing excessively high local via current density, optimizing the via current density of each via, and providing a stable power connection for the load. The first via array 304 can be located above the second via array 305. In this case, the projection area of the second via array 305 on the top surface of the second layer 312 partially surrounds or encloses the projection area of the first via array 304 on the top surface of the second layer 312, i.e., an upper-enclosing structure.
[0128] In some embodiments, a via corresponding to the first via array 304 is projected onto the bottom surface of the second layer 312 along the first direction of the second via array 305, and a via corresponding to the first via array 304 is projected onto the bottom surface of the second layer 312 along the second direction of the second via array 305. The vias in the first via array 304 can include adjacent vias and non-adjacent vias. Adjacent vias are those adjacent to the second via array 305, and non-adjacent vias are those other than adjacent vias. For adjacent vias, the spacing between them and their corresponding vias in the second via array 305 is small. For non-adjacent vias, the spacing between them and their corresponding vias in the second via array 305 is also small compared to other arrangements of the two via arrays. Each via in the second via array 305 can simultaneously provide electrical connections to the vias in the first via array 304, preventing excessive current concentration in any single via and thus avoiding excessively high local via current density. This optimizes the via current density of each via and provides a stable power connection to the load. The first direction along the second via array 305 can be the row direction, and the second direction along the second via array 305 can be the column direction.
[0129] In some embodiments, at least one via corresponding to the first via array 304 is projected onto the bottom surface of the second layer 312 along the first direction of the second via array 305, and at least one via corresponding to the first via array 304 is projected onto the bottom surface of the second layer 312 along the second direction of the second via array 305.
[0130] In some embodiments, the projection area of the first via array 304 on the top surface of the second layer 312 does not overlap with the projection area of the second via array 305 on the top surface of the second layer 312. Therefore, there is no intersection between the two projection areas, which avoids the situation where the relative gap between some vias in the first via array 304 and the vias in the second via array 305 is small, thereby avoiding the situation where the current density of some vias is too high.
[0131] In some embodiments, if the spacing between the vias in the first via array 304 and at least two vias in the second via array 305 satisfies a preset spacing, then the via electrical connection selection in the first via array 304 can be at least two. The vias in the first via array 304 can select one of the vias that satisfies the preset spacing for power supply connection, thereby avoiding excessive current concentration in a certain via, thus optimizing the via current density of each via and providing a stable power supply for the load chip.
[0132] In some embodiments, the vias in the first via array 304 have the same spacing as the two vias in the second via array 305. The vias in the first via array 304 can be selected to power supply one of the vias that meets the preset spacing, or the current can be shared between the two vias, thereby balancing the via current density, optimizing the via current density of each via, and providing a stable power supply for the load chip.
[0133] Figure 11 This is a projection layout of another first via array and a second via array according to some embodiments. Figure 11 As shown, in some embodiments, the vias in the second via array 305 are staggered. The vias in the first via array 304 are arranged along the outer side of the second via array 305.
[0134] In some embodiments, a via corresponding to a second via array 305 is projected onto the bottom surface of the second layer 312 along the first direction of the first via array 304, and a via corresponding to a second via array 305 is projected onto the bottom surface of the second layer 312 along the second direction of the first via array 304. The vias in the second via array 305 can include adjacent vias and non-adjacent vias. Adjacent vias are those adjacent to the first via array 304, and non-adjacent vias are those other than adjacent vias. For adjacent vias, the spacing between them and their corresponding vias in the first via array 304 is small. For non-adjacent vias, the spacing between them and their corresponding vias in the first via array 304 is also small compared to other arrangements of the two via arrays. Each via in the first via array 304 can simultaneously provide electrical connection to the vias in the second via array 305, preventing excessive current concentration in any single via and thus avoiding excessively high local via current density. This optimizes the via current density of each via and provides a stable power connection to the load. The first direction along the first via array 304 can be along the row direction of the first via array 304, and the second direction along the first via array 304 can be along the column direction of the first via array 304.
[0135] In some embodiments, at least one via corresponding to the second via array 305 is projected onto the bottom surface of the second layer 312 along the first direction of the first via array 304, and at least one via corresponding to the second via array 305 is projected onto the bottom surface of the second layer 312 along the second direction of the first via array 304.
[0136] Figure 12 This is a projection layout diagram of another first via array and a second via array according to some embodiments. For example... Figure 12As shown, in some embodiments, the vias in the second via array 305 are arranged radially outward from the central via. The vias in the first via array 304 are arranged along the outer side of the second via array 305.
[0137] In some embodiments, a via corresponding to a second via array 305 is projected onto the bottom surface of the second layer 312 along the first direction of the first via array 304, and a via corresponding to a second via array 305 is projected onto the bottom surface of the second layer 312 along the second direction of the first via array 304. The vias in the second via array 305 can include adjacent vias and non-adjacent vias. Adjacent vias are those adjacent to the first via array 304, and non-adjacent vias are those other than adjacent vias. For adjacent vias, the spacing between them and their corresponding vias in the first via array 304 is small. For non-adjacent vias, the spacing between them and their corresponding vias in the first via array 304 is also small compared to other arrangements of the two via arrays. Each via in the first via array 304 can simultaneously provide electrical connection to the vias in the second via array 305, preventing excessive current concentration in any single via and thus avoiding excessively high local via current density. This optimizes the via current density of each via and provides a stable power connection to the load. The first direction along the first via array 304 can be along the row direction of the first via array 304, and the second direction along the first via array 304 can be along the column direction of the first via array 304.
[0138] In some embodiments, at least one via corresponding to the second via array 305 is projected onto the bottom surface of the second layer 312 along the first direction of the first via array 304, and at least one via corresponding to the second via array 305 is projected onto the bottom surface of the second layer 312 along the second direction of the first via array 304.
[0139] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. An optical module, characterized in that, include: Multilayer circuit boards, including: First layer; Second layer; The third layer, with the second layer located between the first layer and the third layer; A first via array connects the top surfaces of the first layer and the second layer to electrically connect the first layer and the second layer; The second via array connects the bottom surface of the second layer to the third layer for electrical connection; the projection of the first via array onto the top surface of the second layer is arranged around at least two outer peripheries of the projection of the second via array onto the top surface of the second layer; vias corresponding to the second via array are projected onto the bottom surface of the second layer along a first direction of the first via array; vias corresponding to the second via array are projected onto the bottom surface of the second layer along a second direction of the first via array.
2. The optical module according to claim 1, characterized in that, The projection area of the first via array on the top surface of the second layer does not overlap with the projection area of the second via array on the top surface of the second layer.
3. The optical module according to claim 1, characterized in that, The projection area of the first via array on the top surface of the second layer is located outside the projection area of the second via array on the top surface of the second layer.
4. The optical module according to claim 1, characterized in that, The spacing between the vias in the second via array and at least two vias in the first via array satisfies a preset spacing.
5. The optical module according to claim 1, characterized in that, The second via array contains vias with the same spacing as the two vias in the first via array.
6. An optical module, characterized in that, include: Multilayer circuit boards, including: First layer; Second layer; The third layer, with the second layer located between the first layer and the third layer; A first via array connects the top surfaces of the first layer and the second layer to electrically connect the first layer and the second layer; A second via array connects the bottom surface of the second layer to the third layer to establish an electrical connection between the second layer and the third layer; the projection of the second via array onto the top surface of the second layer is arranged around at least two outer peripheries of the projection of the first via array onto the top surface of the second layer; vias corresponding to the first via array are projected onto the bottom surface of the second layer along a first direction of the second via array; vias corresponding to the first via array are projected onto the bottom surface of the second layer along a second direction of the second via array.
7. The optical module according to claim 6, characterized in that, The projection area of the first via array on the top surface of the second layer does not overlap with the projection area of the second via array on the top surface of the second layer.
8. The optical module according to claim 6, characterized in that, The projection area of the second via array on the top surface of the second layer is outside the projection area of the first via array on the top surface of the second layer.
9. The optical module according to claim 6, characterized in that, The spacing between the vias in the first via array and at least two vias in the second via array satisfies a preset spacing.
10. The optical module according to claim 6, characterized in that, The vias in the first via array have the same spacing as the two vias in the second via array.