Pixel, display device, and electronic device

Abstract

A pixel, a display device, and an electronic device are disclosed. The pixel includes a pulse width modulation ("PWM") circuit configured to generate a PWM signal based on a PWM data voltage and a sweep voltage, a constant current generation ("CCG") circuit configured to generate an emission current based on a CCG data voltage and the PWM signal, and a light emitting element configured to emit light based on the emission current. The CCG circuit includes a CCG driving transistor configured to generate the emission current, a first capacitor including a first electrode receiving a first CCG supply voltage having a relatively high power voltage level and a second electrode connected to a gate of the CCG driving transistor, and a second capacitor including a first electrode connected to the gate of the CCG driving transistor and a second electrode receiving the PWM signal generated by the PWM circuit.

Description

Technical Field

[0001] Embodiments of this inventive concept relate to display devices, and more specifically, to pixels that drive light-emitting elements according to a pulse width modulation (“PWM”) method, display devices including pixels, and electronic devices including display devices. Background Technology

[0002] Display devices can display images by driving light-emitting elements (such as micron-sized light-emitting diodes (“μLEDs”) or organic light-emitting diodes (“OLEDs”) using, for example, pulse amplitude modulation (“PAM”) or pulse width modulation (“PWM”) methods. In the PAM method, gray levels can be represented by adjusting the amount (or amplitude) of the driving current supplied to the light-emitting element. In the PWM method, gray levels can be represented by adjusting the time period (or pulse width) during which the driving current is supplied to the light-emitting element. Utility Model Content

[0003] The wavelength of light emitted by a light-emitting element such as a μLED can shift depending on the amount of driving current. Therefore, when driving a light-emitting element such as a μLED using the PAM method, for example, color shift may occur, and the image may be distorted.

[0004] Some implementations provide a method for driving pixels of light-emitting elements using pulse width modulation (“PWM”).

[0005] Some embodiments provide a display device that includes pixels with light-emitting elements driven by a PWM method and has improved image quality.

[0006] In embodiments of this disclosure, a pixel of a display device is provided. The pixel includes: a PWM circuit that generates a PWM signal based on a PWM data voltage and a sweep voltage; a constant current generation (“CCG”) circuit that generates an emission current based on the CCG data voltage and the PWM signal; and a light-emitting element that emits light based on the emission current. The CCG circuit includes: a CCG driving transistor that generates the emission current; a first capacitor including a first electrode receiving a first CCG power supply voltage having a relatively high power voltage level and a second electrode connected to the gate of the CCG driving transistor; and a second capacitor including a first electrode connected to the gate of the CCG driving transistor and a second electrode receiving the PWM signal generated by the PWM circuit.

[0007] In this implementation, the sweep voltage can be gradually increased during the sweep cycle. When the sweep voltage is higher than the PWM data voltage, the PWM circuit can apply the sweep voltage as a PWM signal to the CCG circuit. The CCG circuit can start generating a transmitting current at the beginning of the sweep cycle and can stop generating the transmitting current in response to the sweep voltage.

[0008] In one implementation, the sweep voltage applied to the CCG circuit can be transmitted to the gate of the CCG driving transistor via the connection of the second capacitor.

[0009] In an embodiment, the CCG driving transistor may include a second electrode connected to a first capacitor and a gate of the first electrode of the second capacitor, a first terminal receiving a first CCG power supply voltage, and a second terminal connected to a light-emitting element.

[0010] In an embodiment, the CCG circuit may further include: a first transistor that applies a reset voltage to the gate of the CCG driving transistor in response to a first scan signal; a second transistor that is diode-connected to the CCG driving transistor in response to a second scan signal; and a third transistor that applies a CCG data voltage to the second electrode of a second capacitor in response to a third scan signal.

[0011] In this implementation, the third scan signal can be a write signal for the Nth pixel row in which pixels are arranged, where N is an integer greater than or equal to 3. The second scan signal can be a write signal for the (N-1)th pixel row. The first scan signal can be a write signal for the (N-2)th pixel row.

[0012] In one embodiment, the first transistor may include a gate for receiving a first scan signal, a first terminal for receiving a reset voltage, and a second terminal connected to the gate of the CCG driving transistor, the second electrode of the first capacitor, and the second electrode of the second capacitor. The second transistor may include a gate for receiving a second scan signal, a first terminal connected to the second terminal of the CCG driving transistor, and a second terminal connected to the gate of the CCG driving transistor, the second electrode of the first capacitor, and the first electrode of the second capacitor. The third transistor may include a gate for receiving a third scan signal, a first terminal for receiving CCG data voltage, and a second terminal connected to the second electrode of the second capacitor.

[0013] In an implementation, the CCG circuit may further include: a fourth transistor that provides an emission current generated by the CCG driving transistor to the light-emitting element in response to an emission signal; a fifth transistor that applies a reference voltage to the second electrode of the second capacitor in response to a fourth scan signal; and a sixth transistor that initializes the light-emitting element in response to a first scan signal.

[0014] In one embodiment, the fourth transistor may include a gate for receiving a transmitted signal, a first terminal connected to the second terminal of the CCG driving transistor, and a second terminal connected to the light-emitting element. The fifth transistor may include a gate for receiving a fourth scan signal, a first terminal connected to the second electrode of the second capacitor, and a second terminal for receiving a reference voltage. The sixth transistor may include a gate for receiving a first scan signal, a first terminal connected to the anode of the light-emitting element, and a second terminal for receiving a second CCG power supply voltage having a relatively low power voltage level.

[0015] In an implementation, the PWM circuit may include: a third capacitor, including a first electrode and a second electrode for receiving a PWM power supply voltage; and a PWM drive transistor, including a gate connected to the second electrode of the third capacitor, a first terminal for receiving a sweep voltage, and a second terminal for outputting a PWM signal.

[0016] In an implementation, the PWM circuit may further include: a seventh transistor that applies a sweep voltage to a first terminal of the PWM drive transistor in response to a transmit signal; an eighth transistor that applies a PWM data voltage to a first terminal of the PWM drive transistor in response to a second scan signal; a ninth transistor that is diode-connected to the PWM drive transistor in response to the second scan signal; a tenth transistor that applies a PWM signal generated by the PWM drive transistor to the CCG circuit in response to a fourth scan signal; and an eleventh transistor that applies a reset voltage to a second electrode of a third capacitor in response to a first scan signal.

[0017] In one embodiment, the seventh transistor may include a gate for receiving a transmit signal, a first terminal for receiving a sweep voltage, and a second terminal connected to the first terminal of the PWM drive transistor. The eighth transistor may include a gate for receiving a second scan signal, a first terminal for receiving a PWM data voltage, and a second terminal connected to the first terminal of the PWM drive transistor. The ninth transistor may include a gate for receiving a second scan signal, a first terminal connected to the second terminal of the PWM drive transistor, and a second terminal connected to the gate of the PWM drive transistor and the second electrode of the third capacitor. The tenth transistor may include a gate for receiving a fourth scan signal, a first terminal connected to the second terminal of the PWM drive transistor, and a second terminal connected to the CCG circuit. The eleventh transistor may include a gate for receiving a first scan signal, a first terminal connected to the second electrode of the third capacitor, and a second terminal for receiving a reset voltage.

[0018] In an implementation, the frame period for a pixel may include: an initialization period in which a first capacitor, a second capacitor, and a third capacitor included in a PWM circuit are initialized; a compensation period in which a PWM data voltage is provided to the PWM circuit, and the threshold voltage of the PWM driving transistor and the threshold voltage of the CCG driving transistor included in the PWM circuit are compensated; a write period in which a CCG data voltage is provided to the CCG circuit; and a frequency sweep period in which the frequency sweep voltage gradually increases.

[0019] In an implementation, the frequency sweep period may include: a transmission period in which the frequency sweep voltage is lower than the PWM data voltage and the light-emitting element emits light; and a non-transmission period in which the frequency sweep voltage is higher than the PWM data voltage and the light-emitting element does not emit light.

[0020] In embodiments of this disclosure, a pixel of a display device is provided. The pixel includes: a first capacitor including a first electrode and a second electrode receiving a first CCG power supply voltage having a relatively high power voltage level; a second capacitor including a first electrode and a second electrode connected to the second electrode of the first capacitor; a CCG driving transistor including a gate connected to the second electrode of the first capacitor and a gate of the first electrode of the second capacitor, a first terminal and a second terminal receiving the first CCG power supply voltage; a first transistor including a gate receiving a first scan signal, a first terminal receiving a reset voltage, and a second terminal connected to the gate of the CCG driving transistor; a second transistor including a gate receiving a second scan signal, a first terminal connected to the second terminal of the CCG driving transistor, and a second terminal connected to the gate of the CCG driving transistor; a third transistor including a gate receiving a third scan signal, a first terminal receiving a CCG data voltage, and a second terminal connected to the second electrode of the second capacitor; a fourth transistor including a gate receiving a transmit signal, a first terminal connected to the second terminal of the CCG driving transistor, and a second terminal connected to the second electrode of the second capacitor; a fifth transistor including a gate receiving a fourth scan signal, a first terminal connected to the second electrode of the second capacitor, and a second terminal receiving a reference voltage; and a sixth transistor including a gate receiving the first scan signal, a first terminal connected to the first electrode of the second capacitor, and a second terminal connected to the second electrode of the second capacitor. The transistor comprises: a second terminal receiving a second CCG power supply voltage having a relatively low power voltage level; a third capacitor including a first electrode and a second electrode receiving a PWM power supply voltage; a PWM driving transistor including a gate, a first terminal, and a second terminal connected to the second electrode of the third capacitor; a seventh transistor including a gate receiving a transmit signal, a first terminal receiving a sweep voltage, and a second terminal connected to the first terminal of the PWM driving transistor; an eighth transistor including a gate receiving a second scan signal, a first terminal receiving a PWM data voltage, and a second terminal connected to the first terminal of the PWM driving transistor; a ninth transistor including a gate receiving a second scan signal, a first terminal connected to the second terminal of the PWM driving transistor, and a second terminal connected to the gate of the PWM driving transistor; a tenth transistor including a gate receiving a fourth scan signal, a first terminal connected to the second terminal of the PWM driving transistor, and a second terminal connected to the second electrode of the second capacitor; an eleventh transistor including a gate receiving a first scan signal, a first terminal connected to the second electrode of the third capacitor, and a second terminal receiving a reset voltage; and a light-emitting element including an anode connected to the second terminal of the fourth transistor and the first terminal of the sixth transistor, and a cathode receiving the second CCG power supply voltage.

[0021] In the implementation, the CCG driving transistor, the PWM driving transistor, the fourth transistor, the seventh transistor, and the tenth transistor can be P-type transistors, and the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor, and the eleventh transistor can be N-type transistors.

[0022] In an implementation, the frame period of a pixel may include: an initialization period, in which the first scan signal, the fourth scan signal, and the transmit signal have relatively high levels, the second scan signal and the third scan signal have relatively low levels, and the first capacitor, the second capacitor, and the third capacitor are initialized; a compensation period, in which the second scan signal, the fourth scan signal, and the transmit signal have relatively high levels, the first scan signal and the third scan signal have relatively low levels, a PWM data voltage is provided to the pixel, the threshold voltage of the PWM driving transistor is compensated, and the threshold voltage of the CCG driving transistor is compensated; a write period, in which the third scan signal and the transmit signal have relatively high levels, the first scan signal, the second scan signal, and the fourth scan signal have relatively low levels, and a CCG data voltage is provided to the pixel; and a frequency sweep period, in which the first scan signal, the second scan signal, the third scan signal, the fourth scan signal, and the transmit signal have relatively low levels, and the frequency sweep voltage gradually increases.

[0023] In an implementation, the frequency sweep period may include: a transmission period in which the frequency sweep voltage is lower than the PWM data voltage and the light-emitting element emits light; and a non-transmission period in which the frequency sweep voltage is higher than the PWM data voltage and the light-emitting element does not emit light.

[0024] In embodiments of this disclosure, a display device is provided, comprising: a display panel including a plurality of pixels; a scan driver providing a scan signal to each of the plurality of pixels; a transmit driver providing a transmit signal to each of the plurality of pixels; a sweep driver providing a sweep voltage to each of the plurality of pixels; a data driver providing a PWM data voltage and a CCG data voltage to each of the plurality of pixels; and a controller controlling the scan driver, the transmit driver, the sweep driver, and the data driver. Each of the plurality of pixels includes: a PWM circuit generating a PWM signal based on the PWM data voltage and the sweep voltage; a CCG circuit generating an transmit current based on the CCG data voltage and the PWM signal; and a light-emitting element emitting light based on the transmit current. The CCG circuit includes: a CCG driving transistor generating the transmit current; a first capacitor including a first electrode receiving a first CCG power supply voltage having a relatively high power voltage level and a second electrode connected to the gate of the CCG driving transistor; and a second capacitor including a first electrode connected to the gate of the CCG driving transistor and a second electrode receiving the PWM signal generated by the PWM circuit.

[0025] In this implementation, the sweep voltage can be gradually increased during the sweep cycle. When the sweep voltage is higher than the PWM data voltage, the PWM circuit can apply the sweep voltage as a PWM signal to the CCG circuit. The CCG circuit can start generating a transmitting current at the beginning of the sweep cycle and can stop generating the transmitting current in response to the sweep voltage. Through the connection of the second capacitor, the sweep voltage applied to the CCG circuit can be transmitted to the gate of the CCG driving transistor.

[0026] An electronic device is provided through an implementation, comprising: a processor for providing input image data; and a display device for receiving the input image data from the processor and displaying an image based on the input image data. The display device includes: a display panel including a plurality of pixels; a scan driver for providing a scan signal to each of the plurality of pixels; a transmit driver for providing a transmit signal to each of the plurality of pixels; a sweep driver for providing a sweep voltage to each of the plurality of pixels; a data driver for providing a PWM data voltage and a CCG data voltage to each of the plurality of pixels; and a controller for controlling the scan driver, the transmit driver, the sweep driver, and the data driver. Each of the plurality of pixels includes: a PWM circuit for generating a PWM signal based on the PWM data voltage and the sweep voltage; a CCG circuit for generating an transmit current based on the CCG data voltage and the PWM signal; and a light-emitting element for emitting light based on the transmit current. The CCG circuit includes: a CCG driving transistor for generating the transmit current; a first capacitor including a first electrode receiving a first CCG power supply voltage having a relatively high power voltage level and a second electrode connected to the gate of the CCG driving transistor; and a second capacitor including a first electrode connected to the gate of the CCG driving transistor and a second electrode receiving the PWM signal generated by the PWM circuit.

[0027] As described above, in the pixel and display device of the embodiment, the PWM driving transistor in the PWM circuit can receive a sweep voltage at its terminal (e.g., the source). Therefore, during the sweep cycle in which the sweep voltage gradually changes, the voltage at the gate of the PWM driving transistor can be substantially constant. Thus, when the CCG driving transistor generates an emission current, the voltage at the gate of the CCG driving transistor can be undistorted by the sweep voltage, and the emission current can have a desired target current level.

[0028] Furthermore, in the pixel and display device of the embodiment, the CCG circuit that generates the emission current may include a first capacitor and a second capacitor connected to the gate of the CCG driving transistor, and the PWM signal received from the PWM circuit can be transmitted to the gate of the CCG driving transistor through the connection of the second capacitor. Therefore, when the CCG driving transistor changes from an on state to an off state, or during the fall time in which the emission current decreases, the voltage stored in the second capacitor, or the voltage reflected by the threshold voltage of the CCG driving transistor, can be substantially maintained. Therefore, even when the emission current decreases, the threshold voltage deviation between the CCG driving transistors of multiple pixels can be compensated, and the image quality of the display device can be improved. Attached Figure Description

[0029] The illustrative and non-limiting embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 This is a circuit diagram illustrating an embodiment of the pixels of a display device.

[0031] Figure 2 The diagram illustrates an embodiment of the emitter current in a pixel in which the gate voltage of the pulse width modulation (“PWM”) driven transistor changes during a sweep cycle, and an embodiment of the emitter current in a pixel according to the present application.

[0032] Figure 3 The figure illustrates an embodiment of the emitter current during the fall time duration in a pixel in which a PWM signal is applied to the gate of a CCG driving transistor when the constant current generation (“CCG”) driving transistor has different threshold voltages, and an embodiment of the emitter current during the fall time duration in a pixel according to the present application when the CCG driving transistor has different threshold voltages.

[0033] Figure 4 The figure illustrates an embodiment of the current error rate based on the PWM data voltage in a pixel where a PWM signal is applied to the gate of the CCG driving transistor in the case of a shift in the threshold voltage of the CCG driving transistor, and an embodiment of the current error rate based on the PWM data voltage in a pixel according to the present application in the case of a shift in the threshold voltage of the CCG driving transistor.

[0034] Figure 5 It is a timing diagram used to describe the implementation of pixel operations.

[0035] Figure 6 This is a circuit diagram used to describe an implementation of pixel operation during the initialization cycle.

[0036] Figure 7 This is a circuit diagram used to describe an implementation of the operation of a pixel during a compensation period.

[0037] Figure 8 This is a circuit diagram describing an implementation of pixel operation during a write cycle.

[0038] Figure 9 It is a circuit diagram used to describe an implementation of the operation of a pixel during the emission cycle within a frequency sweep period.

[0039] Figure 10 This is a circuit diagram used to describe an implementation of the operation of a pixel during the non-emission cycle within a frequency sweep period.

[0040] Figure 11 This is a block diagram illustrating an embodiment of the display device.

[0041] Figure 12This is a block diagram illustrating an embodiment of an electronic device including a display device. Detailed Implementation

[0042] In the following description, embodiments of the present invention will be detailed with reference to the accompanying drawings.

[0043] What will be understood is that when an element is referred to as being "on" another element, it can be directly on said other element, or there can be intervening elements between them. Conversely, when an element is referred to as being "directly" on another element, there are no intervening elements.

[0044] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms (including “at least one”) unless the context clearly indicates otherwise. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” or “containing” and / or “comprising” specify the presence of the described features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0046] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to also include different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” to the other element will be oriented to be “up” to the other element. Thus, the exemplary term “down” can include both “down” and “up” orientations, depending on the specific orientation of the drawing. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other element will be oriented to be “above” the other element. Thus, the exemplary term “below” or “under” can include both “up” and “down” orientations.

[0047] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the stated value and mean within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art. For example, a term such as “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0048] As used herein, terms such as “processor” and “controller” are intended to refer to hardware components such as circuitry that perform predetermined functions. Hardware components may include, for example, field-programmable gate arrays (“FPGAs”) or application-specific integrated circuits (“ASICs”).

[0049] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant technology and this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] Figure 1 This is a circuit diagram illustrating an embodiment of the pixels of a display device. Figure 2 The diagram illustrates an embodiment of the emitter current in a pixel in which the gate voltage of the pulse width modulation (“PWM”) driven transistor changes during a sweep cycle, and an embodiment of the emitter current in a pixel according to the present application. Figure 3The diagram illustrates an embodiment of the emitter current during the fall time duration in a pixel where a PWM signal is applied to the gate of a CCG driving transistor, with the CCG driving transistor having different threshold voltages, and an embodiment of the emitter current during the fall time duration in a pixel according to the present application, with the CCG driving transistor having different threshold voltages. Figure 4 The figure illustrates an embodiment of the current error rate based on the PWM data voltage in a pixel where a PWM signal is applied to the gate of the CCG driving transistor in the case of a shift in the threshold voltage of the CCG driving transistor, and an embodiment of the current error rate based on the PWM data voltage in a pixel according to the present application in the case of a shift in the threshold voltage of the CCG driving transistor.

[0051] refer to Figure 1 The pixel 100 of the display device in the embodiment may include a pulse width modulation (“PWM”) circuit 120, a constant current generation (“CCG”) circuit 140 and a light-emitting element EL. The pulse width modulation (“PWM”) circuit 120 generates a PWM signal SPWM based on the PWM data voltage DV_PWM and the sweep frequency voltage VSWEEP[n]. The constant current generation (“CCG”) circuit 140 generates an emission current based on the CCG data voltage DV_CCG and the PWM signal SPWM. The light-emitting element EL emits light based on the emission current.

[0052] CCG circuit 140 may include CCG driving transistor DT_CCG, a first capacitor C1, and a second capacitor C2. In some embodiments, CCG circuit 140 may also include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0053] The CCG driving transistor DT_CCG can generate an emission current based on the voltage stored by the first capacitor C1 and the second capacitor C2. In some embodiments, the CCG driving transistor DT_CCG may include a gate connected to the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2, a first terminal receiving a CCG high supply voltage (also referred to as the first CCG supply voltage) VDD_CCG having a relatively high power voltage level, and a second terminal connected to the light-emitting element EL through a fourth transistor T4.

[0054] A first capacitor C1 can be connected between the line transmitting the high CCG supply voltage VDD_CCG and the gate of the CCG driving transistor DT_CCG, and a second capacitor C2 can be connected between the gate of the CCG driving transistor DT_CCG and the node connected to the PWM circuit 120, the third transistor T3, and the fifth transistor T5. That is, the first capacitor C1 and the second capacitor C2 can be connected in series between the line transmitting the high CCG supply voltage VDD_CCG and the node. In a conventional pixel, the PWM signal SPWM of the PWM circuit 120 can be directly applied to the gate of the CCG driving transistor DT_CCG. However, in the pixel 100 of this embodiment, which includes the first capacitor C1 and the second capacitor C2, the PWM signal SPWM of the PWM circuit 120 can be applied to the second capacitor C2 and transmitted to the gate of the CCG driving transistor DT_CCG through the connection of the second capacitor C2. In some embodiments, the first capacitor C1 may include a first electrode receiving the high CCG supply voltage VDD_CCG and a second electrode connected to the gate of the CCG driving transistor DT_CCG. The second capacitor C2 may include a second electrode connected to the second electrode of the first capacitor C1 and the first electrode of the CCG driving transistor DT_CCG, and a second electrode that receives the PWM signal SPWM generated by the PWM circuit 120 and is connected to the third transistor T3, the fifth transistor T5 and the tenth transistor T10 of the PWM circuit 120.

[0055] The first transistor T1 can apply a reset voltage VRST to the gate of the CCG driving transistor DT_CCG in response to the first scan signal SCAN1. In some embodiments, for example, when the first scan signal SCAN1 has a relatively high level, the first transistor T1 can apply the reset voltage VRST to the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2. In some embodiments, the first transistor T1 may include a gate for receiving the first scan signal SCAN1, a first terminal for receiving the reset voltage VRST, and a second terminal connected to the gate of the CCG driving transistor DT_CCG, the second electrode of the first capacitor C1, and the first electrode of the second capacitor C2.

[0056] The second transistor T2 can be diode-connected to the CCG driving transistor DT_CCG in response to the second scan signal SCAN2. In some embodiments, for example, when the second scan signal SCAN2 has a relatively high level, the second transistor T2 can connect the gate of the CCG driving transistor DT_CCG and its second terminal (e.g., drain) to each other. In some embodiments, the second transistor T2 may include a gate receiving the second scan signal SCAN2, a first terminal connected to the second terminal of the CCG driving transistor DT_CCG, and a second terminal connected to the gate of the CCG driving transistor DT_CCG, the second electrode of the first capacitor C1, and the second electrode of the second capacitor C2.

[0057] The third transistor T3 can apply a CCG data voltage DV_CCG to the second electrode of the second capacitor C2 in response to a third scan signal SCAN3. In some embodiments, the CCG data voltage DV_CCG supplied to the plurality of pixels 100 included in the display device can be substantially the same voltage. Furthermore, for example, when the third scan signal SCAN3 has a relatively high level, the third transistor T3 can apply the CCG data voltage DV_CCG to the second electrode of the second capacitor C2. The CCG data voltage DV_CCG applied to the second electrode of the second capacitor C2 can be divided by the first capacitor C1 and the second capacitor C2, and the divided CCG data voltage DV_CCG can be applied to the gate of the CCG driving transistor DT_CCG. In some embodiments, the third transistor T3 may include a gate receiving the third scan signal SCAN3, a first terminal receiving the CCG data voltage DV_CCG, and a second terminal connected to the second electrode of the second capacitor C2.

[0058] In some implementations, the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 may be, but are not limited to, scan signals generated by the same shift register. Furthermore, when pixel 100 is arranged in the Nth pixel row (where N is an integer greater than or equal to 3), the third scan signal SCAN3 may be a write signal GW[n] for the Nth pixel row, the second scan signal SCAN2 may be a write signal GW[n-1] for the (N-1)th pixel row, and the first scan signal SCAN1 may be a write signal GW[n-2] for the (N-2)th pixel row, where n is an integer greater than or equal to 3.

[0059] The fourth transistor T4 can supply the light-emitting element EL with the emission current generated by the CCG driving transistor DT_CCG in response to the emission signal EM[n]. In some embodiments, for example, when the emission signal EM[n] has a relatively low level, the fourth transistor T4 can connect the CCG driving transistor DT_CCG to the light-emitting element EL. In some embodiments, the fourth transistor T4 may include a gate for receiving the emission signal EM[n], a first terminal connected to the second terminal of the CCG driving transistor DT_CCG, and a second terminal connected to the light-emitting element EL.

[0060] The fifth transistor T5 can apply a reference voltage VREF to the second electrode of the second capacitor C2 in response to the fourth scan signal SCAN4. In some embodiments, for example, when the fourth scan signal SCAN4 has a relatively high level, the fifth transistor T5 can apply the reference voltage VREF to the second electrode of the second capacitor C2. In some embodiments, the fifth transistor T5 may include a gate for receiving the fourth scan signal SCAN4, a first terminal connected to the second electrode of the second capacitor C2, and a second terminal for receiving the reference voltage VREF.

[0061] The sixth transistor T6 can initialize the light-emitting element EL in response to the first scan signal SCAN1. In one embodiment, for example, when the first scan signal SCAN1 has a relatively high level, the sixth transistor T6 can apply a CCG low supply voltage (also referred to as the second CCG supply voltage) VSS_CCG with a relatively low power supply voltage level to the anode of the light-emitting element EL. In some embodiments, the sixth transistor T6 may include a gate receiving the first scan signal SCAN1, a first terminal connected to the anode of the light-emitting element EL, and a second terminal receiving the CCG low supply voltage VSS_CCG.

[0062] The PWM circuit 120 may include a PWM drive transistor DT_PWM and a third capacitor C3. In some embodiments, the PWM circuit 120 may also include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11.

[0063] The PWM driving transistor DT_PWM can generate a PWM signal SPWM based on the voltage stored in the third capacitor C3 and the sweep voltage VSWEEP[n]. In an embodiment, for example, when the sweep voltage VSWEEP[n] is higher than the PWM data voltage DV_PWM, the PWM driving transistor DT_PWM can be turned on and can output the sweep voltage VSWEEP[n] as the PWM signal SPWM. In a conventional pixel, the PWM driving transistor DT_PWM can receive the sweep voltage VSWEEP[n] at its gate. However, in pixel 100 of the embodiment, the PWM driving transistor DT_PWM can receive the sweep voltage VSWEEP[n] at its first terminal (e.g., the source). In some embodiments, the PWM driving transistor DT_PWM may include a gate connected to the second electrode of the third capacitor C3, a first terminal receiving the sweep voltage VSWEEP[n] through the seventh transistor T7, and a second terminal outputting the PWM signal SPWM.

[0064] A third capacitor C3 may be connected between the line transmitting the PWM power supply voltage VDD_PWM and the gate of the PWM drive transistor DT_PWM. In some embodiments, the third capacitor C3 may include a first electrode receiving the PWM power supply voltage VDD_PWM and a second electrode connected to the gate of the PWM drive transistor DT_PWM. Since the first electrode of the third capacitor C3 receives the PWM power supply voltage VDD_PWM with a substantially constant voltage level instead of the sweep voltage VSWEEP[n], the voltage at the second electrode of the third capacitor C3 or the voltage at the gate of the PWM drive transistor DT_PWM may remain substantially constant during a sweep cycle in which the sweep voltage VSWEEP[n] gradually changes (e.g., increases).

[0065] The seventh transistor T7 can apply a sweep voltage VSWEEP[n] to the first terminal of the PWM drive transistor DT_PWM in response to the transmit signal EM[n]. In some embodiments, for example, when the transmit signal EM[n] has a relatively low level, the seventh transistor T7 can connect the line transmitting the sweep voltage VSWEEP[n] and the first terminal of the PWM drive transistor DT_PWM to each other. In some embodiments, the seventh transistor T7 may include a gate for receiving the transmit signal EM[n], a first terminal for receiving the sweep voltage VSWEEP[n], and a second terminal connected to the first terminal of the PWM drive transistor DT_PWM.

[0066] The eighth transistor T8 can apply a PWM data voltage DV_PWM to the first terminal of the PWM drive transistor DT_PWM in response to the second scan signal SCAN2. In some embodiments, the voltage level of the PWM data voltage DV_PWM supplied to each pixel 100 can be determined based on image data for pixel 100. Furthermore, the duration of the transmission cycle within the sweep period can be determined based on the voltage level of the PWM data voltage DV_PWM, and the brightness of pixel 100 can be determined based on the duration of the transmission cycle. That is, pixel 100 can be driven using a PWM method that controls the duration of the transmission cycle, and the duration of the transmission cycle can be adjusted by adjusting the voltage level of the PWM data voltage DV_PWM. Furthermore, in some embodiments, the eighth transistor T8 may include a gate for receiving the second scan signal SCAN2, a first terminal for receiving the PWM data voltage DV_PWM, and a second terminal connected to the first terminal of the PWM drive transistor DT_PWM.

[0067] The ninth transistor T9 can be diode-connected to the PWM drive transistor DT_PWM in response to the second scan signal SCAN2. In one embodiment, for example, when the second scan signal SCAN2 has a relatively high level, the ninth transistor T9 can connect the gate of the PWM drive transistor DT_PWM and its second terminal (e.g., drain) to each other. In some embodiments, the ninth transistor T9 may include a gate receiving the second scan signal SCAN2, a first terminal connected to the second terminal of the PWM drive transistor DT_PWM, and a second terminal connected to the gate of the PWM drive transistor DT_PWM and the second electrode of the third capacitor C3.

[0068] The tenth transistor T10 can apply a PWM signal SPWM generated by the PWM drive transistor DT_PWM to the CCG circuit 140 in response to the fourth scan signal SCAN4. In one embodiment, for example, when the fourth scan signal SCAN4 has a relatively low level, the tenth transistor T10 can connect the second terminal of the PWM drive transistor DT_PWM to the second electrode of the second capacitor C2. In some embodiments, the tenth transistor T10 may include a gate receiving the fourth scan signal SCAN4, a first terminal connected to the second terminal of the PWM drive transistor DT_PWM, and a second terminal connected to the second electrode of the second capacitor C2 in the CCG circuit 140.

[0069] The eleventh transistor T11 can apply a reset voltage VRST to the second electrode of the third capacitor C3 in response to the first scan signal SCAN1. In some embodiments, for example, when the first scan signal SCAN1 has a relatively high level, the eleventh transistor T11 can apply the reset voltage VRST to the second electrode of the third capacitor C3. In some embodiments, the eleventh transistor T11 may include a gate for receiving the first scan signal SCAN1, a first terminal connected to the second electrode of the third capacitor C3, and a second terminal for receiving the reset voltage VRST.

[0070] The light-emitting element EL can emit light based on the emission current generated by the CCG driving transistor DT_CCG. In some embodiments, the light-emitting element EL can be, but is not limited to, a micron-sized light-emitting diode (“μLED”). In other embodiments, the light-emitting element EL can be an organic light-emitting diode (“OLED”). In still other embodiments, the light-emitting element EL can be a nano-sized light-emitting diode (“NED”), a quantum dot (“QD”) light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. Furthermore, in some embodiments, the light-emitting element EL may include an anode connected to the second terminal of the fourth transistor T4 and the first terminal of the sixth transistor T6, and a cathode receiving the low supply voltage VSS_CCG of the CCG.

[0071] In some implementations, such as Figure 1 As shown, the CCG driving transistor DT_CCG, the PWM driving transistor DT_PWM, and the fourth transistor T4, the seventh transistor T7, and the tenth transistor T10 can be P-type transistors, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 can be N-type transistors. In some embodiments, for example, the CCG driving transistor DT_CCG, the PWM driving transistor DT_PWM, and the fourth transistor T4, the seventh transistor T7, and the tenth transistor T10 can be, but are not limited to, P-type low-temperature polycrystalline silicon (“LTPS”) thin-film transistors, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 can be, but are not limited to, N-type amorphous indium gallium zinc oxide (“a-IGZO”) thin-film transistors. In other embodiments, all transistors can be P-type transistors. In still other embodiments, all transistors can be N-type transistors. In other embodiments, some of the transistors may be P-type transistors, and the remaining transistors may be N-type transistors.

[0072] In a typical pixel, the gate of the PWM driving transistor DT_PWM receives the sweep voltage VSWEEP[n] via the third capacitor C3. In this case, during the sweep cycle, the voltage of the gate of the PWM driving transistor DT_PWM gradually changes, and the voltage of the second terminal (e.g., the drain) of the PWM driving transistor DT_PWM may also change due to the parasitic capacitance between the gate and the second terminal of the PWM driving transistor DT_PWM. Furthermore, when the voltage of the second terminal of the PWM driving transistor DT_PWM changes, the voltage of the gate of the CCG driving transistor DT_CCG changes via the tenth transistor T10 and the second capacitor C2, and the emitter current IEL generated by the CCG driving transistor DT_CCG (see...) Figure 2 It may be distorted. In regular pixels, for example, such as... Figure 2 As shown in Figure 160, the emission current IEL generated by the CCG driving transistor DT_CCG may gradually increase from the desired target current TI. In this case, the luminous efficiency of the light-emitting element EL may decrease, the color coordinates of pixel 100 may be distorted, and color shift may occur in the display device.

[0073] However, in pixel 100 of the embodiment, the first terminal (e.g., the source) of the PWM driving transistor DT_PWM can receive the sweep voltage VSWEEP[n] through the seventh transistor T7, and the gate of the PWM driving transistor DT_PWM can receive the PWM power supply voltage VDD_PWM with a substantially constant voltage level through the third capacitor C3. Therefore, even when the sweep voltage VSWEEP[n] gradually changes (e.g., increases) during the sweep cycle, the voltage at the gate of the PWM driving transistor DT_PWM can remain substantially constant. Therefore, the emitter current IEL generated by the CCG driving transistor DT_CCG can be undistorted. In the embodiment, as Figure 2 As shown in the second figure 180, for example, the emission current IEL generated by the CCG driving transistor DT_CCG can be maintained at the desired target current TI (until the PWM driving transistor DT_PWM is turned on). Therefore, the luminous efficiency of the light-emitting element EL can be maintained, the color coordinates of the pixel 100 can be undistorted, and color shift can be avoided in the display device.

[0074] In pixel 100, when the sweep voltage VSWEEP[n] is higher than the PWM data voltage DV_PWM, the PWM circuit 120 can apply the PWM signal SPWM to the CCG circuit 140, and the CCG driving transistor DT_CCG can be turned off in response to the PWM signal SPWM. Ideally, when the sweep voltage VSWEEP[n] becomes higher than the PWM data voltage DV_PWM, the CCG driving transistor DT_CCG immediately turns off, and the emission current IEL generated by the CCG driving transistor DT_CCG can decrease rapidly. However, in reality, when the sweep voltage VSWEEP[n] becomes higher than the PWM data voltage DV_PWM, the CCG driving transistor DT_CCG changes from the on state to the off state within a predetermined time period, and the emission current IEL can decrease within the predetermined time period. That is, when the sweep voltage VSWEEP[n] becomes higher than the PWM data voltage DV_PWM, the emission current IEL can decrease from the desired target current TI within the fall time.

[0075] Furthermore, in a conventional pixel, the PWM signal SPWM generated by the PWM circuit 120 can be directly applied to the gate of the CCG driving transistor DT_CCG. In a conventional display device where the CCG driving transistors DT_CCG of multiple conventional pixels have different threshold voltages, since the PWM signal SPWM, which is independent of the threshold voltage of the CCG driving transistor DT_CCG, is applied to the gate of the CCG driving transistor DT_CCG of each conventional pixel, multiple conventional pixels may emit light with different brightness during the fall time duration. Figure 3 The following diagram illustrates the emission current 210 during the fall time duration in a conventional pixel where the threshold voltage of the CCG driving transistor DT_CCG is not offset, the emission current 220 during the fall time duration in a conventional pixel where the threshold voltage of the CCG driving transistor DT_CCG is offset in the positive direction, and the emission current 230 during the fall time duration in a conventional pixel where the threshold voltage of the CCG driving transistor DT_CCG is offset in the negative direction. Figure 3 As shown, a conventional pixel including a CCG driving transistor DT_CCG with different threshold voltages may generate different emission currents 210, 220 and 230 during the fall time duration, and may emit light with different brightness based on the different emission currents 210, 220 and 230.

[0076] However, in pixel 100 of the embodiment, the PWM signal SPWM generated by PWM circuit 120 can be applied to the second electrode of second capacitor C2 and transmitted to the gate of CCG driving transistor DT_CCG through the connection of second capacitor C2. Therefore, when CCG driving transistor DT_CCG changes from the on state to the off state, or during the fall time in which the emission current IEL decreases, the second capacitor C2 of each pixel 100 can substantially maintain the voltage reflected by the threshold voltage of CCG driving transistor DT_CCG, and thus the threshold voltage of CCG driving transistor DT_CCG can be reflected in the voltage of the gate of CCG driving transistor DT_CCG of each pixel 100. Therefore, even when the CCG driving transistors DT_CCG of multiple pixels 100 of the display device in the embodiment have different threshold voltages, multiple pixels 100 can emit light with substantially constant brightness during the fall time. Figure 3 The following diagram illustrates the emission current 260 during the fall time duration in pixel 100 where the threshold voltage of the CCG driving transistor DT_CCG is not offset, the emission current 270 during the fall time duration in pixel 100 where the threshold voltage of the CCG driving transistor DT_CCG is offset in the positive direction, and the emission current 280 during the fall time duration in pixel 100 where the threshold voltage of the CCG driving transistor DT_CCG is offset in the negative direction. Figure 3 As shown, even when the CCG driving transistor DT_CCG has different threshold voltages, the pixel 100 in the embodiment can generate emission currents 260, 270, and 280 with smaller differences than the emission currents 210, 220, and 230 of conventional pixels during the fall time duration, and can emit light with substantially constant brightness based on the emission currents 260, 270, and 280 with smaller differences. Therefore, the image quality of the display device in the embodiment can be improved.

[0077] Figure 4The diagram illustrates the current error rate 310 for the emitter current IEL of the PWM data voltage DV_PWM in a regular pixel where the absolute value of the threshold voltage of the CCG driving transistor DT_CCG increases by approximately 0.5 volts (V); the current error rate 330 for the emitter current IEL of the PWM data voltage DV_PWM in a regular pixel where the absolute value of the threshold voltage of the CCG driving transistor DT_CCG decreases by approximately 0.5V; the current error rate 360 ​​for the emitter current IEL of the PWM data voltage DV_PWM in a pixel 100 where the absolute value of the threshold voltage of the CCG driving transistor DT_CCG increases by approximately 0.5V; and the current error rate 380 for the emitter current IEL of the PWM data voltage DV_PWM in a pixel 100 where the absolute value of the threshold voltage of the CCG driving transistor DT_CCG decreases by approximately 0.5V. Figure 4 As shown, in a conventional pixel, when the threshold voltage of the CCG driving transistor DT_CCG increases or decreases by about 0.5V, the emission current IEL can increase or decrease by about 30%, and therefore the brightness of the conventional pixel can increase or decrease by about 30%. However, in pixel 100 of the embodiment, when the threshold voltage of the CCG driving transistor DT_CCG increases or decreases by about 0.5V, the emission current IEL can increase or decrease by about 10%, and therefore the brightness of pixel 100 can increase or decrease by about 10%. Therefore, the image quality of the display device including pixel 100 of the embodiment can be improved.

[0078] As described above, in pixel 100 of the embodiment, the PWM driving transistor DT_PWM can receive the sweep voltage VSWEEP[n] at a first terminal (e.g., the source). Therefore, during the sweep cycle in which the sweep voltage VSWEEP[n] gradually changes, the voltage at the gate of the PWM driving transistor DT_PWM can be substantially constant. Therefore, when the CCG driving transistor DT_CCG generates the emitter current IEL, the voltage at the gate of the CCG driving transistor DT_CCG can be undistorted by the sweep voltage VSWEEP[n], and the emitter current IEL can have a current level substantially equal to the desired target current TI. Furthermore, in pixel 100 of the embodiment, the CCG circuit 140 can include a first capacitor C1 and a second capacitor C2 connected to the gate of the CCG driving transistor DT_CCG, and the PWM signal SPWM generated by the PWM circuit 120 can be transmitted to the gate of the CCG driving transistor DT_CCG through the connection of the second capacitor C2. Therefore, when the CCG driving transistor DT_CCG changes from the on state to the off state, or during the fall time during which the emission current IEL decreases, the voltage stored in the second capacitor C2, or the voltage reflected by the threshold voltage of the CCG driving transistor DT_CCG, can be substantially maintained. Thus, even when the emission current IEL decreases, the threshold voltage deviation between the CCG driving transistors DT_CCG of the multiple pixels 100 can be compensated, and the image quality of the display device can be improved.

[0079] In the following text, see below for reference. Figure 1 and Figures 5 to 10 The operation of pixel 100 in the implementation method is described.

[0080] Figure 5 It is a timing diagram used to describe the implementation of pixel operations. Figure 6 This is a circuit diagram describing an implementation of pixel operation during the initialization cycle. Figure 7 This is a circuit diagram describing an implementation of pixel operation during a compensation period. Figure 8 This is a circuit diagram describing an implementation of pixel operation during a write cycle. Figure 9 This is a circuit diagram describing an implementation of the operation of a pixel during its emission cycle within a frequency sweep period, and... Figure 10 This is a circuit diagram describing an implementation of the operation of a pixel during the non-emission cycle within a frequency sweep period.

[0081] refer to Figure 1 and Figure 5The frame period FP of pixel 100 may include: an initialization period IP, in which the first capacitor C1, the second capacitor C2, the third capacitor C3, and the parasitic capacitance of the light-emitting element EL are initialized; a compensation period CP, in which the PWM data voltage DV_PWM is provided to the PWM circuit 120, the threshold voltage of the PWM driving transistor DT_PWM is compensated, and the threshold voltage of the CCG driving transistor DT_CCG is compensated; a write period WP, ​​in which the CCG data voltage DV_CCG is provided to the CCG circuit 140; and a sweep period SP, in which the sweep voltage VSWEEP[n] is gradually changed (e.g., increased). In some embodiments, the sweep period SP may include a transmit period EP and a non-transmit period NEP, in which the sweep voltage VSWEEP[n] is lower than the PWM data voltage DV_PWM and the light-emitting element EL emits light, and in the non-transmit period NEP, the sweep voltage VSWEEP[n] is higher than the PWM data voltage DV_PWM and the light-emitting element EL does not emit light.

[0082] During the initialization cycle IP, the first scan signal SCAN1, the fourth scan signal SCAN4, and the transmit signal EM[n] can have relatively high levels, while the second scan signal SCAN2 and the third scan signal SCAN3 can have relatively low levels. In an implementation, for example, as... Figure 6As shown, the first transistor T1 can be turned on in response to the first scan signal SCAN1, the fifth transistor T5 can be turned on in response to the fourth scan signal SCAN4, the sixth transistor T6 can be turned on in response to the first scan signal SCAN1, and the eleventh transistor T11 can be turned on in response to the first scan signal SCAN1. The first transistor T1 can apply a reset voltage VRST to the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2, and the fifth transistor T5 can apply a reference voltage VREF to the second electrode of the second capacitor C2. Therefore, the first capacitor C1 can be initialized based on the CCG high supply voltage VDD_CCG and the reset voltage VRST, and the second capacitor C2 can be initialized based on the reset voltage VRST and the reference voltage VREF. The eleventh transistor T11 can apply the reset voltage VRST to the second electrode of the third capacitor C3, and therefore the third capacitor C3 can be initialized based on the PWM supply voltage VDD_PWM and the reset voltage VRST. Furthermore, the sixth transistor T6 can apply the low CCG supply voltage VSS_CCG to the anode of the light-emitting element EL, and thus the parasitic capacitance of the light-emitting element EL can be initialized based on the low CCG supply voltage VSS_CCG. The second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be turned off.

[0083] During the compensation period CP, the second scan signal SCAN2, the fourth scan signal SCAN4, and the transmit signal EM[n] can have relatively high levels, while the first scan signal SCAN1 and the third scan signal SCAN3 can have relatively low levels. In the implementation, as... Figure 7As shown, for example, the second transistor T2 can be turned on in response to the second scan signal SCAN2, the fifth transistor T5 can be turned on in response to the fourth scan signal SCAN4, the eighth transistor T8 can be turned on in response to the second scan signal SCAN2, and the ninth transistor T9 can be turned on in response to the second scan signal SCAN2. The second transistor T2 can be diode-connected to the CCG driving transistor DT_CCG, and the voltage at the gate of the CCG driving transistor DT_CCG can be changed to a voltage VDD_CCG-VTH_CCG obtained by subtracting the threshold voltage VTH_CCG of the CCG driving transistor DT_CCG from the high supply voltage VDD_CCG of the CCG. Therefore, the first capacitor C1 and the second capacitor C2 can store the voltage in which the threshold voltage VTH_CCG of the CCG driving transistor DT_CCG is compensated. Furthermore, the eighth transistor T8 can apply the PWM data voltage DV_PWM to the first terminal of the PWM drive transistor DT_PWM, and the ninth transistor T9 can be diode-connected to the PWM drive transistor DT_PWM. Therefore, the gate voltage of the PWM drive transistor DT_PWM can be changed to a voltage DV_PWM - VTH_PWM obtained by subtracting the threshold voltage VTH_PWM of the PWM drive transistor DT_PWM from the PWM data voltage DV_PWM. Thus, the third capacitor C3 can store the voltage in which the threshold voltage VTH_PWM of the PWM drive transistor DT_PWM is compensated. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 can be turned off.

[0084] During the write cycle WP, the third scan signal SCAN3 and the transmit signal EM[n] can have relatively high levels, while the first scan signal SCAN1, the second scan signal SCAN2, and the fourth scan signal SCAN4 can have relatively low levels. In the implementation, as... Figure 8As shown, for example, the third transistor T3 can be turned on in response to the third scan signal SCAN3, and the tenth transistor T10 can be turned on in response to the fourth scan signal SCAN4. Even when the tenth transistor T10 is turned on, since the seventh transistor T7 and the ninth transistor T9 are turned off, the tenth transistor T10 does not affect the voltage of the second electrode of the second capacitor C2. The third transistor T3 can apply the CCG data voltage DV_CCG to the second electrode of the second capacitor C2, and the voltage of the second electrode of the second capacitor C2 can be changed from the reference voltage VREF to the CCG data voltage DV_CCG by the voltage difference DV_CCG-VREF between the CCG data voltage DV_CCG and the reference voltage VREF. In addition, through the first capacitor C1 and the second capacitor C2 connected in series, the gate voltage of the CCG driving transistor DT_CCG can become "VDD_CCG-VTH_CCG+(DV_CCG-VREF)×C2 / (C1+C2)". The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 can be turned off.

[0085] During the sweep cycle SP, the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and the transmit signal EM[n] can have relatively low levels, and the sweep voltage VSWEEP[n] can gradually increase. During the sweep cycle SP, the fourth transistor T4 and the seventh transistor T7 can be turned on in response to the transmit signal EM[n], the tenth transistor T10 can be turned on in response to the fourth scan signal SCAN4, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 can be turned off.

[0086] Furthermore, during the transmit cycle EP where the sweep frequency voltage VSWEEP[n] is lower than the PWM data voltage DV_PWM, such as Figure 9As shown, the PWM driving transistor DT_PWM can be turned off. In an embodiment, the gate voltage of the PWM driving transistor DT_PWM can be "DV_PWM-VTH_PWM", and therefore the source-gate voltage of the PWM driving transistor DT_PWM can be, for example, "VSWEEP[n]-DV_PWM+VTH_PWM". Therefore, when the sweep voltage VSWEEP[n] is lower than the PWM data voltage DV_PWM, the source-gate voltage of the PWM driving transistor DT_PWM can be lower than the threshold voltage VTH_PWM of the PWM driving transistor DT_PWM, and the PWM driving transistor DT_PWM can be turned off. Furthermore, since the gate voltage of the CCG driving transistor DT_CCG is "VDD_CCG-VTH_CCG+(DV_CCG-VREF)×C2 / (C1+C2)", the voltage stored between the first and second electrodes of the first capacitor C1 or the source-gate voltage of the CCG driving transistor DT_CCG can be "VTH_CCG-(DV_CCG-VREF)×C2 / (C1+C2)". Therefore, the CCG driving transistor DT_CCG can generate an emitter current IEL corresponding to “(DV_CCG-VREF)×C2 / (C1+C2)”, which is independent of the threshold voltage VTH_CCG of the CCG driving transistor DT_CCG.

[0087] The PWM driving transistor DT_PWM can receive the sweep voltage VSWEEP[n] at its first terminal (e.g., the source). Therefore, during the sweep period SP, the gate voltage of the PWM driving transistor DT_PWM can be substantially constant. Thus, when the CCG driving transistor DT_CCG generates the emitter current IEL, the gate voltage of the CCG driving transistor DT_CCG can be undistorted by the sweep voltage VSWEEP[n], and the emitter current IEL can have a value substantially equal to the desired target current TI (reference). Figure 2 The current level of ).

[0088] When the sweep voltage VSWEEP[n] becomes higher than the PWM data voltage DV_PWM, or during the non-emitter period NEP in which the sweep voltage VSWEEP[n] is higher than the PWM data voltage DV_PWM, such as Figure 10As shown, the PWM driving transistor DT_PWM can be turned on. In an implementation, for example, when the sweep voltage VSWEEP[n] is higher than the PWM data voltage DV_PWM, the source-gate voltage of the PWM driving transistor DT_PWM can be higher than the threshold voltage VTH_PWM of the PWM driving transistor DT_PWM, and the PWM driving transistor DT_PWM can be turned on. Therefore, the PWM driving transistor DT_PWM can output the sweep voltage VSWEEP[n] as the PWM signal SPWM, and the tenth transistor T10 can apply the sweep voltage VSWEEP[n] as the PWM signal SPWM to the second electrode of the second capacitor C2. The sweep voltage VSWEEP[n] applied to the second electrode of the second capacitor C2 can be transmitted to the gate of the CCG driving transistor DT_CCG through the connection of the second capacitor C2. Therefore, the CCG driving transistor DT_CCG can be turned off based on the sweep voltage VSWEEP[n] applied to the gate of the CCG driving transistor DT_CCG, the emission current IEL can not be provided to the light-emitting element EL, and the light-emitting element EL can not emit light. In other words, the CCG circuit 140 can start generating the emission current IEL at the beginning of the sweep cycle SP, and can stop generating the emission current IEL in response to the sweep voltage VSWEEP[n].

[0089] However, when the sweep voltage VSWEEP[n] becomes higher than the PWM data voltage DV_PWM, ideally the CCG driving transistor DT_CCG could be immediately turned off, but in reality, the CCG driving transistor DT_CCG can change from the on state to the off state within a predetermined time period. In the pixel 100 of the embodiment, when the CCG driving transistor DT_CCG changes from the on state to the off state, or during the fall time in which the emitter current IEL decreases, the voltage stored in the second capacitor C2 or the voltage reflected by the threshold voltage VTH_CCG of the CCG driving transistor DT_CCG can be substantially maintained. Therefore, even when the emitter current IEL decreases, the threshold voltage deviation between the CCG driving transistors DT_CCG of the plurality of pixels 100 can be compensated, and the image quality of the display device can be improved.

[0090] Figure 11 This is a block diagram illustrating an embodiment of the display device.

[0091] refer to Figure 11The display device 400 in the embodiment may include: a display panel 410 including a plurality of pixels PX; a scan driver 420 providing scan signals SCAN1, SCAN2, SCAN3 and SCAN4 to each of the plurality of pixels PX; a transmit driver 430 providing a transmit signal EM[n] to each of the plurality of pixels PX; a sweep driver 440 providing a sweep voltage VSWEEP[n] to each of the plurality of pixels PX; a data driver 450 providing a PWM data voltage DV_PWM and a CCG data voltage DV_CCG to each of the plurality of pixels PX; and a controller 460 controlling the scan driver 420, the transmit driver 430, the sweep driver 440 and the data driver 450.

[0092] The display panel 410 may include multiple PWM data lines, multiple CCG data lines, multiple scan lines, multiple emitter lines, and multiple pixels PX connected to the multiple PWM data lines, multiple CCG data lines, multiple scan lines, and multiple emitter lines. Each pixel PX can be Figure 1 Pixel 100, etc., are shown in the diagram. In each pixel PX, a PWM drive transistor (e.g., Figure 1 The DT_PWM in the PWM drive transistor can receive the swept voltage VSWEEP[n] at the terminal (e.g., the source) of the PWM drive transistor. Therefore, the CCG drive transistor (e.g., Figure 1 The gate voltage of the DT_CCG (in the image) can be kept undistorted by the sweep voltage VSWEEP[n], and the CCG driving transistor can generate an emitter current with the desired target current level. Furthermore, the CCG circuit of each pixel PX can include a first capacitor and a second capacitor connected to the gate of the CCG driving transistor, and the PWM signal can be transmitted to the gate of the CCG driving transistor via the connection of the second capacitor. Therefore, even when the emitter current decreases, the threshold voltage deviation between the CCG driving transistors of multiple pixels PX can be compensated, and the image quality of the display device 400 can be improved.

[0093] The scan driver 420 can sequentially provide scan signals SCAN1, SCAN2, SCAN3, and SCAN4 to multiple pixels PX on a line-by-line basis based on the scan control signal SCTRL received from the controller 460. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. The scan driver 420 may include at least one shift register that sequentially generates the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, and the fourth scan signal SCAN4. In some embodiments, the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 may be generated, but is not limited to, by a single shift register. Furthermore, in some embodiments, the scan driver 420 may be integrated or formed in the display panel 410. In other embodiments, the scan driver 420 may be implemented using one or more integrated circuits.

[0094] The transmit driver 430 can sequentially provide transmit signals EM[n] to multiple pixels PX on a row-by-row basis based on the transmit control signal EMCTRL received from the controller 460. In some embodiments, the transmit control signal EMCTRL may include, but is not limited to, a transmit start signal and a transmit clock signal. Furthermore, in some embodiments, the transmit driver 430 may be integrated or formed in the display panel 410. In other embodiments, the transmit driver 430 may be implemented using one or more integrated circuits.

[0095] The sweep driver 440 can sequentially provide sweep voltage VSWEEP[n] to multiple pixels PX on a row-by-row basis based on the sweep control signal SWPCTRL received from the controller 460. In some embodiments, the sweep voltage VSWEEP[n] can be gradually increased during the sweep cycle. Furthermore, in some embodiments, the sweep driver 440 can be integrated or formed in the display panel 410. In other embodiments, the sweep driver 440 can be implemented using one or more integrated circuits.

[0096] Data driver 450 can receive data control signal DCTRL and output image data ODAT from controller 460, and can provide PWM data voltage DV_PWM to multiple pixels PX based on the output image data ODAT, and can provide substantially the same CCG data voltage DV_CCG to multiple pixels PX. In some embodiments, the voltage level of the PWM data voltage DV_PWM for each pixel PX can be determined based on the gray level indicated by the output image data ODAT for the pixel PX. Furthermore, in some embodiments, data driver 450 can provide substantially the same CCG data voltage DV_CCG to multiple pixels PX. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. Furthermore, in some embodiments, data driver 450 and controller 460 can be implemented as a single integrated circuit, and this single integrated circuit may be referred to as a timing controller embedded data driver (“TED”) integrated circuit. In other embodiments, data driver 450 and controller 460 can be implemented as separate integrated circuits.

[0097] Controller 460 (e.g., a timing controller) can receive input image data IDAT and control signals CTRL from an external host processor (e.g., a graphics processing unit (“GPU”), application processor (“AP”), or graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 460 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, a transmit control signal EMCTRL, and a sweep frequency control signal SWPCTRL based on the input image data IDAT and the control signal CTRL. Controller 460 can control data driver 450 by providing output image data ODAT and data control signal DCTRL to data driver 450, control scan driver 420 by providing scan control signal SCTRL to scan driver 420, control transmit driver 430 by providing transmit control signal EMCTRL to transmit driver 430, and control sweep frequency driver 440 by providing sweep frequency control signal SWPCTRL to sweep frequency driver 440.

[0098] Figure 12 This is a block diagram illustrating an embodiment of an electronic device including a display device.

[0099] refer to Figure 12Electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (“I / O”) device 1140, a power supply 1150, and a display device 1160. Electronic device 1100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electronic devices, etc.

[0100] Processor 1110 can perform various computing functions or tasks. Processor 1110 can be an application processor (“AP”), a microprocessor, a central processing unit (“CPU”), etc. Processor 1110 can be connected to other components via address buses, control buses, data buses, etc. In addition, in some embodiments, processor 1110 can also be connected to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0101] The memory device 1120 can store data for the operation of the electronic device 1100. In embodiments, for example, the memory device 1120 may include at least one non-volatile memory device and / or at least one volatile memory device. The at least one non-volatile memory device is such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc. The at least one volatile memory device is such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (“mobile DRAM”) device, etc.

[0102] Storage device 1130 may be a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, an optical disc read-only memory (“CD-ROM”) device, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 provides power for the operation of electronic device 1100. Display device 1160 can be connected to other components via a bus or other communication link.

[0103] In each pixel of the display device 1160, the PWM driving transistor can receive a sweep voltage at its terminal (e.g., the source). Therefore, during a sweep cycle in which the sweep voltage gradually changes, the voltage at the gate of the PWM driving transistor can be substantially constant. Thus, when the CCG driving transistor generates an emission current, the voltage at the gate of the CCG driving transistor can be undistorted by the sweep voltage, and the emission current can have a desired target current level. Furthermore, in each pixel of the display device 1160, the CCG circuitry can include a first capacitor and a second capacitor connected to the gate of the CCG driving transistor, and the PWM signal can be transmitted to the gate of the CCG driving transistor via the connection of the second capacitor. Therefore, when the CCG driving transistor changes from an on state to an off state, or during the fall time in which the emission current decreases, the voltage stored in the second capacitor, or the voltage reflected by the threshold voltage of the CCG driving transistor, can be substantially maintained. Therefore, even when the emission current decreases, threshold voltage deviations between the CCG driving transistors of multiple pixels can be compensated, and the image quality of the display device 1160 can be improved.

[0104] This inventive concept can be applied to any electronic device 1100 including the display device 1160. In embodiments, this inventive concept can be applied to, for example, mobile phones, smartphones, virtual reality (“VR”) devices, televisions (“TV”) (e.g., digital TV, 3D TV, etc.), wearable electronic devices, personal computers (“PC”) (e.g., laptop computers, tablet computers, etc.), home appliances, personal digital assistants (“PDAs”), portable multimedia players (“PMPs”), digital cameras, music players, portable game consoles, navigation devices, etc.

[0105] The foregoing description is illustrative of embodiments and should not be construed as limiting the embodiments. Although several embodiments have been described, those skilled in the art will readily understand that many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. It will therefore be understood that the foregoing description is illustrative of various embodiments and should not be construed as limiting oneself to the disclosed exemplary embodiments, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A pixel of a display device, characterized in that, The pixels include: A pulse width modulation circuit is configured to generate a pulse width modulation signal based on pulse width modulation data voltage and sweep frequency voltage. A constant current generating circuit is configured to generate a transmit current based on a constant current generating a data voltage and the pulse width modulation signal, the constant current generating circuit comprising: A constant current generating drive transistor is configured to generate the emitter current; The first capacitor includes: The first electrode receives a first constant current with a high power voltage level to generate a power supply voltage; and The second electrode is connected to the gate of the constant current generating drive transistor; and The second capacitor includes: A first electrode is connected to the gate of the constant current generating drive transistor; and The second electrode receives the pulse width modulation signal generated by the pulse width modulation circuit; and The light-emitting element is configured to emit light based on the emission current.

2. The pixel according to claim 1, characterized in that, The sweep voltage gradually increases during the sweep cycle. Specifically, when the sweep voltage is higher than the pulse width modulation data voltage, the pulse width modulation circuit applies the sweep voltage as the pulse width modulation signal to the constant current generation circuit. The constant current generating circuit starts generating the transmission current at the beginning of the frequency sweep cycle and stops generating the transmission current in response to the frequency sweep voltage.

3. The pixel according to claim 2, characterized in that, The sweep voltage applied to the constant current generating circuit is transmitted to the gate of the constant current generating drive transistor via the connection of the second capacitor.

4. The pixel according to claim 1, characterized in that, The constant current generating drive transistor includes a second electrode connected to the first capacitor and the gate of the first electrode of the second capacitor, a first terminal receiving the power supply voltage generated by the first constant current, and a second terminal connected to the light-emitting element.

5. The pixel according to claim 4, characterized in that, The constant current generating circuit also includes: The first transistor is configured to apply a reset voltage to the gate of the constant current generating drive transistor in response to a first scan signal; The second transistor is configured to diode-connect the constant current generating drive transistor in response to the second scan signal; and A third transistor is configured to generate a data voltage from the constant current and apply it to the second electrode of the second capacitor in response to a third scan signal.

6. The pixel according to claim 5, characterized in that, The third scan signal is a write signal for the Nth pixel row in which the pixels are arranged, where N is an integer greater than or equal to 3. Wherein, the second scan signal is the write signal for the (N-1)th pixel row, and The first scan signal is a write signal for the (N-2)th pixel row.

7. The pixel according to claim 5, characterized in that, The constant current generating circuit also includes: A fourth transistor is configured to provide the light-emitting element with the emission current generated by the constant current generating drive transistor in response to an emission signal; A fifth transistor is configured to apply a reference voltage to the second electrode of the second capacitor in response to a fourth scan signal; and A sixth transistor is configured to initialize the light-emitting element in response to the first scan signal.

8. The pixel according to claim 1, characterized in that, The pulse width modulation circuit includes: The third capacitor includes a first electrode and a second electrode for receiving pulse width modulation power supply voltage; A pulse width modulation driving transistor includes a gate connected to the second electrode of the third capacitor, a first terminal for receiving the swept voltage, and a second terminal for outputting the pulse width modulation signal; A seventh transistor is configured to apply the sweep voltage to the first terminal of the pulse width modulation drive transistor in response to a transmit signal; The eighth transistor is configured to apply the pulse width modulation data voltage to the first terminal of the pulse width modulation driving transistor in response to the second scan signal; The ninth transistor is configured to be diode-connected to the pulse width modulation drive transistor in response to the second scan signal; The tenth transistor is configured to apply the pulse width modulation signal generated by the pulse width modulation drive transistor to the constant current generating circuit in response to the fourth scan signal; and The eleventh transistor is configured to apply a reset voltage to the second electrode of the third capacitor in response to a first scan signal.

9. A display device, characterized in that, include: A display panel includes a plurality of pixels, each of the plurality of pixels comprising: A pulse width modulation circuit is configured to generate a pulse width modulation signal based on pulse width modulation data voltage and sweep frequency voltage. A constant current generating circuit is configured to generate a transmit current based on a constant current generating a data voltage and the pulse width modulation signal, the constant current generating circuit comprising: A constant current generating drive transistor is configured to generate the emitter current; A first capacitor includes a first electrode receiving a first constant current generating power supply voltage having a high power voltage level and a second electrode connected to the gate of the constant current generating drive transistor; and The second capacitor includes a first electrode connected to the gate of the constant current generating drive transistor and a second electrode receiving the pulse width modulation signal generated by the pulse width modulation circuit; and A light-emitting element configured to emit light based on the emission current; A scan driver configured to provide a scan signal to each of the plurality of pixels; A transmit driver configured to provide a transmit signal to each of the plurality of pixels; A sweep frequency driver configured to provide the sweep frequency voltage to each of the plurality of pixels; A data driver configured to provide the pulse width modulation data voltage and the constant current generating data voltage to each of the plurality of pixels; and The controller is configured to control the scan driver, the transmit driver, the sweep driver, and the data driver.

10. An electronic device, characterized in that, include: The processor is configured to provide input image data; as well as A display device configured to receive input image data from the processor and display an image based on the input image data, the display device comprising: A display panel includes a plurality of pixels, each of the plurality of pixels comprising: A pulse width modulation circuit is configured to generate a pulse width modulation signal based on pulse width modulation data voltage and sweep frequency voltage. A constant current generating circuit is configured to generate a transmit current based on a constant current generating a data voltage and the pulse width modulation signal, the constant current generating circuit comprising: A constant current generating drive transistor is configured to generate the emitter current; A first capacitor includes a first electrode that receives a first constant current to generate a power supply voltage and a second electrode connected to the gate of the constant current generating drive transistor; and The second capacitor includes a first electrode connected to the gate of the constant current generating drive transistor and a second electrode receiving the pulse width modulation signal generated by the pulse width modulation circuit; and A light-emitting element configured to emit light based on the emission current; A scan driver configured to provide a scan signal to each of the plurality of pixels; A transmit driver configured to provide a transmit signal to each of the plurality of pixels; A sweep frequency driver configured to provide the sweep frequency voltage to each of the plurality of pixels; A data driver configured to provide the pulse width modulation data voltage and the constant current generating data voltage to each of the plurality of pixels; and The controller is configured to control the scan driver, the transmit driver, the sweep driver, and the data driver.

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