A silicon rod, silicon wafer, solar cell, and photovoltaic module
By optimizing the surface roughness of silicon rods and wafers, the problem of high breakage rates in silicon wafers and solar cells was solved, achieving the effects of reducing silicon wafer breakage rates and improving production quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- LONGI GREEN ENERGY TECH CO LTD
- Filing Date
- 2024-12-31
- Publication Date
- 2026-07-31
AI Technical Summary
During the processing of solar silicon rods, the breakage rate of silicon wafers and cells is relatively high, mainly due to micro-cracks and fragmentation caused by micro-defects on the surface of silicon rods and wafers.
By optimizing the surface roughness of silicon rods and wafers, the average roughness Ra of silicon rods and wafers is limited to 0.05-0.2 μm and the roughness Rz is limited to 0.8-2.5 μm, thereby optimizing the grinding and polishing process of silicon rods to reduce the breakage rate of silicon wafers.
It significantly reduces the silicon wafer breakage rate during silicon rod cutting and also reduces the breakage rate of solar cells and photovoltaic modules, thereby improving the production quality and efficiency of silicon wafers and solar modules.
Smart Images
Figure CN224575923U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of photovoltaic processing technology, specifically relating to a silicon rod, silicon wafer, solar cell, and photovoltaic module. Background Technology
[0002] During the processing of solar silicon rods, the monocrystalline silicon rods are squared to form rough square rods. Micro-defects such as line marks and pits easily form on the surface of these rods, generally requiring grinding and polishing. Furthermore, during the cutting of silicon rods into wafers, these micro-defects on the surface of the square rods can easily cause micro-cracks during wire cutting, leading to wafer fragmentation. Even further, during the subsequent processing of solar cells or modules, the presence of these micro-defects on the silicon wafers can easily cause fragmentation, significantly increasing the breakage rate in the production of silicon wafers and cells. Utility Model Content
[0003] This application aims to provide a silicon rod, silicon wafer, solar cell, and photovoltaic module to solve the problem of high fragmentation rate of existing silicon wafers.
[0004] To solve the above-mentioned technical problems, this application is implemented as follows:
[0005] In a first aspect, a silicon rod is provided, including a silicon rod body, the silicon rod body including a plurality of surfaces parallel to the axial direction of the silicon rod;
[0006] The average roughness Ra of at least one of the surfaces is 0.05–0.2 μm; and / or the roughness Rz of at least one of the surfaces is 0.8–2.5 μm.
[0007] Optionally, the silicon rod body includes a first surface and a second surface that are parallel to and opposite to the axial direction of the silicon rod, and a plurality of side surfaces connecting the first surface and the second surface;
[0008] The average roughness Ra of the first surface is 0.09–0.2 μm, and the average roughness Ra of the second surface is 0.05–0.1 μm.
[0009] And / or, the roughness Rz of the first surface is 1.1-2.5 μm, and the roughness Rz of the second surface is 0.8-1.3 μm.
[0010] Optionally, the first surface has a first chamfer at both ends, and the second surface has a second chamfer at both ends, wherein the edge length of the first chamfer is less than or equal to the edge length of the second chamfer; wherein,
[0011] The average roughness Ra of the first surface is greater than or equal to the average roughness Ra of the second surface; and / or, the roughness Rz of the first surface is greater than or equal to the roughness Rz of the second surface.
[0012] In a second aspect, a silicon wafer is provided, the silicon wafer comprising: a silicon wafer body, the silicon wafer body including a first surface and a second surface disposed opposite to each other along its thickness direction, and a plurality of silicon wafer side surfaces connecting the first surface and the second surface, wherein the average roughness Ra of at least one of the plurality of silicon wafer side surfaces is 0.05-0.2 μm.
[0013] And / or, the roughness Rz of at least one of the plurality of silicon wafer sides is 0.5-2.5 μm.
[0014] Optionally, among the plurality of silicon wafer sides, at least one of the silicon wafer sides has an average roughness Ra greater than the average roughness Ra of the other silicon wafer sides.
[0015] Optionally, the plurality of silicon wafer sides include a first silicon wafer side and a second silicon wafer side disposed opposite to each other. The first silicon wafer side has a first chamfer at both ends, and the second silicon wafer side has a second chamfer at both ends. The edge length of the first chamfer is less than or equal to the edge length of the second chamfer.
[0016] The average roughness Ra of the first silicon wafer side surface is greater than the average roughness Ra of the second silicon wafer side surface; and / or, the roughness Rz of the first silicon wafer side surface is greater than or equal to the roughness Rz of the second silicon wafer side surface.
[0017] Optionally, the edge length of the first chamfer is 1-2 mm, and the edge length of the second chamfer is 1-8 mm.
[0018] Optionally, the average roughness Ra of the side surface of the first silicon wafer is 0.09-0.2 μm, and the average roughness Ra of the side surface of the second silicon wafer is 0.05-0.1 μm;
[0019] And / or, the surface roughness Rz of the first silicon wafer side is 1.1-2.5 μm, and the surface roughness Rz of the second silicon wafer side is 0.8-1.3 μm.
[0020] Optionally, the average roughness Ra of the third and fourth surfaces is 0.05–0.18 μm;
[0021] And / or, the roughness Rz of the third surface and the fourth surface is 0.5-1.0 μm.
[0022] Thirdly, this application also discloses a solar cell, the solar cell comprising: the silicon wafer described in any of the preceding claims.
[0023] Fourthly, this application also discloses a photovoltaic module, which includes the aforementioned solar cells.
[0024] In this embodiment, silicon rods are typically diced into silicon wafers using wire cutting. During dicing, the surface roughness of the silicon rod is related to the wafer breakage rate. When dicing silicon wafers, the silicon rod needs to be bonded to a resin board. The surface roughness of the silicon rod is related to the bonding strength and stability of the resin board. Excessive surface roughness of the silicon rod leads to an increased breakage rate. This application addresses this by optimizing the grinding and polishing process of the silicon rod to improve its surface roughness, thereby reducing the wafer breakage rate during dicing.
[0025] The roughness of the silicon wafer side surface mainly depends on the roughness of the silicon rod surface. The roughness of the silicon wafer side surface is related to the breakage rate of the battery or module. As the silicon substrate of the battery or module, the silicon wafer needs to withstand the stress under different process steps during the battery or module manufacturing process, such as cleaning, transportation, basket loading, screen printing, and electrode welding. Excessive roughness of the silicon wafer side surface will also lead to a breakage rate during the battery or module manufacturing process.
[0026] This application reduces the micro-defects on the sides of the silicon wafer by limiting the average roughness Ra of at least one side of the silicon rod or the silicon wafer to 0.05-0.2 μm, thereby reducing the breakage rate of the silicon wafer during the slicing process and correspondingly reducing the breakage rate of the solar cells and solar modules using the silicon wafer.
[0027] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0028] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0029] Figure 1 This is a schematic diagram of the cross-sectional structure of a silicon rod according to an embodiment of this application;
[0030] Figure 2 This is a schematic diagram of the structure of a silicon wafer according to an embodiment of this application;
[0031] Figure 3 This is a schematic diagram of the cutting of a silicon rod as described in an embodiment of this application.
[0032] Reference numerals: 10 - silicon rod body, 100 - side surface, 101 - first surface, 102 - second surface, 104 - first chamfer, 105 - second chamfer, 20 - silicon wafer body, 200 - silicon wafer side surface, 201 - first silicon wafer side surface, 202 - second silicon wafer side surface, 203 - third silicon wafer side surface. Detailed Implementation
[0033] The embodiments of this utility model will now be described in detail. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0034] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0035] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.
[0036] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0037] This application provides a silicon rod, including a silicon rod body, the silicon rod body including a plurality of surfaces parallel to the axial direction of the silicon rod. The average roughness Ra of at least one of the surfaces is 0.05–0.2 μm; and / or, the roughness Rz of at least one of the surfaces is 0.8–2.5 μm.
[0038] Specifically, as one implementation method, this application provides a silicon rod, such as... Figure 1As shown, the silicon rod may specifically include: a silicon rod body 10, which may specifically include a first surface 101 and a second surface 102 that are parallel to and opposite to the axial direction of the silicon rod, and a plurality of side surfaces 100 connecting the first surface 101 and the second surface 102. At least one of the first surface 101 and the second surface 102, or the plurality of side surfaces 100 connecting the first surface 101 and the second surface 102, has an average surface roughness Ra of 0.05-0.2 μm.
[0039] In this embodiment, the silicon rod is a square rod. The axial direction of the silicon rod refers to the length direction along the prism of the square rod. The surface parallel to the axial direction of the silicon rod refers to the side surface of the square rod.
[0040] Specifically, the average roughness Ra represents the arithmetic mean of the absolute values of the profile offsets over a sampling length. In this embodiment, a roughness meter is used to measure the roughness along the axial direction perpendicular to the silicon rod, with a measurement range of 13.5 mm and a measurement speed of 0.5 mm / s. During actual measurement, different areas on the surface of a single silicon rod are selected for measurement, such as five areas at distances of 20 mm, 40 mm, 60 mm, 80 mm, and 100 mm from the axial edge of the silicon rod. At least three silicon rods are measured simultaneously; finally, the average value of the measured data is calculated.
[0041] In this embodiment, by limiting the average roughness Ra of at least one surface of the silicon rod to 0.05-0.2 μm, the overall quality of the silicon rod surface is limited, thereby reducing micro-defects on the silicon rod surface. This reduces the breakage rate of the silicon rod during the slicing process, and correspondingly reduces the breakage rate of the solar cells and solar modules using the silicon wafers.
[0042] In practical applications, the silicon rod is cut into silicon wafers using a diamond wire mesh. During the cutting process, the surface roughness of the silicon rod is related to the fragmentation rate of the silicon wafers. Furthermore, during the cutting process, the silicon rod needs to be bonded to a resin board. The surface roughness of the silicon rod is related to the bonding strength and stability of the resin board. Excessive roughness leads to an increased fragmentation rate. This application addresses this by optimizing the grinding and polishing process of the silicon rod to improve its surface roughness, thereby reducing the fragmentation rate of the silicon wafers during cutting.
[0043] For example, when the average surface roughness Ra of the silicon rod is less than 0.2 μm, the breakage rate at the silicon wafer end is less than 0.8%. When the average surface roughness Ra is greater than 0.2 μm, the breakage rate at the silicon wafer end is greater than 0.8%. For instance, when the average surface roughness Ra is 0.3 μm, the breakage rate at the silicon wafer end is 1.02%; when the average surface roughness Ra is 0.5 μm, the breakage rate is 1.05%.
[0044] Based on the above embodiments, a silicon rod is provided, wherein the roughness Rz of at least one of the first surface 101, the second surface 102, or the plurality of side surfaces 100 of the silicon rod is 0.8-2.5 μm.
[0045] Specifically, Rz represents the sum of the maximum profile peak height and the maximum profile valley depth within a sampling length; this parameter reflects the microscopic roughness of the surface. In this embodiment, a roughness meter is used for roughness measurement, measured along the axial direction perpendicular to the silicon rod, with a measurement range of 13.5 mm and a measurement speed of 0.5 mm / s. In actual measurement, different areas on the surface of a single silicon rod are selected for measurement, such as five areas at distances of 20 mm, 40 mm, 60 mm, 80 mm, and 100 mm from the axial edge of the silicon rod. At least three silicon rods are measured simultaneously; finally, the average value of the measured data is calculated.
[0046] In this embodiment, the maximum defect on the silicon rod surface is further limited by defining the roughness Rz, thereby further defining the quality of the silicon rod surface. When the silicon rod is polished, limiting the surface roughness reduces the thickness of the damage layer on the surface and sides of the silicon rod; simultaneously, when the surface or sides of the silicon rod contact the diamond wire mesh, it avoids the problem of excessively large micro-defects causing micro-crack propagation and leading to increased silicon wafer fragmentation.
[0047] Specifically, for example, when the surface roughness Rz of the silicon rod is less than 0.8 μm, the fragmentation rate at the silicon wafer end is less than 0.8%. When the average roughness Rz is greater than 2.5 μm, the fragmentation rate at the silicon wafer end is greater than 0.8%. For example, when the average roughness Rz is 3 μm, the fragmentation rate at the silicon wafer end is 1.02%; when the average roughness Rz is 3.5 μm, the fragmentation rate is 1.04%.
[0048] Based on the above embodiments or other alternative embodiments, see Figure 1 and Figure 3 As shown, the silicon rod is a half rod, which is cut from a finished square silicon rod. The first surface 101 of the silicon rod has a first chamfer 104 at both ends, and the second surface has a second chamfer 105 at both ends. The edge length of the first chamfer 104 is less than or equal to the edge length of the second chamfer 105.
[0049] In this embodiment, the first surface and the second surface refer to two opposite sides of the square bar. The two ends of the first surface refer to the ends of the first surface closest to its two adjacent sides. The first chamfer is provided on the two side edges adjacent to the first surface, i.e., the side edges are chamfered. The second chamfer is provided on the two side edges adjacent to the second surface. The edge length of the first chamfer refers to the length of the first chamfer circumferentially on the square bar. The edge length of the second chamfer refers to the length of the second chamfer circumferentially on the square bar.
[0050] Specifically, in this embodiment, the edge length of the first chamfer 104 is less than or equal to the edge length of the second chamfer 105, resulting in a larger surface area of the first surface 101 than the second surface 102. This provides more contact surface during the adhesive bonding of the silicon rod, enhancing adhesion and making the bond between the silicon rod and the resin board stronger. Furthermore, the two first chamfers 104 of the first surface 101 are identical, and the two second chamfers 105 of the second surface 102 are identical, facilitating tension control of the wire mesh during silicon rod cutting.
[0051] In this embodiment, the average roughness Ra of the first surface 101 is greater than or equal to the average roughness Ra of the second surface 102; and / or, the roughness Rz of the first surface 101 is greater than or equal to the roughness Rz of the second surface 102.
[0052] Optionally, in any silicon rod, the average roughness Ra of the first surface 101 of the silicon rod is greater than or equal to the average roughness Ra of the second surface 102.
[0053] Optionally, the average roughness Ra of the first surface 101 of the silicon rod is 0.09-0.2 μm, specifically including but not limited to any one of 0.09 μm, 0.12 μm, 0.16 μm, 0.17 μm, and 0.2 μm. The average roughness Ra of the second surface 102 is 0.05-0.1 μm, specifically including but not limited to any one of 0.05 μm, 0.12 μm, 0.16 μm, 0.17 μm, and 0.2 μm. In this embodiment, the values of the average roughness Ra of the first surface 101 and the second surface 102 are not specifically limited.
[0054] Optionally, in any silicon rod, the roughness Rz of the first surface 101 of the silicon rod is greater than or equal to the roughness Rz of the second surface 102.
[0055] Optionally, the roughness Rz of the first surface 101 of the silicon rod is 1.1-2.5 μm, specifically including but not limited to any one of 1.1 μm, 1.4 μm, 1.7 μm, 2.0 μm and 2.5 μm; the roughness Rz of the second surface 102 is 0.8-1.3 μm, specifically including but not limited to any one of 0.8 μm, 0.95 μm, 1.0 μm, 1.1 μm and 1.3 μm.
[0056] In practical applications, as one implementation, by defining the roughness Ra or Rz of the first surface 101 of the silicon rod as greater than the roughness of the second surface 102, when selecting the first surface 101 as the adhesive surface, the greater roughness provides a larger surface area, offering more contact surface to enhance adhesion, thus making the adhesive bond between the silicon rod and the resin plate stronger. Furthermore, the surface with greater roughness has more pits and cracks; during bonding, the adhesive can fill more surface pits and cracks in the same area, forming a stronger physical connection, thereby improving the adhesive bonding strength and reducing fragmentation caused by silicon wafers falling during dicing.
[0057] Furthermore, when selecting the first surface 101 as the adhesive surface, its high roughness ensures stability and reduces the risk of wafer cracking during cutting as the wire mesh enters the contact area between the resin plate and the second surface 102. This is because the silicon rod and resin plate are firmly bonded together. Conversely, the second surface 102 has a lower roughness. When the wire mesh begins to contact the silicon rod, it is preferable to contact the second surface 102. As the cutting surface, the lower roughness of the second surface results in fewer pits or defects on the silicon rod surface. This reduces edge defects in the silicon wafer, such as notches and microcracks, during wire mesh cutting.
[0058] In practical applications, by limiting the roughness of the first surface 101 to be greater than or equal to the roughness of the second surface 102, the processing steps for the first surface 101 can be reduced. For example, after the finished silicon rod is cut into the silicon rod of this embodiment, the finer polishing of the first surface 101 is eliminated. This reduces the processing steps or processing time for the first surface 101 while improving the processing efficiency and quality during silicon rod cutting. In this embodiment, the second surface 102 of the silicon rod still undergoes finer polishing. In specific production processes, if the average roughness Ra of the second surface 102 of the silicon rod is less than 0.05 μm, the workload of polishing the silicon rod becomes extremely large, resulting in very high production costs. Therefore, considering processing performance and production costs, the average roughness Ra of the second surface 102 should be controlled above 0.05 μm. In this embodiment, limiting the average roughness Ra of the second surface 102 to 0.05–0.1 μm or the roughness Rz to 0.8–1.3 μm can improve the quality of the silicon wafers during silicon rod cutting.
[0059] As another embodiment of this application, refer to Figure 2 The diagram illustrates a structural schematic of a silicon wafer according to an embodiment of this application. Figure 2 As shown, the silicon wafer may specifically include: a silicon wafer body 20, which may specifically include a third surface and a fourth surface disposed opposite to each other along its thickness direction, and a plurality of silicon wafer side surfaces 200 connecting the third surface and the fourth surface, wherein the average roughness Ra of at least one silicon wafer side surface 200 is 0.05-0.2 μm. The plurality of silicon wafer side surfaces 200 include a first silicon wafer side surface 201, a second silicon wafer side surface 202, and a third silicon wafer side surface 203.
[0060] In this embodiment, the third and fourth surfaces of the silicon wafer, which are disposed opposite to each other along its thickness direction, refer to the two surfaces formed after the square rod is wire-cut. The side surface of the silicon wafer refers to the surface along the thickness direction of the silicon rod.
[0061] Based on the above embodiments, as one implementation method, the average roughness Ra of at least one silicon wafer side 200 among the plurality of silicon wafer side surfaces is 0.05-0.2 μm; and / or, the roughness Rz of at least one silicon wafer side 200 is 0.5-2.5 μm.
[0062] Specifically, in this embodiment, the roughness data of the silicon wafer side surface 200, such as the average roughness Ra and roughness Rz, can be measured by direct contact, such as with a roughness meter, or by non-contact measurement, such as with an optical measurement method like a laser scanning microscope. In this embodiment, by limiting the average roughness Ra of at least one silicon wafer side surface 200 to 0.05-0.2 μm and the roughness Rz of at least one silicon wafer side surface to 0.5-2.5 μm, the micro-defects on the silicon wafer side surface 200 can be reduced, thereby reducing the breakage rate of the silicon wafer during slicing, cleaning, and other processes, and correspondingly reducing the breakage rate of the solar cells and solar modules using the silicon wafer.
[0063] In specific applications, the breakage rate of the silicon wafer during slicing and subsequent production processes (such as at the battery end) is related to the average roughness Ra of the silicon wafer's side surface 200. Experimental results show that the larger the average roughness Ra and roughness Rz of the silicon wafer's side surface 200, the greater the breakage rate at the battery end.
[0064] For example, the average roughness Ra reflects the average quality of micro-defects on the side surface of the silicon wafer. When the average roughness Ra of the silicon wafer side surface is less than 0.2 μm, the breakage rate at the cell end is less than 1%. When the average roughness Ra is greater than 0.2 μm, the breakage rate at the cell end is greater than 1%. For example, when the average roughness Ra is 0.3 μm, the breakage rate at the cell end is 1.02%; when the average roughness Ra is 0.5 μm, the breakage rate is 1.05%.
[0065] Roughness Rz reflects the maximum value of micro-defects on the side surface of the silicon wafer. When the roughness Rz of the silicon wafer side surface (200 mm) is less than 0.5 μm, the fragmentation rate at the cell end is less than 1%. When the average roughness Ra is greater than 2.5 μm, the fragmentation rate at the cell end is greater than 1%. For example, when the roughness Rz is 3 μm, the fragmentation rate at the cell end is 1.03%; when the roughness Rz is 3.5 μm, the fragmentation rate is 1.04%.
[0066] In practical applications, the average roughness Ra of the silicon wafer side surface 200 is also related to the processing difficulty of the silicon wafer side surface 200. During the process of forming the silicon wafer using silicon rod slicing, the outer surface of the silicon rod needs to be polished to control the roughness of the silicon wafer side surface 200. The smaller the average roughness of the silicon wafer side surface 200, the higher the workload and quality requirements for polishing the silicon rod. In specific production processes, when the average roughness Ra of the silicon wafer side surface 200 is less than 0.05 μm, the workload for polishing the silicon rod becomes extremely large, resulting in very high production costs. Furthermore, when the average roughness Ra of the silicon wafer side surface is less than 0.05 μm, the breakage rate during slicing and subsequent production processes (cell end) is already very low. Therefore, considering processing performance and production costs, the average roughness Ra of the silicon wafer side surface 200 should be controlled above 0.05 μm.
[0067] In this embodiment, by controlling the average roughness Ra of the silicon wafer side surface 200 to 0.05-0.2 μm, the breakage rate of the silicon wafer during the slicing process can be significantly reduced, and the breakage rate at the battery end can be reduced accordingly, thereby reducing the overall production cost of the silicon wafer. Simultaneously, the polishing operation and production cost of the silicon rod can be balanced, making it easy to implement.
[0068] For example, the average roughness Ra of the silicon wafer side surface 200 can be 0.05um, 0.08um, 0.12um, 0.17um and 0.2um, etc. In this embodiment of the application, the average roughness Ra of the silicon wafer side surface 200 is not specifically limited.
[0069] It should be noted that in practical applications, after the silicon ingot is wire-cut, the first silicon wafer side surface 201 is part of the first surface 101 of the silicon ingot, and the second silicon wafer side surface 202 is part of the second surface 102 of the silicon ingot. The cut silicon wafers generally need to be cleaned with acid or alkali to obtain the final silicon wafer product. The roughness of the silicon wafer side surface 200 is basically the same as the roughness data of the silicon ingot from which the silicon wafer was cut, or the roughness of the silicon wafer side surface 200 is slightly smaller than the roughness data of the silicon ingot surface. Specifically, one optional measurement method is to directly measure the roughness of the silicon ingot, thereby defining or characterizing the roughness of the silicon wafer side surface 200 by measuring and defining the average surface roughness of the silicon ingot. Another optional measurement method is to measure the roughness of the silicon wafer side surface using a roughness meter or a laser scanning microscope.
[0070] For example, the surface roughness data of the silicon rod can be measured using a roughness meter (e.g., an SJ-210 roughness meter). For instance, in the case where the silicon rod is a square silicon rod, the surface roughness of the silicon rod can be measured radially using a roughness measuring device.
[0071] In some optional embodiments of this application, among the plurality of silicon wafer sides 200 of the silicon wafer body 20, at least one silicon wafer side 200 has an average roughness Ra greater than the average roughness Ra of the other silicon wafer sides 200. During the process of cutting the silicon rod into silicon wafers, one surface of the silicon rod needs to be bonded to a resin plate. To improve the bonding reliability between the silicon rod and the resin plate, the surface on which the silicon rod is bonded to the resin plate needs to have a certain roughness.
[0072] Specifically, when the roughness of the adhesive surface on the silicon rod bonded to the resin plate is relatively large, the adhesive surface has a larger surface area, providing more contact area to enhance adhesion and thus making the adhesive bond stronger. Furthermore, due to the larger roughness of the adhesive surface, there are more pits and cracks. During bonding, within the same area, the adhesive can fill more surface pits and cracks, forming a stronger physical bond, thereby improving the adhesive bonding strength. In addition, the large roughness of the adhesive surface helps the wire mesh maintain stability when it is cut into the contact area between the wire mesh and the resin plate, reducing the risk of wafer breakage. That is, the silicon rod must have at least one surface (the adhesive surface) with a rougher surface than the others, which can be used for bonding with the resin plate. Therefore, after the silicon rod is cut into silicon wafers, the average roughness Ra of the silicon wafer side surface 200 formed by the rougher surface bonded to the resin plate is greater than the average roughness Ra of the other silicon wafer side surfaces 200.
[0073] It should be noted that, in practical applications, the silicon rod can be bonded to the resin plate on one or more surfaces. Correspondingly, the silicon wafer can also have one or more silicon wafer sides 200 with an average roughness Ra greater than other silicon wafer sides 200. This application embodiment does not limit this.
[0074] In some optional embodiments of this application, the plurality of silicon wafer sides 200 include a first silicon wafer side 201 and a second silicon wafer side 202 disposed opposite to each other. The first silicon wafer side 201 has a first chamfer 104 at both ends, and the second silicon wafer side 202 has a second chamfer 105 at both ends. The length of the first silicon wafer side 201 is greater than the dimension of the second silicon wafer side 202; the edge length of the first chamfer 104 is less than or equal to the edge length of the second chamfer. The average roughness Ra of the first silicon wafer side 201 is greater than the average roughness Ra of the second silicon wafer side 202.
[0075] In this embodiment, the first silicon wafer side surface 201 and the second silicon wafer side surface 202 are two oppositely arranged sides of the silicon wafer. The first chamfers at both ends of the first silicon wafer side surface 201 correspond to the first chamfers of the silicon rod; the second silicon wafer side surface 202 has second chamfers at both ends, corresponding to the second chamfers of the silicon rod. Specifically, in this embodiment, the edge length of the first chamfer 104 is less than or equal to the edge length of the second chamfer 105, resulting in the length of the first silicon wafer side surface 201 being greater than or equal to the length of the second silicon wafer side surface 202. This provides more contact surface during the adhesive bonding of the silicon rod, enhancing adhesion and making the adhesive bonding between the silicon rod and the resin board stronger. Furthermore, the two first chamfers 104 of the first silicon wafer side surface 201 are identical, and the two second chamfers 105 of the second silicon wafer side surface 202 are identical, facilitating tension control of the wire mesh during silicon rod cutting.
[0076] Optionally, the average roughness Ra of the first silicon wafer side surface 201 is greater than the average roughness Ra of the second silicon wafer side surface 202; and / or, the roughness Rz of the first silicon wafer side surface 201 is greater than or equal to the roughness Rz of the second silicon wafer side surface 202.
[0077] In practical applications, as one implementation method, by defining the roughness Ra or Rz of the first surface of the silicon rod as greater than the roughness of the second surface, when selecting the first silicon wafer side surface 201 as the adhesive surface, the greater roughness provides more surface area, which can provide more contact surface to enhance adhesion, thereby making the adhesive bond between the silicon rod and the resin board stronger. Furthermore, the surface with greater roughness has more pits and cracks; during bonding, in the same area, the adhesive can fill more surface pits and cracks, forming a stronger physical connection, thereby improving the adhesive bonding strength and reducing wafer detachment during slicing.
[0078] In practical applications, by setting a first chamfer 104 at both ends of the first silicon wafer side 201 and a second chamfer 105 at both ends of the second silicon wafer side 202, the breakage rate of the silicon wafer during slicing and production can be effectively reduced.
[0079] In some optional embodiments of this application, the edge length of the first chamfer 104 is less than the edge length of the second chamfer 105, so that the size of the first chamfer 104 is less than the size of the second chamfer 105, thereby making the length of the first silicon wafer side surface 201 between the two first chamfers 104 greater than the length of the second silicon wafer side surface 202 between the two second chamfers 105.
[0080] The edge length of the first chamfer 104 refers to the length of the chamfer along the circumferential direction of the side of the silicon wafer. The edge length of the second chamfer 105 refers to the length of the chamfer along the circumferential direction of the side of the silicon wafer. In practical applications, the edge length of the first chamfer 104 can specifically be the length of the hypotenuse of the first chamfer 104, and the edge length of the second chamfer 105 can specifically be the length of the hypotenuse of the second chamfer 105.
[0081] Optionally, the edge length of the first chamfer 104 is 1-2 mm, and the edge length of the second chamfer 105 is 1-8 mm. In this way, on the one hand, the edge length of the first chamfer 104 is smaller than the edge length of the second chamfer 105, and on the other hand, the first chamfer 104 and the second chamfer 105 are easier to process.
[0082] Specifically, the side 100 between the first silicon wafer side 201 and the second silicon wafer side 202 can be collectively referred to as the third silicon wafer side 203. That is, the first chamfer 104 is located between the first silicon wafer side 201 and the third silicon wafer side 203, and the second chamfer 105 is located between the second silicon wafer side 202 and the third silicon wafer side 203. In practical applications, while controlling the edge lengths of the first chamfer 104 and the second chamfer 105, the included angles between the first chamfer 104 and the second chamfer 105 and the third silicon wafer side 203 can also be controlled to reduce the breakage rate of the silicon wafer during slicing. For example, by controlling the included angles between the first chamfer 104, the second chamfer 105 and the third silicon wafer side 203 to 40°-50°, it is convenient to process the first chamfer 104 and the second chamfer 105, and at the same time, the breakage rate of the silicon wafer during slicing and subsequent processing can be significantly reduced.
[0083] Optionally, in any silicon wafer, the average roughness Ra of the first silicon wafer side surface 201 is greater than or equal to the average roughness Ra of the second silicon wafer side surface 202.
[0084] Optionally, the average roughness Ra of the first silicon wafer side surface 201 is 0.09-0.2 μm, specifically including but not limited to any one of 0.09 μm, 0.12 μm, 0.16 μm, 0.17 μm, and 0.2 μm. The average roughness Ra of the second silicon wafer side surface 202 is 0.05-0.1 μm, specifically including but not limited to any one of 0.05 μm, 0.12 μm, 0.16 μm, 0.17 μm, and 0.2 μm. In this embodiment, the value of the average roughness Ra of the first silicon wafer side surface 201 and the second silicon wafer side surface 202 is not specifically limited.
[0085] Optionally, in any silicon wafer, the roughness Rz of the first silicon wafer side surface 201 is greater than or equal to the roughness Rz of the second silicon wafer side surface 202.
[0086] Optionally, the roughness Rz of the first silicon wafer side surface 201 is 1.1-2.5 μm, specifically including but not limited to any one of 1.1 μm, 1.4 μm, 1.7 μm, 2.0 μm, and 2.5 μm; the roughness Rz of the second silicon wafer side surface 202 is 0.8-1.3 μm, specifically including but not limited to any one of 0.8 μm, 0.95 μm, 1.0 μm, 1.1 μm, and 1.3 μm.
[0087] Optionally, the average roughness Ra of the third and fourth surfaces is 0.05-0.18 μm; and / or, the roughness Rz of the third and fourth surfaces is 0.5-1.0 μm. By adjusting the average roughness Ra and roughness Rz of the third and fourth surfaces, the overall surface quality of the silicon wafer can be improved, avoiding an excessively thick damage layer on the silicon wafer surface and excessive removal at the battery end.
[0088] In summary, the silicon wafer described in the embodiments of this application may include at least the following advantages:
[0089] In this embodiment of the application, by limiting the average roughness Ra of at least one side surface of the silicon wafer to 0.05-0.2 μm, and / or, the roughness Rz of at least one of the plurality of silicon wafer sides to 0.5-2.5 μm, the average micro-defect and maximum micro-defect values of the silicon wafer sides can be reduced, thereby reducing the breakage rate of the silicon wafer during the slicing process, and correspondingly reducing the breakage rate of the solar cells and solar modules using the silicon wafer.
[0090] This application also provides a battery cell, which can be made using the silicon wafer described in the above embodiments.
[0091] In specific applications, during the process of manufacturing the aforementioned silicon wafer into solar cells, since the average roughness Ra of at least one side of the silicon wafer is 0.05-0.2 μm, the micro-defects on the side of the silicon wafer can be reduced, thereby reducing the breakage rate of the silicon wafer in the production of solar cells and photovoltaic modules.
[0092] This application also provides a photovoltaic module, which may specifically include the solar cells described in the above embodiments.
[0093] In this embodiment, the structure of the battery cell is the same as that of the battery cell described in any of the above embodiments, and its beneficial effects are similar, so it will not be described in detail here.
[0094] Example 1 provides a silicon rod for fabricating silicon wafers.
[0095] Step 1: Provide a silicon rod with the following specifications: dimensions of 183.6*195.2; use a grinding wheel to polish the four chamfers and four surfaces of the silicon rod, resulting in a finished square rod with dimensions of 182.3*183.9.
[0096] Step 2: Prepare half-rods: such as Figure 3 As shown, by using a loop to cut the finished square bar laterally along the length direction at the middle position of the long side at 183.9, and then using a grinding wheel to polish the newly generated wire-cut surface, a finished half bar with a size of 182.3*91.1 is produced, which is the silicon rod of this application.
[0097] Step 3: Slicing: The surface of the silicon rod generated in step 2, i.e. the first surface, is attached to the adhesive board and then cut along the short side with a length of 91.1 mm to produce a silicon wafer.
[0098] In this embodiment, the roughness of the silicon rod obtained in step 2 is measured using a roughness meter. The measurement is performed along the axial direction perpendicular to the silicon rod, with a measurement range of 13.5 mm and a measurement speed of 0.5 mm / s. During the actual measurement, different areas on the surface of a single silicon rod are selected for measurement, such as five areas at distances of 20 mm, 40 mm, 60 mm, 80 mm, and 100 mm from the axial edge of the silicon rod (the position 80 mm from the axial edge is approximately the center position of the square rod's edge). At least three silicon rods are measured simultaneously. The final data for the second and first surfaces of the silicon rod are shown in the table below.
[0099] Table 1: Second surface of silicon rod (surface with lower roughness)
[0100]
[0101]
[0102] Table 2: First surface of silicon rod (surface with greater roughness)
[0103]
[0104] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0105] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.
Claims
1. A silicon rod, characterized in that, Includes a silicon rod body, the silicon rod body including a plurality of surfaces parallel to the axial direction of the silicon rod; The average roughness Ra of at least one of the surfaces is 0.05-0.2 μm; and / or the roughness Rz of at least one of the surfaces is 0.8-2.5 μm.
2. The silicon rod according to claim 1, characterized in that, The silicon rod body includes a first surface and a second surface that are parallel to and opposite to the axial direction of the silicon rod; The average roughness Ra of the first surface is 0.09-0.2 μm, and the average roughness Ra of the second surface is 0.05-0.1 μm; And / or, the roughness Rz of the first surface is 1.1-2.5 μm, and the roughness Rz of the second surface is 0.8-1.3 μm.
3. The silicon rod of claim 2, wherein The first surface has a first chamfer at both ends, and the second surface has a second chamfer at both ends, wherein the edge length of the first chamfer is less than or equal to the edge length of the second chamfer; wherein, The average roughness Ra of the first surface is greater than or equal to the average roughness Ra of the second surface; and / or, the roughness Rz of the first surface is greater than or equal to the roughness Rz of the second surface.
4. A silicon wafer, characterized in that, The wafer includes a silicon wafer body, which includes a third surface and a fourth surface disposed opposite to each other along its thickness direction, and a plurality of silicon wafer sides connecting the third surface and the fourth surface. The average roughness Ra of at least one of the silicon wafer sides is 0.05-0.2 μm; and / or, the roughness Rz of at least one of the plurality of silicon wafer sides is 0.5-2.5 μm.
5. The silicon wafer of claim 4, wherein, Of the plurality of silicon wafer sides, at least one of the silicon wafer sides has an average roughness Ra greater than the average roughness Ra of the other silicon wafer sides.
6. The silicon wafer of claim 4, wherein, The plurality of silicon wafer sides include a first silicon wafer side and a second silicon wafer side disposed opposite to each other. The first silicon wafer side has a first chamfer at both ends, and the second silicon wafer side has a second chamfer at both ends. The edge length of the first chamfer is less than or equal to the edge length of the second chamfer. The average roughness Ra of the first silicon wafer side surface is greater than the average roughness Ra of the second silicon wafer side surface; and / or, the roughness Rz of the first silicon wafer side surface is greater than or equal to the roughness Rz of the second silicon wafer side surface.
7. The silicon wafer of claim 6, wherein, The edge length of the first chamfer is 1-2mm, and the edge length of the second chamfer is 1-8mm.
8. The silicon wafer of claim 6, wherein, The average roughness Ra of the side surface of the first silicon wafer is 0.09-0.2 μm, and the average roughness Ra of the side surface of the second silicon wafer is 0.05-0.1 μm; And / or, the surface roughness Rz of the first silicon wafer side is 1.1-2.5 μm, and the surface roughness Rz of the second silicon wafer side is 0.8-1.3 μm.
9. The silicon wafer of claim 4, wherein, The average roughness Ra of the third and fourth surfaces is 0.05-0.18 μm; And / or, the roughness Rz of the third surface and the fourth surface is 0.5-1.0 μm.
10. A battery sheet, characterized by The solar cell comprises: a silicon wafer as described in any one of claims 4 to 9.
11. A photovoltaic module, characterized by The photovoltaic module includes the solar cell as described in claim 10.