Wafer and pressure sensor

Abstract

The wafer and force sensor provided in this application relate to the field of pressure sensing technology, and can ensure the insulation performance of the insulating layer during the bonding process between the substrate and the cover plate. The wafer includes: a first substrate comprising a semiconductor material; an insulating layer; a second substrate comprising a semiconductor material, the second substrate including multiple connecting portions and multiple piezoresistive strips, adjacent connecting portions being spaced apart, and the two ends of the piezoresistive strips being connected to two adjacent connecting portions respectively, the connecting portions and the connected piezoresistive strips being alternately connected to form a pressure detection structure, the first substrate and the second substrate being connected through a first conductive structure; a cover plate, a portion of its surface near the first substrate being bonded to a portion of its surface away from the first substrate, the cover plate including a first opening penetrating the cover plate; and a second conductive structure located within the first opening and electrically connected to the first conductive structure for receiving external power signals.

Description

Technical Field

[0001] This application relates to the field of pressure sensing technology, and more particularly to a wafer and a pressure sensor. Background Technology

[0002] With the advancement and development of sensing technology, the requirements for the sensitivity and reliability of sensors are gradually increasing. For pressure sensors, it is usually necessary to etch the surface of a silicon substrate to form interconnected piezoresistive strips. When an external force is applied to the pressure sensor, the piezoresistive strips deform, and further, under the piezoresistive effect of the semiconductor material, the resistance of the piezoresistive strips changes, thereby converting the pressure signal into an electrical signal and realizing the detection of pressure.

[0003] In existing pressure sensors, the glass cover and silicon wafer layer are typically connected using anodic bonding technology to form a cavity, allowing the piezoresistive strip to deform within the cavity. However, during the anodic bonding process between the substrate, including the insulating layer, and the glass, a high voltage is usually applied to the silicon wafer layer in the substrate. This can damage the insulation properties of the insulating layer, leading to a decrease in the reliability of the piezoresistive strip and affecting the reliability of the pressure sensor. Utility Model Content

[0004] The wafer and pressure sensor provided in this application embodiment can ensure the insulation performance of the insulating layer during the bonding process between the substrate and the cover plate, improve the reliability of the piezoresistive strip, and further ensure the sensitivity and reliability of the pressure sensor.

[0005] A first aspect of this application provides a wafer, comprising:

[0006] A first substrate, the first substrate comprising a semiconductor material;

[0007] An insulating layer is located on one side of the first substrate;

[0008] The second substrate is located on the side of the insulating layer away from the first substrate. The second substrate includes a semiconductor material. The second substrate includes a plurality of connecting portions and a plurality of piezoresistive strips. Two adjacent connecting portions are spaced apart. The two ends of the piezoresistive strips are respectively connected to two adjacent connecting portions. The connecting portions and the connected piezoresistive strips are alternately connected to form a pressure detection structure. The first substrate and the second substrate are connected through a first conductive structure.

[0009] A cover plate is located on the side of the second substrate away from the first substrate. A portion of the surface of the cover plate near the first substrate is bonded to a portion of the surface of the second substrate away from the first substrate. The cover plate includes a first opening that penetrates the cover plate, and the orthographic projection of the first opening on the plane of the first substrate falls within the orthographic projection of the connecting portion on the plane of the first substrate.

[0010] The second conductive structure is located inside the first opening of the cover plate and is electrically connected to the first conductive structure. The second conductive structure is used to receive external power signals.

[0011] In some embodiments, the second substrate includes a second opening, the insulating layer includes a third opening, the first opening, the second opening and the third opening are interconnected, the first conductive structure is located within the second opening and the third opening, one end of the first conductive structure is connected to the first substrate, the other end of the first conductive structure is connected to the second conductive structure through the second opening, and the first conductive structure is connected to the inner wall of the second opening.

[0012] In some embodiments, the first substrate includes a first groove communicating with the second opening, a portion of the first conductive structure being located within the first groove, and the first conductive structure being connected to at least a portion of the inner wall of the first groove.

[0013] In some embodiments, the orthographic projection of the first conductive structure onto the plane of the first substrate falls within the orthographic projection of the second conductive structure onto the plane of the first substrate.

[0014] In some embodiments, the first conductive structure covers the outer walls of the first substrate and the second substrate in the thickness direction.

[0015] In some embodiments, the first conductive structure completely covers the outer wall of the insulating layer in the thickness direction.

[0016] In some embodiments, the first conductive structure is connected to at least a portion of the surface of the first substrate on the side opposite to the second substrate.

[0017] In some embodiments, the first conductive structure is connected to at least a portion of the surface of the second substrate on the side opposite to the first substrate.

[0018] In some embodiments, the wafer includes multiple detection units, and the connection portions within different detection units are spaced apart from each other.

[0019] In some embodiments, the first substrate includes a fourth opening, and the orthographic projection of the piezoresistive strip on the plane of the first substrate falls within the orthographic projection of the fourth opening on the plane of the first substrate.

[0020] In some embodiments, the cover plate has a second groove on the side near the first substrate, and the orthographic projection of the piezoresistive strip on the plane of the first substrate falls within the orthographic projection of the second groove on the plane of the first substrate.

[0021] In some embodiments, the orthographic projection of the surface of the first opening near the insulating layer onto the plane of the first substrate falls within the orthographic projection of the surface of the first opening away from the insulating layer onto the plane of the first substrate.

[0022] In some embodiments, the orthographic projection of the surface of the fourth opening of the first substrate near the insulating layer onto the plane of the first substrate falls within the orthographic projection of the surface of the fourth opening away from the insulating layer onto the plane of the first substrate.

[0023] In some embodiments, the orthographic projection of the fourth opening on the surface of the insulating layer onto the plane of the first substrate falls within the orthographic projection of the second groove of the cover plate onto the plane of the first substrate, wherein the second groove is located on the side of the cover plate closest to the first substrate.

[0024] In some embodiments, the orthographic projection of the second groove onto the plane of the first substrate falls within the orthographic projection of the surface of the fourth opening away from the insulating layer onto the plane of the first substrate.

[0025] In some embodiments, the number of the first openings is equal to the number of the connecting portions.

[0026] In some embodiments, the orthographic projection shape of the pressure sensing structure onto the plane of the first substrate includes an axisymmetric pattern, and at least two second conductive structures connected to the same pressure sensing structure are arranged symmetrically about the axisymmetric pattern.

[0027] In some embodiments, the number of the pressure resistance strips is equal to the number of the connecting portions.

[0028] In some embodiments, the number of the pressure resistance strip and the connecting portion are both multiples of 4.

[0029] In some embodiments, the thickness of the second substrate ranges from 0.6 μm to 1 μm.

[0030] In some embodiments, the first substrate comprises monocrystalline silicon.

[0031] In some embodiments, the second substrate comprises monocrystalline silicon.

[0032] In some embodiments, the insulating layer comprises silicon oxide.

[0033] In some embodiments, the first conductive structure includes at least one of a metallic material and in-situ doped polycrystalline silicon.

[0034] A second aspect of this application provides a pressure sensor, comprising:

[0035] Wafers as described in any of the first aspects above.

[0036] In some embodiments, the first conductive structure of the wafer is connected to a portion of the surface of the first substrate of the wafer on the side away from the insulating layer of the wafer.

[0037] In some embodiments, the first conductive structure of the wafer is connected to a portion of the surface of the second substrate of the wafer on the side away from the insulating layer of the wafer.

[0038] In some embodiments, the pressure sensor includes a detection unit on the wafer.

[0039] The wafer and pressure sensor provided in this application embodiment, by setting a second substrate including a connecting portion and a piezoresistive strip, allows the resistance value of the piezoresistive strip to change when pressure is applied, further causing a change in the voltage output by the connected piezoresistive strip and the connecting portion. Pressure signal detection is achieved through the change in the output voltage signal. By stacking a first substrate, an insulating layer, and a second substrate, a composite substrate of semiconductor material-insulating material-semiconductor material can be obtained. During patterning of the first and second substrates, the insulating layer provides etching resistance, further reducing the difficulty of wafer fabrication, lowering the requirements for fabrication precision, and improving wafer yield. Simultaneously, it facilitates the control of the thickness of the second substrate; reducing the thickness of the second substrate can improve the sensitivity and detection accuracy of the pressure sensor. When an external power signal is connected through a second conductive structure to apply an external voltage to the second substrate, and the second substrate is anoly bonded to the cover plate, the first conductive structure connects the first and second substrates, ensuring electrical connection. This prevents a large accumulation of positive and negative charges on both sides of the insulating layer when an external voltage is applied, thus preventing electrostatic breakdown of the insulating layer. The insulation layer is less susceptible to electrostatic breakdown, which improves its insulation performance and prevents electrical connections between the insulation layer and the piezoresistive strip after breakdown. This avoids affecting the linearity between the resistance change and the pressure change of the piezoresistive strip and prevents leakage current between the piezoresistive strip and the insulation layer during detection, ensuring accurate signal output from the piezoresistive strip and further improving the accuracy and reliability of the pressure sensor. Furthermore, since a large amount of energy is released when the insulation layer is electrostatically broken down, preventing this also reduces mechanical damage to the piezoresistive strip, ensuring its integrity and stability and preventing open circuits. This further improves the reliability and stability of the pressure sensor. Improving the reliability of the insulation layer also ensures the uniformity of the piezoresistive strip's morphology, allowing it to deform accordingly to the applied pressure. This prevents inconsistencies between the deformation and the applied pressure caused by uneven morphology, further improving the sensitivity and accuracy of the pressure sensor. Attached Figure Description

[0040] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic partial structural diagram of a wafer provided for an embodiment of this application;

[0042] Figure 2 A schematic partial structural diagram of another wafer provided in an embodiment of this application;

[0043] Figure 3 A schematic partial structural diagram of another wafer provided in an embodiment of this application;

[0044] Figure 4 A schematic partial structural diagram of another wafer provided in an embodiment of this application;

[0045] Figure 5 A schematic partial structural diagram of a wafer provided for an embodiment of this application;

[0046] Figure 6 A schematic partial structural diagram of another wafer provided in an embodiment of this application;

[0047] Figure 7 A schematic partial structural diagram of another wafer provided in an embodiment of this application;

[0048] Figure 8 A schematic partial structural diagram of another wafer provided in an embodiment of this application;

[0049] Figure 9 A schematic structural diagram of a pressure sensor provided for an embodiment of this application;

[0050] Figure 10 A schematic structural diagram of another pressure sensor provided in an embodiment of this application. Detailed Implementation

[0051] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0052] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0053] In existing piezoresistive sensors, monocrystalline silicon is typically used as the substrate. Etching is performed on both sides of the monocrystalline silicon to create a back cavity and a piezoresistive strip. Force applied to the surface near the back cavity causes deformation of the piezoresistive strip on the other side, resulting in a change in resistance. This change further alters the electrical signal output by the pressure sensor, enabling pressure detection. However, in actual etching processes, using the same material for two etching operations on both sides makes it difficult to control the etching quality. This can easily lead to insufficient or over-etching, increasing the risk of device breakage and affecting the reliability and stability of the pressure sensor. Furthermore, it can result in poor device uniformity, causing variations in the shape of the piezoresistive strip within the same pressure sensor, or uneven pressure surfaces within the same sensor. This can lead to poor linearity of the pressure sensor, affecting the accuracy of the detection results and the sensitivity of the pressure sensor.

[0054] Therefore, SOI (Silicon-On-Insulator) material can be used as the substrate in piezoresistive sensors. The insulating layer in SOI acts as an etching barrier layer, reducing the etching precision requirements and improving the control over etching depth when etching the silicon material on both sides of the insulating layer. This improves the uniformity of the piezoresistive strip and reduces its thickness, further enhancing the sensitivity and reliability of the pressure sensor. Anodic bonding is a wafer-level bonding technology that permanently, strongly, and hermetically seals alkali-containing metal glass to silicon wafers, SiC, or metals under high-temperature and high-voltage DC electric fields. When encapsulating the SOI substrate using anodic bonding, a high voltage needs to be applied to the surface of the silicon substrate where the piezoresistive strip is located to create a strong adsorption between the SOI substrate and the glass cover. However, due to the presence of an insulating layer in the SOI substrate, and the mutual insulation between the silicon substrates on both sides of the insulating layer, a large number of different charges accumulate in the silicon substrates on both sides of the insulating layer under a high voltage. This leads to an increase in the electric field strength within the insulating layer, even exceeding its breakdown field strength, thus increasing the risk of insulation layer breakdown. Furthermore, if the insulating layer breaks down, an electrical connection may form between the insulating layer and the piezoresistive strip, affecting the resistance value of the piezoresistive strip and consequently the linearity between the resistance change and the applied pressure change, thus impacting the accuracy of the pressure sensor. Simultaneously, the electrical connection between the piezoresistive strip and the insulating layer may also cause leakage current during detection, affecting the accuracy of the electrical signal output from the piezoresistive strip and further impacting the accuracy and reliability of the pressure sensor. Since electrostatic breakdown is accompanied by the release of a large amount of energy, electrostatic breakdown of the insulating layer may also cause mechanical damage to the piezoresistive strip, causing deformation or even breakage, affecting the integrity and stability of the piezoresistive strip, and potentially causing short circuits or open circuits in the device, thus affecting the reliability and stability of the pressure sensor.

[0055] Figure 1 This is a schematic partial structural diagram of a wafer provided in an embodiment of this application. Figure 2 This is a schematic partial structural diagram of another wafer provided in an embodiment of this application.

[0056] A first aspect of the embodiments of this application provides a wafer, such as Figure 1 and Figure 2As shown, the wafer includes: a first substrate 100, an insulating layer 200, a second substrate 300, a cover plate 400, a first conductive structure 500, and a second conductive structure 600. The first substrate 100 comprises a semiconductor material; the insulating layer 200 is located on one side of the first substrate 100; the second substrate 300 is located on the side of the insulating layer 200 away from the first substrate 100, and the second substrate 300 also comprises a semiconductor material. The second substrate 300 includes multiple connecting portions 310 and multiple piezoresistive strips 320. Adjacent connecting portions 310 are spaced apart, and the two ends of each piezoresistive strip 320 are connected to adjacent connecting portions 310. The connecting portions 310 and the connected piezoresistive strips 320 are alternately connected to form a pressure detection structure. The first substrate 100 and the second substrate 300 are connected through the first conductive structure 500; the cover plate 400 is located on... On the side of the second substrate 300 away from the first substrate 100, a portion of the surface of the cover plate 400 near the first substrate 100 is bonded to a portion of the surface of the second substrate 300 away from the first substrate 100. The cover plate 400 includes a first opening H1 that penetrates the cover plate 400, and the orthographic projection of the first opening H1 on the plane where the first substrate 100 is located falls within the orthographic projection of the connecting portion 310 on the plane where the first substrate 100 is located. The second conductive structure 600 is located within the first opening H1 of the cover plate 400, and the second conductive structure 600 is electrically connected to the first conductive structure 500. The second conductive structure 600 is used to receive external power signals.

[0057] For example, the second conductive structure 600 located in a pressure detection structure can be electrically connected to the positive terminal of an external power supply, and the cover plate 400 can be electrically connected to the negative terminal of the external power supply. The positive and negative terminals of the external power supply are used together to provide an external power signal, and the first substrate 100 can be grounded. The material of the cover plate 400 may include alkali-containing glass. When a voltage corresponding to the external power signal is applied to the second substrate 300 through the second conductive structure 600, and the ambient temperature is controlled to keep the wafer in a high-temperature environment, the second substrate 300 and the cover plate 400 can achieve anodic bonding under the action of an external electric field. The external power signal can be a DC voltage from 200V to 1000V, for example, 200V, 300V, 500V, 800V, 1000V, etc. The ambient temperature of the bonding process can be from 300°C to 500°C, for example, 300°C, 350°C, 400°C, 450°C, 500°C, etc.

[0058] For example, the orthographic projection shape of the pressure detection structure on the plane of the first substrate 100 is a closed shape, that is, the piezoresistive strips 320 and connecting portions 310 located within a pressure detection structure are alternately arranged to form a ring. Figure 2As shown, the orthographic projection shape of the piezoresistive strip 320 on the plane of the first substrate 100 can be serpentine, so that a longer piezoresistive strip 320 can be set in a smaller space, thereby amplifying the deformation of the piezoresistive strip 320. While meeting the miniaturization requirements of the pressure sensor, the sensitivity and detection accuracy of the pressure sensor can be further improved.

[0059] The wafer provided in this embodiment includes a second substrate 300 comprising a connecting portion 310 and a piezoresistive strip 320. When pressure is applied to the piezoresistive strip 320, its resistance changes, further causing a change in the voltage output by the connected piezoresistive strip 320 and the connecting portion 310. This change in output voltage signal enables pressure signal detection. By stacking the first substrate 100, the insulating layer 200, and the second substrate 300, a composite substrate of semiconductor material-insulating material-semiconductor material can be obtained. During patterning of the first substrate 100 and the second substrate 300, the insulating layer 200 provides etching resistance, further reducing wafer fabrication difficulty, lowering the precision requirements, and improving wafer yield. Simultaneously, the thickness of the second substrate 300 can be easily controlled; reducing its thickness can improve the sensitivity and detection accuracy of the pressure sensor. When an external power signal is connected through the second conductive structure 600 to apply an external voltage to the second substrate 300, and anodic bonding is performed between the second substrate 300 and the cover plate 400,…

[0060] By connecting the first substrate 100 and the second substrate 300 through the first conductive structure 500, the first substrate 100 and the second substrate 300 can be electrically connected. This prevents a large accumulation of positive and negative charges on both sides of the insulating layer 200 when an external voltage is applied, thus preventing the insulating layer 200 from being electrostatically broken down. The insulating layer 200 is less prone to electrostatic breakdown, which improves its insulation performance and prevents it from forming an electrical connection with the piezoresistive strip 320 after breakdown. This avoids affecting the linearity between the resistance change of the piezoresistive strip 320 and the applied pressure change, and also prevents leakage current between the piezoresistive strip 320 and the insulating layer 200 during detection. This ensures accurate output of the electrical signal on the piezoresistive strip 320, further improving the accuracy and reliability of the pressure sensor. Furthermore, since a large amount of energy is released when the insulation layer 200 is electrostatically broken down, preventing this breakdown can reduce mechanical damage to the piezoresistive strip 320, ensuring its integrity and stability, and preventing open circuits. This further improves the reliability and stability of the pressure sensor. Improving the reliability of the insulation layer 200 also ensures the uniformity of the piezoresistive strip 320's morphology, allowing it to deform accordingly to the applied pressure. This prevents inconsistencies between the deformation and the applied pressure caused by uneven morphology, further enhancing the sensitivity and accuracy of the pressure sensor.

[0061] In some feasible implementations, such as Figure 1 As shown, the first substrate 100 includes a fourth opening H4, and the orthographic projection of the piezoresistive strip 320 on the plane of the first substrate 100 falls within the orthographic projection of the fourth opening H4 on the plane of the first substrate 100.

[0062] It should be noted that the fourth opening H4 penetrates the first substrate 100 in the thickness direction, so that a portion of the surface of the insulating layer 200 away from the second substrate 300 is exposed.

[0063] For example, the orthographic projection of all the piezoresistive bars 320 in a pressure detection structure onto the plane of the first substrate 100 falls within the orthographic projection of the corresponding fourth opening H4 onto the plane of the first substrate 100.

[0064] The wafer provided in this embodiment, by including a fourth opening H4 in the first substrate 100, allows a portion of the surface of the insulating layer 200 away from the second substrate 300 to serve as a pressing surface, thereby transmitting externally applied pressure to the piezoresistive strip 320. Furthermore, the orthographic projection of the piezoresistive strip 320 onto the plane of the first substrate 100 falls within the orthographic projection of the fourth opening H4 onto the plane of the first substrate 100. This ensures that the opening area of ​​the fourth opening H4 near the insulating layer 200 is larger than the total area of ​​the piezoresistive strip 320. This provides sufficient expansion space for the insulating layer 200 under pressure, allowing for sufficient deformation of the piezoresistive strip 320. This improves the linearity between the pressure on the insulating layer 200 and the stress on the piezoresistive strip 320, further enhancing the accuracy and reliability of the pressure sensor. Simultaneously, it avoids direct pressure on the piezoresistive strip 320, reducing the risk of breakage and ensuring its integrity and stability. This prevents open circuits or partial circuits in the device, further improving the reliability and stability of the pressure sensor.

[0065] In some feasible implementations, such as Figure 1 As shown, the cover plate 400 has a second groove T2 on the side near the first substrate 100, and the orthographic projection of the pressure strip 320 on the plane where the first substrate 100 is located falls into the orthographic projection of the second groove T2 on the plane where the first substrate 100 is located.

[0066] It should be noted that the surface of the second groove T2 of the cover plate 400 near the second substrate 300 and the surface of the pressure resistance strip 320 near the cover plate 400 are spaced apart to form a cavity.

[0067] The wafer provided in this embodiment has a second groove T2 on the side of the cover plate 400 near the first substrate 100. The orthographic projection of the piezoresistive strip 320 on the plane of the first substrate 100 falls within the orthographic projection of the second groove T2 on the plane of the first substrate 100. This creates a cavity between the cover plate 400 and the piezoresistive strip 320, providing deformation space for the piezoresistive strip 320. This allows for the determination of the pressure corresponding to the deformation of the piezoresistive strip 320 based on the change in resistance value caused by the deformation. Simultaneously, it avoids direct contact between the cover plate 400 and the piezoresistive strip 320, which would increase the risk of breakage of the piezoresistive strip 320. This ensures the integrity and stability of the piezoresistive strip 320, prevents open circuits or partial circuits in the device, and further improves the reliability and stability of the pressure sensor.

[0068] In some feasible implementations, such as Figure 1 As shown, the orthographic projection of the surface of the first opening H1 near the insulating layer 200 on the plane where the first substrate 100 is located falls within the orthographic projection of the surface of the first opening H1 away from the insulating layer 200 on the plane where the first substrate 100 is located.

[0069] For example, the inner diameter of the first opening H1 on the side closer to the insulating layer 200 is smaller than the inner diameter of the first opening H1 on the side farther away from the insulating layer 200.

[0070] The wafer provided in this application embodiment has a cover plate 400 with a first opening H1 that is larger at the top and smaller at the bottom. This facilitates the placement of the second conductive structure 600 in the first opening H1, fully utilizes the opening area of ​​the first opening H1 near the second substrate 300, increases the contact area between the second conductive structure 600 and the second substrate 300, reduces contact loss between the second conductive structure 600 and the second substrate 300, and improves the bonding quality between the cover plate 400 and the second substrate 300.

[0071] In some feasible implementations, such as Figure 1 As shown, the orthographic projection of the surface of the fourth opening H4 of the first substrate 100 near the insulating layer 200 on the plane where the first substrate 100 is located falls within the orthographic projection of the surface of the fourth opening H4 away from the insulating layer 200 on the plane where the first substrate 100 is located.

[0072] For example, the inner diameter of the fourth opening H4 on the side closer to the insulating layer 200 is smaller than the inner diameter of the fourth opening H4 on the side farther from the insulating layer 200.

[0073] The wafer provided in this embodiment of the application, by setting the first substrate 100 to have a fourth opening H4 that is smaller at the top and larger at the bottom, can avoid the insulating layer 200 being exposed to an excessively large area, which would result in an excessively large pressure-bearing surface of the pressure sensor, making the distance between the pressure point and the piezoresistive strip 320 too far, causing inaccurate deformation of the piezoresistive strip 320. This can improve the linearity between the pressure on the insulating layer 200 and the stress on the piezoresistive strip 320, and further improve the accuracy and reliability of the pressure sensor.

[0074] In some feasible implementations, such as Figure 1 As shown, the orthographic projection of the fourth opening H4 on the side of the insulating layer 200 onto the plane of the first substrate 100 falls into the orthographic projection of the second groove T2 of the cover plate 400 onto the plane of the first substrate 100. The second groove T2 is located on the side of the cover plate 400 near the first substrate 100, and the opening of the second groove T2 faces the opening of the insulating layer 200.

[0075] It should be noted that if the area of ​​the second groove T2 is too small, the pressure surface will exceed the range of the second groove T2, so that the force applied to the edge of the pressure surface will act directly on the cover plate 400 and will not cause the deformation of the pressure strip 320.

[0076] The wafer provided in this application embodiment, by setting the area of ​​the second groove T2 to be larger than the surface area of ​​the fourth opening H4 near the insulating layer 200, can ensure that the pressure at any position on the pressure-bearing surface can be transmitted to the piezoresistive strip 320 when the exposed surface of the insulating layer 200 is pressed, thereby improving the sensitivity and accuracy of the pressure sensor.

[0077] In some feasible implementations, the orthographic projection of the second groove T2 onto the plane of the first substrate 100 falls within the orthographic projection of the surface of the fourth opening H4 on the side away from the insulating layer 200 onto the plane of the first substrate 100.

[0078] For example, the inner diameter of the second groove T2 is smaller than the inner diameter of the fourth opening H4 on the side away from the insulating layer 200.

[0079] The wafer provided in this application embodiment can avoid the risk of breakage of the cover plate 400 due to the excessively large area of ​​the second groove T2, thereby further improving the safety and stability of the wafer under stress and improving the reliability of the pressure sensor.

[0080] In some feasible implementations, such as Figure 2 As shown, the number of first openings H1 is equal to the number of connecting parts 310.

[0081] It should be noted that the surface of the connection portion 310 near the first substrate 100 is in complete contact with the surface of the insulating layer 200 away from the first substrate 100. Therefore, the wafer provided in this embodiment, by setting the number of first openings H1 equal to the number of connection portions 310, can increase the number of second conductive structures 600, reduce the power supply range of each second conductive structure 600, and reduce the maximum distance between the second conductive structure 600 and the boundary of the connected second substrate 300. This can improve the voltage uniformity at various positions on the connection portion 310, avoid excessively low local voltage on the connection portion 310, and further improve the bonding quality between the second substrate 300 and the cover plate 400.

[0082] In some feasible implementations, such as Figure 2 As shown, the orthographic projection shape of the pressure detection structure on the plane of the first substrate 100 includes an axisymmetric pattern, and at least two second conductive structures 600 connected to the same pressure detection structure are arranged symmetrically about the axisymmetric pattern.

[0083] The wafer provided in this application embodiment, by setting the orthographic projection shape of the pressure detection structure on the plane of the first substrate 100 to include an axisymmetric pattern, can ensure that each piezoresistive strip 320 is subjected to uniform force, thereby improving the sensitivity of the pressure sensor and reducing the detection error of the pressure detection structure. Furthermore, by symmetrically arranging at least two second conductive structures 600 connected to the same pressure detection structure about the axisymmetric pattern, the power supply range of the symmetrically arranged second conductive structures 600 is made the same, improving the voltage uniformity at various positions on the connection portion 310 and enhancing the bonding quality between the second substrate 300 and the cover plate 400.

[0084] In some feasible implementations, such as Figure 2 As shown, the number of pressure resistance strips 320 and connecting parts 310 are equal.

[0085] The wafer provided in this application embodiment, by setting a connection part 310 corresponding to a piezoresistive strip 320, can avoid the sharing of the connection part 310, prevent crosstalk resistance and temperature drift, thereby further improving the stability and reliability of the pressure sensor and improving the accuracy of the detection results.

[0086] In some feasible implementations, such as Figure 2 As shown, the number of pressure resistance strips 320 and connecting parts 310 are both multiples of 4.

[0087] It should be noted that, in a pressure detection structure comprising four piezoresistive strips 320 and four connecting portions 310, the alternately connected piezoresistive strips 320 and connecting portions 310 can form a Wheatstone bridge. The Wheatstone bridge can differentially amplify the minute voltage changes caused by small variations in the resistance of the piezoresistive strips 320, thereby improving the sensitivity and accuracy of the pressure sensor, enhancing its linearity, reliability, and stability.

[0088] Figure 3 This is a schematic partial structural diagram of another wafer provided in an embodiment of this application. Figure 4 This is a schematic partial structural diagram of another wafer provided in an embodiment of this application. In some feasible implementations, such as... Figure 3 and Figure 4 As shown, the second substrate 300 includes a second opening H2, the insulating layer 200 includes a third opening H3, the first opening H1, the second opening H2 and the third opening H3 are interconnected, the first conductive structure 500 is located inside the second opening H2 and the third opening H3, one end of the first conductive structure 500 is connected to the first substrate 100, and the other end of the first conductive structure 500 is connected to the second conductive structure 600 through the second opening H2, and the first conductive structure 500 is connected to the inner wall of the second opening H2.

[0089] For example, the number of first conductive structures 500 connected to the same pressure sensing structure may be less than or equal to the number of second conductive structures 600.

[0090] It should be noted that the second opening H2 penetrates the second substrate 300 in the thickness direction, and the third opening H3 penetrates the insulating layer 200 in the thickness direction.

[0091] The wafer provided in this embodiment of the application, by setting the second substrate 300 to include a second opening H2, the insulating layer 200 to include a third opening H3, and the first conductive structure 500 located within the second opening H2 and the third opening H3, allows the first conductive structure 500 to be connected to the second substrate 300 through the inner wall of the second opening H2, and to be connected to the first substrate 100 through the surface of the first substrate 100 near the second substrate 200. Furthermore, the first conductive structure can simultaneously connect the first substrate 100 and the second substrate 300. This prevents a large accumulation of positive and negative charges on both sides of the insulating layer 200 when an external voltage is applied, thus preventing the insulating layer 200 from being electrostatically broken down. Furthermore, this can improve the insulation performance of the insulating layer 200, preventing electrical connection between the insulating layer 200 and the piezoresistive strip 320, which would affect the linearity between the resistance change of the piezoresistive strip 320 and the pressure change. It can also prevent leakage current between the piezoresistive strip 320 and the insulating layer 200 during detection, ensuring accurate output of the electrical signal from the piezoresistive strip 320, thus further improving the accuracy and reliability of the pressure sensor. In addition, it can ensure the integrity and stability of the piezoresistive strip 320, preventing open circuits or partial circuits, further improving the reliability and stability of the pressure sensor.

[0092] In some feasible implementations, such as Figure 4 As shown, the first substrate 100 includes a first groove T1, which is connected to a second opening H2. A portion of the first conductive structure 500 is located within the first groove T1, and the first conductive structure 500 is connected to at least a portion of the inner wall of the first groove T1.

[0093] The wafer provided in this application embodiment, by setting the first substrate 100 to include a first groove T1, and a portion of the first conductive structure 500 located within the first groove T1, with the first conductive structure 500 connected to at least a portion of the inner wall of the first groove T1, can further increase the contact area between the first conductive structure 500 and the first substrate 100. This allows for faster carrier transport between the second substrate 300 and the first substrate 100 when an external electric field is applied to the second substrate 300 via an external power signal, further reducing the risk of a large accumulation of positive and negative charges on both sides of the insulating layer 200, improving the insulation performance of the insulating layer 200, and enhancing the electrostatic discharge (ESD) resistance of the insulating layer 200 in the wafer. Furthermore, this can improve the linearity between the resistance change of the piezoresistive strip and the applied pressure change, ensuring accurate output of the electrical signal on the piezoresistive strip 320, and also ensuring the integrity and stability of the piezoresistive strip 320, preventing open circuits or partial circuits in the device, further improving the accuracy and reliability of the pressure sensor.

[0094] In some feasible implementations, such as Figure 3 and Figure 4 As shown, the orthographic projection of the first conductive structure 500 on the plane of the first substrate 100 falls within the orthographic projection of the second conductive structure 600 on the plane of the first substrate 100.

[0095] For example, the minimum diameter of the first conductive structure 500 is smaller than the minimum diameter of the second conductive structure 600.

[0096] The wafer provided in this application embodiment, by setting the orthographic projection of the first conductive structure 500 on the plane where the first substrate 100 is located to fall within the orthographic projection of the second conductive structure 600 on the plane where the first substrate 100 is located, can avoid the first conductive structure 500 being too large, resulting in the first conductive structure 500 occupying too much space in the connection portion 310, and further reduce the volume of the connection portion 310, thereby realizing the miniaturization of the pressure sensor.

[0097] Figure 5 This is a schematic partial structural diagram of a wafer provided for an embodiment of this application. In some feasible implementations, such as... Figure 5 As shown, the first conductive structure 500 covers the outer wall of the first substrate 100 and the second substrate 300 in the thickness direction.

[0098] For example, the first conductive structure 500 may cover a portion of the outer wall of the first substrate 100 in the thickness direction and a portion of the outer wall of the second substrate 300 in the thickness direction. The first conductive structure 500 may be spaced apart from the outer wall of the insulating layer 200 in the thickness direction, or the first conductive structure 500 may cover a portion of the outer wall of the insulating layer 200 in the thickness direction.

[0099] The wafer provided in this embodiment, by providing a first conductive structure 500 covering the outer wall of the first substrate 100 and the second substrate 300 in the thickness direction, allows the first substrate 100 and the second substrate 300 to be connected in the thickness direction, and the first conductive structure can simultaneously connect the first substrate 100 and the second substrate 300. This prevents a large accumulation of positive and negative charges on both sides of the insulating layer 200 when an external voltage is applied, thus preventing the insulating layer 200 from being electrostatically broken down. Furthermore, it improves the insulation performance of the insulating layer 200, preventing electrical connection between the insulating layer 200 and the piezoresistive strip 320, which would affect the linearity between the resistance change of the piezoresistive strip 320 and the applied pressure change. It also prevents leakage current between the piezoresistive strip 320 and the insulating layer 200 during detection, ensuring accurate output of the electrical signal on the piezoresistive strip 320, further improving the accuracy and reliability of the pressure sensor. In addition, it ensures the integrity and stability of the piezoresistive strip 320, preventing open circuits or partial circuits in the device, further improving the reliability and stability of the pressure sensor.

[0100] In some feasible implementations, such as Figure 5 As shown, the first conductive structure 500 completely covers the outer wall of the insulating layer 200 in the thickness direction.

[0101] The wafer provided in this application embodiment, by setting the first conductive structure 500 to completely cover the outer wall of the insulating layer 200 in the thickness direction, allows the first conductive structure 500 to be attached to the outer wall of the first substrate 100, the insulating layer 200, and the second substrate 300 in the thickness direction during the fabrication of the first conductive structure 500. This reduces the difficulty of wafer fabrication and improves wafer fabrication efficiency. At the same time, it avoids the first conductive structure 500 being suspended relative to the outer wall of the insulating layer 200 in the thickness direction, further improving the stability of the first conductive structure 500, thereby improving the reliability and stability of the pressure sensor.

[0102] In some feasible implementations, such as Figure 5 As shown, the first conductive structure 500 is connected to at least a portion of the surface of the first substrate 100 on the side opposite to the second substrate 300.

[0103] In some feasible implementations, such as Figure 5 As shown, the first conductive structure 500 is connected to at least a portion of the surface of the second substrate 300 on the side opposite to the first substrate 100.

[0104] The wafer provided in this application embodiment, by connecting the first conductive structure 500 to at least a portion of the surface of the first substrate 100 facing away from the second substrate 300, increases the contact area between the first conductive structure 500 and the first substrate 100, and between the first conductive structure 500 and the second substrate 300. This allows for faster carrier transport between the second substrate 300 and the first substrate 100 when an external electric field is applied to the second substrate 300 via an external power signal. This further reduces the risk of a large accumulation of positive and negative charges on both sides of the insulating layer 200, improves the insulation performance of the insulating layer 200, and enhances the electrostatic discharge (ESD) resistance of the insulating layer 200 in the wafer. Consequently, it improves the linearity between the resistance change of the piezoresistive strip and the applied pressure change, ensuring accurate output of the electrical signal on the piezoresistive strip 320. It also ensures the integrity and stability of the piezoresistive strip 320, preventing open circuits or partial circuits in the device, and further improving the accuracy and reliability of the pressure sensor.

[0105] Figure 6 This is a schematic partial structural diagram of another wafer provided in an embodiment of this application. Figure 7 This is a schematic partial structural diagram of another wafer provided in an embodiment of this application. Figure 8 This is a schematic partial structural diagram of another wafer provided in an embodiment of this application. In some feasible implementations, such as... Figures 6 to 8 As shown, the wafer includes multiple detection units A, and the connection portions 310 within different detection units A are spaced apart from each other. The portion outlined by the dashed line represents one detection unit A.

[0106] For example, such as Figures 2 to 4 As shown, a wafer may include a detection unit A. A detection unit A may include a pressure detection structure.

[0107] It should be noted that when the wafer includes multiple detection units A, the wafer needs to be diced during the fabrication of the pressure sensor to obtain individual detection units A. Figure 7 In the wafer shown, the first conductive structure 500 can simultaneously connect the first substrate 100 and the second substrate 300 before and after dicing. Therefore, the order of the bonding and dicing steps is not fixed, but bonding is usually performed before dicing. Figure 8In the wafer shown, different detection units A on the same wafer are connected by a first conductive structure 500 located on the outer wall of the first substrate 100 and the second substrate 300 in the thickness direction, or the first substrate 100 and the second substrate 300 in different detection units A are connected, and at least one of the connected detection units A includes the first conductive structure 500 located on the outer wall of the first substrate 100 and the second substrate 300 in the thickness direction. That is, there may be detection units A on the wafer that do not include the first conductive structure 500 directly located on the outer wall of the first substrate 100 and the second substrate 300 in the thickness direction. For Figure 8 To ensure that no electrostatic breakdown occurs in each detection unit A during the bonding process, the wafer shown needs to be bonded first and then cut according to the detection unit A.

[0108] In some feasible implementations, the thickness of the second substrate 300 ranges from 0.6 μm to 1 μm.

[0109] For example, the thickness of the second substrate 300 can be 0.6 μm, 0.7 μm, 0.75 μm, 0.9 μm, 1 μm, etc.

[0110] It should be noted that the thinner the piezoresistive strip 320 is, the higher its sensitivity to pressure. That is, under a small pressure change, a thinner piezoresistive strip 320 can produce a more obvious deformation, and thus a more obvious change in resistance value.

[0111] The wafer provided in this application embodiment, by setting the thickness range of the second substrate 300 to 0.6μm to 1μm, can avoid the increased risk of breakage caused by the piezoresistive strip 320 being too thin, thereby improving the reliability and safety of the pressure sensor. It can also avoid the deformation of the piezoresistive strip being too small due to the thickness of the piezoresistive strip 320 being too large, thereby improving the linearity of the pressure sensor and improving the sensitivity and accuracy of the pressure sensor.

[0112] In some feasible implementations, the first substrate 100 comprises monocrystalline silicon.

[0113] In some feasible implementations, the second substrate 300 comprises monocrystalline silicon.

[0114] The wafer provided in this application embodiment, by setting the first substrate 100 to include monocrystalline silicon and the second substrate 300 to include monocrystalline silicon, can suppress leakage current and signal noise, improve the bonding quality between the cover plate 400 and the second substrate 300, and improve the detection quality of the pressure sensor.

[0115] In some feasible implementations, the first conductive structure 500 includes at least one of a metallic material and in-situ doped polycrystalline silicon.

[0116] It should be noted that in-situ doped polycrystalline silicon involves directly introducing impurity-containing gas into the reaction chamber while growing a polycrystalline silicon thin film, so that doping and deposition are completed in one step without the need for subsequent ion implantation or diffusion.

[0117] For example, when the second substrate 300 includes a second opening H2, the insulating layer 200 includes a third opening H3, and the first conductive structure 500 is located within the second opening H2 and the third opening H3, the first conductive structure 500 may include a metallic material to be formed by a metal interconnect process. When the first conductive structure 500 covers the outer walls of the first substrate 100 and the second substrate 300 in the thickness direction, the first conductive structure 500 may include in-situ doped polycrystalline silicon to be formed as a conductive layer on the surfaces of the first substrate 100, the insulating layer 200, and the second substrate 300 in a single step using a chemical vapor deposition process.

[0118] Figure 9 This is a schematic structural diagram of a pressure sensor provided in an embodiment of this application. Figure 10 A schematic structural diagram of another pressure sensor provided in an embodiment of this application. A second aspect of the embodiments of this application, as... Figure 9 and Figure 10 As shown, a pressure sensor is provided, the pressure sensor comprising: a wafer 1000 as described in any of the first aspects above.

[0119] The pressure sensor provided in this embodiment includes a second substrate 300 comprising a connecting portion 310 and a piezoresistive strip 320. When pressure is applied to the piezoresistive strip 320, its resistance changes, further causing a change in the voltage output by the connected piezoresistive strip 320 and the connecting portion 310. Pressure signal detection is achieved through this change in the output voltage signal. By stacking the first substrate 100, the insulating layer 200, and the second substrate 300, a composite substrate of semiconductor material-insulating material-semiconductor material can be obtained. During patterning of the first substrate 100 and the second substrate 300, the insulating layer 200 provides etching resistance, further reducing the difficulty of wafer fabrication, lowering the requirements for fabrication precision, and improving wafer yield. Simultaneously, the thickness of the second substrate 300 can be easily controlled; reducing the thickness of the second substrate 300 can improve the sensitivity and detection accuracy of the pressure sensor. When an external power signal is connected through the second conductive structure 600 to apply an external voltage to the second substrate 300, and the second substrate 300 is anodicly bonded to the cover plate 400, the first conductive structure 500 connects the first substrate 100 and the second substrate 300. This allows for electrical connection between the first substrate 100 and the second substrate 300, preventing the large accumulation of positive and negative charges on both sides of the insulating layer 200 when an external voltage is applied, thus preventing electrostatic breakdown of the insulating layer 200. The reduced susceptibility of the insulating layer 200 to electrostatic breakdown improves its insulation performance, preventing electrical connection between the insulating layer 200 and the piezoresistive strip 320 after breakdown. This avoids affecting the linearity between the resistance change and the pressure change of the piezoresistive strip 320, and also prevents leakage current between the piezoresistive strip 320 and the insulating layer 200 during detection, ensuring accurate output of the electrical signal on the piezoresistive strip 320. This further improves the accuracy and reliability of the pressure sensor. Furthermore, since a large amount of energy is released when the insulation layer 200 is electrostatically broken down, preventing this breakdown can reduce mechanical damage to the piezoresistive strip 320, ensuring its integrity and stability, and preventing open circuits. This further improves the reliability and stability of the pressure sensor. Improving the reliability of the insulation layer 200 also ensures the uniformity of the piezoresistive strip 320's morphology, allowing it to deform accordingly to the applied pressure. This prevents inconsistencies between the deformation and the applied pressure caused by uneven morphology, further enhancing the sensitivity and accuracy of the pressure sensor.

[0120] In some feasible implementations, such as Figure 10 As shown, the first conductive structure 500 of the wafer is connected to a portion of the surface of the first substrate 100 of the wafer away from the insulating layer 200 of the wafer.

[0121] In some feasible implementations, such as Figure 10 As shown, the first conductive structure 500 of the wafer is connected to a portion of the surface of the second substrate 300 of the wafer away from the insulating layer 200 of the wafer.

[0122] The pressure sensor provided in this application embodiment connects a first conductive structure 500 of the wafer to a portion of the surface of the first substrate 100 away from the insulating layer 200, and the first conductive structure 500 is also connected to a portion of the surface of the second substrate 300 away from the insulating layer 200. This allows the first substrate 100 and the second substrate 300 to be connected in the thickness direction before the wafer is diced to obtain the pressure sensor. This enables the first conductive structure to simultaneously connect the first substrate 100 and the second substrate 300. Consequently, when an external voltage is applied, a large accumulation of positive and negative charges on both sides of the insulating layer 200 is avoided, preventing the insulating layer 200 from being electrostatically broken down. Furthermore, this can improve the insulation performance of the insulating layer 200, preventing electrical connection between the insulating layer 200 and the piezoresistive strip 320, which would affect the linearity between the resistance change of the piezoresistive strip 320 and the pressure change. It can also prevent leakage current between the piezoresistive strip 320 and the insulating layer 200 during detection, ensuring accurate output of the electrical signal from the piezoresistive strip 320, thus further improving the accuracy and reliability of the pressure sensor. In addition, it can ensure the integrity and stability of the piezoresistive strip 320, preventing open circuits or partial circuits, further improving the reliability and stability of the pressure sensor.

[0123] In some feasible implementations, such as Figure 9 and Figure 10 As shown, the pressure sensor includes a detection unit A on a wafer.

[0124] It should be noted that when a wafer includes multiple detection units A, the wafer needs to be cut according to the detection units A to obtain multiple independent detection units A, and then each independent detection unit A is packaged into an independent pressure sensor.

[0125] It should be noted that when a pressure sensor includes multiple detection units A, the pressure-bearing surfaces of the multiple detection units A are not completely connected. This results in the detection results output by the pressure sensor being coupled from the detection results of multiple detection units A, making it difficult to distinguish whether the pressure is localized or multi-point. This leads to increased detection difficulty and decreased detection accuracy of the pressure sensor.

[0126] The pressure sensor provided in this application embodiment reduces the detection difficulty and improves the detection efficiency of the pressure sensor by including a detection unit A on a wafer, while also saving costs.

[0127] The display devices provided in this disclosure may include smartphones, tablets, laptops, televisions, and smart wearable display devices, etc. Smart wearable display devices may include smartwatches, VR (augmented reality) displays, and AR (virtual reality) displays, etc. The embodiments in this disclosure are not specifically limited.

[0128] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0129] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0130] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A wafer, characterized by, include: A first substrate, the first substrate comprising a semiconductor material; An insulating layer is located on one side of the first substrate; The second substrate is located on the side of the insulating layer away from the first substrate. The second substrate includes a semiconductor material. The second substrate includes a plurality of connecting portions and a plurality of piezoresistive strips. Two adjacent connecting portions are spaced apart. The two ends of the piezoresistive strips are respectively connected to two adjacent connecting portions. The connecting portions and the connected piezoresistive strips are alternately connected to form a pressure detection structure. The first substrate and the second substrate are connected through a first conductive structure. A cover plate is located on the side of the second substrate away from the first substrate. A portion of the surface of the cover plate near the first substrate is bonded to a portion of the surface of the second substrate away from the first substrate. The cover plate includes a first opening that penetrates the cover plate, and the orthographic projection of the first opening on the plane of the first substrate falls within the orthographic projection of the connecting portion on the plane of the first substrate. The second conductive structure is located inside the first opening of the cover plate and is electrically connected to the first conductive structure. The second conductive structure is used to receive external power signals.

2. The wafer according to claim 1, characterized in that, The second substrate includes a second opening, and the insulating layer includes a third opening. The first opening, the second opening, and the third opening are interconnected. The first conductive structure is located within the second opening and the third opening. One end of the first conductive structure is connected to the first substrate, and the other end of the first conductive structure is connected to the second conductive structure through the second opening. The first conductive structure is connected to the inner wall of the second opening.

3. The wafer according to claim 2, characterized in that, The first substrate includes a first groove communicating with the second opening, a portion of the first conductive structure being located within the first groove, and the first conductive structure being connected to at least a portion of the inner wall of the first groove; and / or, The orthographic projection of the first conductive structure onto the plane of the first substrate falls within the orthographic projection of the second conductive structure onto the plane of the first substrate.

4. The wafer according to claim 1, characterized in that, The first conductive structure covers the outer walls of the first substrate and the second substrate in the thickness direction.

5. The wafer according to claim 4, characterized in that, The first conductive structure completely covers the outer wall of the insulating layer in the thickness direction.

6. The wafer according to claim 4, characterized in that, The first conductive structure is connected to at least a portion of the surface of the first substrate on the side opposite to the second substrate; and / or, The first conductive structure is connected to at least a portion of the surface of the second substrate on the side opposite to the first substrate.

7. The wafer according to claim 1, 2 or 4, characterized in that, The wafer includes multiple detection units, and the connection portions within different detection units are spaced apart from each other.

8. The wafer according to claim 1, characterized in that, The first substrate includes a fourth opening, and the orthographic projection of the piezoresistive strip on the plane of the first substrate falls within the orthographic projection of the fourth opening on the plane of the first substrate.

9. The wafer according to claim 1, characterized in that, The cover plate has a second groove on the side near the first substrate, and the orthographic projection of the pressure resistance strip on the plane of the first substrate falls into the orthographic projection of the second groove on the plane of the first substrate.

10. The wafer according to claim 1, characterized in that, The orthographic projection of the surface of the first opening near the insulating layer onto the plane of the first substrate falls within the orthographic projection of the surface of the first opening away from the insulating layer onto the plane of the first substrate. And / or, The orthographic projection of the surface of the fourth opening of the first substrate near the insulating layer onto the plane of the first substrate falls within the orthographic projection of the surface of the fourth opening away from the insulating layer onto the plane of the first substrate. And / or, The orthographic projection of the surface of the fourth opening near the insulating layer onto the plane of the first substrate falls into the orthographic projection of the second groove of the cover plate onto the plane of the first substrate, wherein the second groove is located on the side of the cover plate near the first substrate. And / or, The orthographic projection of the second groove onto the plane of the first substrate falls within the orthographic projection of the surface of the fourth opening away from the insulating layer onto the plane of the first substrate.

11. The wafer according to claim 1, characterized in that, The number of the first openings is equal to the number of the connecting portions; and / or, The orthographic projection shape of the pressure detection structure on the plane of the first substrate includes an axisymmetric pattern, and at least two second conductive structures connected to the same pressure detection structure are arranged symmetrically about the axisymmetric pattern.

12. The wafer according to claim 1, characterized in that, The number of the pressure-resistance strips is equal to the number of the connecting portions; and / or, The number of the pressure-resistance strips and the connecting parts are both multiples of 4; and / or, The thickness of the second substrate ranges from 0.6 μm to 1 μm.

13. The wafer according to claim 1, characterized in that, The first substrate comprises monocrystalline silicon; and / or, The second substrate comprises monocrystalline silicon; and / or, The insulating layer comprises silicon oxide; and / or, The first conductive structure includes at least one of a metallic material and in-situ doped polycrystalline silicon.

14. A pressure sensor, characterized by include: The wafer as described in any one of claims 1 to 13.

15. The pressure sensor of claim 14, wherein, include: The first conductive structure of the wafer is connected to a portion of the surface of the first substrate of the wafer on the side away from the insulating layer of the wafer; And / or, The first conductive structure of the wafer is connected to a portion of the surface of the second substrate of the wafer on the side away from the insulating layer of the wafer.

16. The pressure sensor of claim 14, wherein, Includes a detection unit for the wafer.

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