A power-optimized module testing device

Abstract

A power-optimized module testing device includes a main control chip, a video signal generation module, a multi-channel power management module, a power control chip, a dynamic timing control module, and a remote feedback adjustment module. The power control chip communicates with the main control chip via an interface. The dynamic timing control module communicates with the power control chip via an SPI bus and incorporates parameter adjustment and timing optimization circuits to generate compensation signals and adjust the output timing and voltage of the multi-channel power management module in real time. The remote feedback adjustment module includes an ADC sampling unit and a DAC adjustment circuit to acquire the load voltage and feed it back to the dynamic timing control module to generate a compensation signal. The DAC adjustment circuit then generates a compensation voltage signal based on the compensation signal and feeds it back to the corresponding channel. This device achieves millisecond-level timing accuracy and introduces real-time remote feedback compensation technology to automatically compensate for line losses, significantly improving the reliability of test data.

Description

Technical Field

[0001] This utility model relates to the field of electronic display module testing technology, and specifically to a power-optimized module testing device. Background Technology

[0002] As electronic display modules rapidly evolve towards higher resolution, higher refresh rates, and lower power consumption, the timing accuracy and voltage stability of their power supply systems have become core factors affecting test reliability. (Traditional test fixtures - please refer to...) Figure 1 Most systems employ integrated power timing control schemes, relying on software multi-threaded scheduling to achieve multi-channel power management, which presents the following technical bottlenecks: 1) Difficulty in accurately coordinating the control of multiple power supplies: In traditional testing, it is difficult to accurately coordinate the start / stop timing of multiple power supplies, which can easily lead to problems such as power-on shock and timing disorder of the module.

[0003] 2) Lack of far-end voltage drop compensation: Existing testing devices mostly use near-end feedback, which only monitors the output voltage of the power module and ignores the voltage drop at the load end caused by the connection impedance of PCB, FPC, electronic wires, etc. (ΔV=Iload×Rtrace). This causes the actual power supply voltage of the display module to deviate from the set value (for example, the deviation of 3.3V system reaches ±5%), affecting the detection accuracy of key indicators such as color uniformity.

[0004] 3) Conflict between dynamic response and accuracy: Traditional multi-threaded architectures struggle to balance timing control accuracy with real-time compensation requirements. For example, when using a single MCU core to handle PID regulation, the closed-loop control cycle for 9 power supplies needs to be ≥10ms, which cannot meet the voltage fluctuations caused by large current differences in different test scenarios of the module.

[0005] To address these issues, the industry has attempted improvements through hardware acceleration and feedback optimization. For example, some solutions employ dedicated timing controllers for multi-power supply serialization management, but their fixed timing templates are difficult to adapt to the diverse testing scenarios of display modules. Furthermore, existing testing equipment often uses independent functional module designs, resulting in low coordination efficiency between power management, timing control, and feedback compensation, leading to increased system complexity and cost. Utility Model Content

[0006] In view of this, a power-optimized module testing device is provided to solve the technical problems of timing control inaccuracy, lack of remote voltage drop compensation, and insufficient dynamic response in traditional test fixtures.

[0007] A power-optimized module testing device includes a test main control chip MCU1, a video signal generation module FPGA1, a multi-channel power management module, a power control chip MCU2, a dynamic timing control module, and a remote feedback adjustment module. The power control chip MCU2 is connected to the test main control chip MCU1 through an interface; The dynamic timing control module communicates with the power control chip MCU2 via the SPI bus and has built-in parameter adjustment circuit and timing optimization circuit to generate compensation signals and adjust the output timing and voltage of the multi-channel power management module in real time. The remote feedback adjustment module includes an ADC sampling unit and a DAC adjustment circuit. The ADC sampling unit and the DAC adjustment circuit are respectively connected to the dynamic timing control module via an SPI bus. The ADC sampling unit is also connected to the load end to collect load end voltage data and feed it back to the dynamic timing control module. The parameter adjustment circuit provides a compensation signal according to the power supply voltage requirement of the corresponding channel. The DAC adjustment circuit receives the compensation signal and outputs a compensation voltage signal based on the compensation signal. The compensation voltage signal is fed back to the corresponding channel in the multi-channel power management module.

[0008] Furthermore, the multi-channel power management module integrates a DC-DC circuit and outputs nine independent power supplies. The DAC adjustment circuit is connected to a first operational amplifier U87. The non-inverting input of the first operational amplifier U87 is connected to the compensation voltage signal VCC1_V_DAC output by the DAC chip. After processing by the operational amplifier, the output of the first operational amplifier U87 outputs a voltage feedback signal V_FB. The input voltage adjustment pin VSNS of the DC-DC circuit receives the voltage feedback signal V_FB.

[0009] Furthermore, the non-inverting input terminal of the first operational amplifier U87 is connected to an input current-limiting resistor R493 and an input filter unit. The input filter unit includes an input filter capacitor C469 and an input filter resistor R1096 connected in parallel. One end of the input filter unit is connected between the input current-limiting resistor R493 and the non-inverting input terminal, and the other end is grounded. The positive power supply terminal of the first operational amplifier U87 is connected to the positive power supply VCC5V_OP, and the negative power supply terminal is connected to the negative power supply VCC-3V3_OP. After the inverting input terminal and the output terminal of the first operational amplifier U87 are shorted, the output voltage feedback signal V_FB is given to the DC-DC circuit.

[0010] Furthermore, the enable pin EN of the DC-DC circuit is connected to the power control chip MCU2, and the power control chip MCU2 outputs an enable signal VCC_EN to the DC-DC circuit to enable the DC-DC circuit.

[0011] Furthermore, the DC-DC circuit includes a DC-DC chip U86. Multiple output capacitors are connected in parallel between the switching node pin PH and the ground pin GND of the DC-DC chip U86. The first end of the multiple output capacitors connected in parallel is connected to the switching node pin PH of the DC-DC chip U86 through the thirteenth inductor L13 and outputs a voltage signal VCC1_OUT. A diode D100 is connected in parallel between the second end of the multiple output capacitors connected in parallel and the input terminal of the thirteenth inductor L13. The positive terminal of the diode D100 is connected to the ground pin GND of the DC-DC chip U86, and the negative terminal is connected to the input terminal of the thirteenth inductor L13. The switching node pin PH is also connected to the bootstrap startup pin BOOT of the DC-DC chip U86 through a fourth filter capacitor C450 and a twelfth resistor R1243 connected in series.

[0012] Furthermore, the voltage feedback signal V_FB is connected to the input voltage adjustment pin VSNS through a feedback current limiting resistor R492 and an RC filter unit. One end of the RC filter unit is connected between the feedback current limiting resistor R492 and the input voltage adjustment pin VSNS, and the other end is connected to the first end of a series of output capacitors connected in parallel through a tenth current limiting resistor R1056. The RC filter unit includes a feedback filter resistor R489 and a feedback filter capacitor C463.

[0013] Furthermore, the testing device also includes a power discharge circuit, which includes a dual op-amp chip with two op-amp topologies. The dual op-amp chip includes a first op-amp U95A and a second op-amp chip U95B. The non-inverting input terminal of the first op-amp U95A is connected to VCC1_DISC via a current-limiting resistor R523. The signal is provided, and the inverting input of the first op-amp U95A is connected to the 1.25V comparator power supply CMP_VREF1V25 via a resistor R220, and to the output of the first op-amp U95A via a resistor R221. The output of the first op-amp U95A is connected to the non-inverting input of the second op-amp U95B. The output of the second op-amp U95B is connected to the gate of a discharge switch transistor Q182 via a sixth current-limiting resistor R524. The drain of the discharge switch transistor Q182 is connected to the load power input VCC1_P to achieve fast power supply regulation or discharge. The inverting input of the second op-amp U95B is connected to the source of the discharge switch transistor Q182 via a resistor R525 and grounded via a discharge resistor R527.

[0014] Furthermore, the ADC sampling unit has multiple channels, and the sampling cable of each ADC sampling unit is connected to the positive terminal and the ground terminal of the load terminal respectively, so as to directly measure the voltage difference at the load terminal.

[0015] Preferably, each of the ADC sampling units is processed by a fourth operational amplifier U96 or a fifth operational amplifier U97 and then transmitted to the ADC chip. The non-inverting input of the fourth operational amplifier U96 is connected to the sampling return signal VCC1_BACK, and the inverting input of the fourth operational amplifier U96 is shorted to the output to output the processed positive terminal sampling signal VCC1_BACK#. The non-inverting input of the fifth operational amplifier U97 is connected to the ground terminal sampling return signal GND_BACK, and the inverting input of the fifth operational amplifier U97 is shorted to the output to output the processed ground terminal sampling signal GND_BACK#.

[0016] Preferably, the DC-DC circuit of the multi-channel power management module adopts a synchronous rectification topology, with each channel having an output current range of 1uA-3A and an output voltage accuracy of ±1%; the ADC sampling unit of the remote feedback adjustment module has a resolution of 16 bits and a sampling frequency of not less than 250kHz.

[0017] The aforementioned power-optimized module testing device has at least the following beneficial effects: 1. The dynamic timing control module can synchronously regulate the output timing and voltage ramp-up rate of the multi-channel power management module (e.g., adjustable to 0.01V / μs) through hardware-level parallel design, thereby avoiding power domain contention. 2. The ADC unit of the remote feedback adjustment module can monitor the load voltage of the display module in real time, and dynamically correct the DAC output in combination with the parameter adjustment circuit built into the dynamic timing control module to compensate for line loss; 3. The power control chip MCU2 receives instructions from the host computer through the interface, sends the preset timing parameters to the dynamic timing control module, and displays the voltage / current curves and abnormal alarm information of each channel in real time; 4. Improved timing accuracy: Through the dynamic timing control module, millisecond-level timing accuracy is achieved, ensuring that each power supply works in coordination according to the predetermined curve, avoiding device damage or test failure caused by timing deviation. For example, the power supply start-up and shutdown timing deviation is reduced from ±50ms in the traditional solution to ±0.1ms, the surge current is reduced by 92%, and the risk of module breakdown is completely avoided. 5. Dynamic voltage drop compensation: Through remote feedback closed-loop control, the load-side voltage fluctuation is narrowed from ±5% to ±0.5%, ensuring the power supply stability of the display module (e.g., 3.3V system error <0.016V). 6. System Integration and Adaptability: With its highly integrated architecture design, it can seamlessly adapt to testing scenarios of various display technologies such as OLED / LCD, providing efficient and flexible testing solutions for the R&D and mass production of diversified display products. Attached Figure Description

[0018] Figure 1 This is a functional block diagram of existing technology.

[0019] Figure 2 Functional block diagram of the power optimization module testing device provided in the embodiment of this utility model; Figure 3 A partial circuit diagram of the DC-DC circuit in the power-optimized module testing device provided in this embodiment of the utility model.

[0020] Figure 4 A partial circuit diagram of the DAC adjustment circuit in the power-optimized module testing device provided in this embodiment of the utility model.

[0021] Figure 5 The schematic diagram of the processing circuit after sampling by the ADC sampling unit at the positive terminal of the load in the power-optimized module testing device provided in this embodiment of the utility model.

[0022] Figure 6 The schematic diagram of the processing circuit after the ADC sampling unit samples at the ground terminal of the load in the power-optimized module testing device provided in this embodiment of the utility model.

[0023] Figure 7 A partial circuit diagram of the power discharge circuit in the power optimization module testing device provided in this embodiment of the utility model. Detailed Implementation

[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0025] Please see Figure 1 This illustration shows a power optimization module testing device provided in Embodiment 1 of the present invention, which includes a test main control chip MCU1, a video signal generation module FPGA1, a multi-channel power management module, a power control chip MCU2, a dynamic timing control module, and a remote feedback adjustment module. The dynamic timing control module and the remote feedback adjustment module are typically integrated together, for example, combined into the FPGA2 shown in the figure.

[0026] The power control chip MCU2 communicates with the test main control chip MCU1 via an interface, for example, through an SPI or UART communication interface. The dynamic timing control module communicates with the power control chip MCU2 via the SPI bus and has built-in parameter adjustment circuits and timing optimization circuits to generate compensation signals and adjust the output timing and voltage of the multi-channel power management module in real time. The host computer sends test parameters to the test main control chip MCU1 via an Ethernet or UART communication interface; MCU1 parses the parameters and generates configuration instructions, then transmits the configuration parameters to MCU2 via the UART communication interface; subsequently, MCU2 transmits the timing configuration instructions to the dynamic timing control module and remote feedback adjustment module of FPGA2 as needed. The remote feedback adjustment module includes an ADC sampling unit and a DAC adjustment circuit. The ADC sampling unit and the DAC adjustment circuit are respectively connected to the dynamic timing control module via an SPI bus. The ADC sampling unit is also connected to the load end to collect load end voltage data and feed it back to the dynamic timing control module. The parameter adjustment circuit provides a compensation signal according to the power supply voltage requirement of the corresponding channel. The DAC adjustment circuit receives the compensation signal and outputs a compensation voltage signal based on the compensation signal. The compensation voltage signal is fed back to the corresponding channel in the multi-channel power management module.

[0027] In this embodiment, the test main control chip MCU1 is a MIMXRT1052DVL6B chip, the dynamic timing control module is a GW2A-LV18QN88C8, and the power control chip MCU2 is a microcontroller of model HC32F460PETB. The test main control chip MCU1 is... Figure 2 The MUC1 main controller and dynamic timing control module are... Figure 2 This is part of the FPGA2 module. The video signal generation module FPGA1 is... Figure 2 FPGA1 in the test is connected to the test main control chip MCU1 via FMC communication.

[0028] Specifically, the multi-channel power management module integrates a DC-DC converter circuit and outputs nine independent power supplies. In a specific embodiment, there are nine DC-DC converter circuits, seven of which are positive voltage output circuits and two are negative voltage output circuits. One of the positive voltage circuits has a relatively large voltage range. The enable pin EN of each DC-DC converter circuit is connected to the power control chip MCU2. The power control chip MCU2 outputs an enable signal VCC_EN to the corresponding DC-DC converter circuit to activate it.

[0029] The basic structure of each DC-DC circuit is the same. This embodiment uses... Figure 3 The circuit diagram in the image is used as an example. For example... Figure 3As shown, the DC-DC circuit has a DC-DC chip U86. Multiple output capacitors are connected in parallel between the switching node pin PH and the ground pin GND of the DC-DC chip U86. The first terminal of the parallel output capacitors is connected to the switching node pin PH of the DC-DC chip U86 through a thirteenth inductor L13 and outputs a voltage signal VCC1_OUT. A diode D100 is connected in parallel between the second terminal of the parallel output capacitors and the input terminal of the thirteenth inductor L13. The anode of diode D100 is connected to the ground pin GND of the DC-DC chip U86, and the cathode is connected to the input terminal of the thirteenth inductor L13. The switching node pin PH is also connected to the bootstrap pin BOOT of the DC-DC chip U86 through a fourth filter capacitor C450 and a twelfth resistor R1243 connected in series. In this embodiment, the DC-DC circuit adopts a synchronous rectification topology, for example, using an LA1315E synchronous rectifier chip. The single-channel output current range is 1μA-3A, the output voltage accuracy is ±1%, and it supports multi-power domain collaborative control. Each DC-DC circuit receives a compensation voltage signal from the DAC adjustment circuit, thereby precisely adjusting the output timing and phase of the power supply for the nine DC-DC circuits in real time.

[0030] In this embodiment, the ADC sampling unit adopts a remote sampling method, with the ADC remote sampling cable electrically connected to the load terminal of the display module. The ADC sampling unit in this embodiment uses an SGM51622S8 chip to achieve a sampling frequency of 250kHz, capturing load voltage fluctuations in real time through an operational amplifier following the input. The ADC sampling unit has a 16-bit resolution and a sampling frequency of no less than 250kHz. The ADC sampling unit acquires load voltage data in real time, and the FPGA parameter adjustment circuit generates a compensation signal to control the transmission path impedance voltage drop deviation within ±0.5%. The ADC remote sampling cable is connected to the positive terminal and ground terminal of the load terminal respectively, directly measuring the load voltage difference, eliminating lead resistance errors, and ensuring high accuracy.

[0031] like Figure 4As shown, the sampling detection signal VCC1_BACK at the positive terminal of the load is processed by a fourth operational amplifier U96. Specifically, the non-inverting input of the fourth operational amplifier U96 is connected to the sampling return signal VCC1_BACK, and the inverting input and output of the fourth operational amplifier U96 are shorted to output the processed positive terminal sampling signal VCC1_BACK#. Therefore, in the ADC sampling unit, the sampling return signal VCC1_BACK is amplified by the fourth operational amplifier U96 to obtain the processed positive terminal sampling signal VCC1_BACK#, which is then transmitted to the ADC chip. The ADC chip receives the processed positive terminal sampling signal VCC1_BACK# and feeds it back to the dynamic timing control module, which then adjusts the signal based on the sampling signal. In addition, a resistor R331 is connected to the output front end of the processed positive terminal sampling signal VCC1_BACK# for voltage division before sending VCC1_BACK# to the ADC chip.

[0032] like Figure 5 The diagram shows the sampling and detection signal GND_BACK from the load's ground terminal being processed by a fifth operational amplifier, U97. The processing circuit principle of the sampling and detection signal GND_BACK is similar to... Figure 4 The processing circuit for the sampling detection signal VCC1_BACK at the positive terminal of the load is basically the same. Similarly, the non-inverting input of the fifth operational amplifier U97 is connected to the sampling return signal GND_BACK at the ground terminal. After shorting the inverting input and output of the fifth operational amplifier U97, the processed ground terminal sampling signal GND_BACK# is output. The processed ground terminal sampling signal GND_BACK# is then transmitted to the ADC chip. The ADC chip receives the processed ground terminal sampling signal GND_BACK# and feeds it back to the dynamic timing control module. The dynamic timing control module then adjusts based on the sampling signal. This embodiment has 9 outputs; therefore, the remaining sampling circuits are essentially the same as described above.

[0033] like Figure 6As shown, the DAC adjustment circuit is connected to a first operational amplifier U87. The non-inverting input of the first operational amplifier U87 is connected to the compensation voltage signal VCC1_V_DAC output by the DAC chip. After processing by the operational amplifier, the output of the first operational amplifier U87 outputs a voltage feedback signal V_FB. The input voltage adjustment pin VSNS of the DC-DC circuit receives the voltage feedback signal V_FB. The first operational amplifier U87 also uses an operational amplifier topology circuit to realize the voltage follower function, thereby enhancing the DAC driving capability. By adjusting the output voltage (VCC1_OUT) through the V_FB signal, V_FB is actually the enhanced DAC signal, which enables the DAC adjustment circuit to output a compensation voltage to the corresponding power supply channel, controlling the load voltage deviation within ±0.5%.

[0034] Furthermore, the non-inverting input terminal of the first operational amplifier U87 is connected to an input current-limiting resistor R493 and an input filter unit. The input filter unit includes an input filter capacitor C469 and an input filter resistor R1096 connected in parallel. One end of the input filter unit is connected between the input current-limiting resistor R493 and the non-inverting input terminal, and the other end is grounded. The positive power supply terminal of the first operational amplifier U87 is connected to the positive power supply VCC5V_OP, and the negative power supply terminal is connected to the negative power supply VCC-3V3_OP. After the inverting input terminal and the output terminal of the first operational amplifier U87 are shorted, the output voltage feedback signal V_FB is given to the DC-DC circuit.

[0035] like Figure 3 As shown, in the DC-DC circuit, the voltage feedback signal V_FB is connected to the input voltage adjustment pin VSNS through a feedback current limiting resistor R492 and an RC filter unit. One end of the RC filter unit is connected between the feedback current limiting resistor R492 and the input voltage adjustment pin VSNS, and the other end is connected to the first end of a series of output capacitors connected in parallel through a tenth current limiting resistor R1056. The RC filter unit includes a feedback filter resistor R489 and a feedback filter capacitor C463.

[0036] Furthermore, the testing device also includes a power discharge circuit, such as... Figure 7As shown, the power supply discharge circuit includes a dual op-amp chip with two op-amp topologies. The dual op-amp chip includes a first op-amp U95A and a second op-amp U95B. The non-inverting input terminal of the first op-amp U95A is connected to VCC1_DISC via a current-limiting resistor R523. The signal is generated as follows: the inverting input of the first op-amp U95A is connected to the 1.25V comparator power supply CMP_VREF1V25 via resistor R220, and to the output of the first op-amp U95A via resistor R221. The output of the first op-amp U95A is connected to the non-inverting input of the second op-amp U95B. The output of the second op-amp U95B is connected to the gate of a discharge switch transistor Q182 via a sixth current-limiting resistor R524. The drain of the discharge switch transistor Q182 is connected to the load power input VCC1_P to achieve fast power supply regulation or discharge. The inverting input of the second op-amp U95B is connected to the source of the discharge switch transistor Q182 via resistor R525 and grounded via discharge resistor R527. The VCC1_DISC signal originates from the dynamic timing control module. The dynamic timing control module directly controls the high and low levels of the VCC1_DISC signal output to control the dual op-amp chip.

[0037] In addition to the parameter adjustment circuit, the dynamic timing control module also incorporates a timing optimization circuit to achieve power-on / off timing adjustment with 0.1ms accuracy and generate a voltage compensation signal based on the sampled signal. Specifically, the load-side voltage is acquired in real time through remote sampling by the ADC sampling unit, and the required compensation signal is fed back to the dynamic timing control module. By comparing the remote voltage (i.e., the acquired load-side voltage) with the target voltage, the VCC1_V_DAC signal of the DAC adjustment circuit is dynamically adjusted in conjunction with the parameter adjustment circuit to achieve remote compensation and stabilize the output voltage. In specific implementation, the dynamic timing control module obtains the modified DAC output, i.e., the VCC1_V_DAC signal, through ADC sampling and a PID algorithm, and then amplifies it and feeds it back to the DCDC circuit to change the output voltage of the corresponding DCDC circuit. The dynamic timing control module uses hardware-level parallel design to synchronously control the output timing and voltage ramp-up rate (adjustable 0.01V / μs) of the multi-channel power management module.

[0038] The specific workflow includes: 1) The host computer sends test parameters via Ethernet, and the test main control chip MCU1 parses the parameters and sends the timing configuration file to the dynamic timing control module; 2) The dynamic timing control module synchronously starts the multi-channel power management module and ramps up the voltage at a preset slope of 0.01V / μs; 3) The ADC sampling unit collects the load voltage data in real time, and generates a compensation signal through the parameter adjustment circuit of the dynamic timing control module; 4) The DAC adjustment circuit outputs a compensation voltage signal, namely VCC1_V_DAC signal, to the corresponding power supply channel to control the load voltage deviation within ±0.5%. In this way, the entire dynamic adjustment cycle is shortened to 100μs, which can compensate for the current surge caused by the switching of the display module screen in real time. 5) Test the communication between the main control chip MCU1 and the video signal generation module FPGA1, display the voltage / current curves of each channel in real time, and immediately cut off the power supply when an abnormality is detected.

[0039] In a specific example, let's take the testing of a 6.1-inch OLED module as an example: • Configure the power supply timing for VCI=3.3V, ELVDD=6V, and ELVSS=-6V. • The dynamic timing control module controls the VCI to power on 15ms before ELVDD / ELVSS, with the voltage ramp-up rate set to 0.05V / μs. • The remote feedback regulation module stabilizes the VCI load voltage at 3.30±0.016V. • Compared to traditional solutions, the power-on inrush current is reduced from 25A to 1.8A, and the timing jitter is less than ±0.05ms. In addition, the device includes a touchscreen connected to the main control MCU for local display of power parameters and alarm information; it is equipped with an emergency stop button for emergency power-off protection. Power protection circuitry is also included during power output.

[0040] It should be noted that this utility model is not limited to the above-described embodiments. Based on the inventive spirit of this utility model, those skilled in the art can make other changes, and these changes made based on the inventive spirit of this utility model should be included within the scope of protection claimed by this utility model.

Claims

1. A power-optimized module testing device, comprising a test master chip MCU1, a video signal generation module FPGA1, and a multi-channel power management module, characterized in that, It also includes a power control chip MCU2, a dynamic timing control module, and a remote feedback adjustment module; The power control chip MCU2 is connected to the test main control chip MCU1 through an interface; The dynamic timing control module communicates with the power control chip MCU2 via the SPI bus and has built-in parameter adjustment circuit and timing optimization circuit to generate compensation signals and adjust the output timing and voltage of the multi-channel power management module in real time. The remote feedback adjustment module includes an ADC sampling unit and a DAC adjustment circuit. The ADC sampling unit and the DAC adjustment circuit are respectively connected to the dynamic timing control module via an SPI bus. The ADC sampling unit is also connected to the load end to collect the load end voltage data and feed it back to the dynamic timing control module. The parameter adjustment circuit provides a compensation signal according to the power supply voltage requirement of the corresponding channel; the DAC adjustment circuit receives the compensation signal and outputs a compensation voltage signal based on the compensation signal, and the compensation voltage signal is fed back to the corresponding channel in the multi-channel power management module.

2. The power-optimized module testing apparatus as described in claim 1, characterized in that, The multi-channel power management module integrates a DC-DC circuit and outputs nine independent power supplies. The DAC adjustment circuit is connected to a first operational amplifier U87. The non-inverting input of the first operational amplifier U87 is connected to the compensation voltage signal VCC1_V_DAC output by the DAC chip. After processing by the operational amplifier, the output of the first operational amplifier U87 outputs a voltage feedback signal V_FB. The input voltage adjustment pin VSNS of the DC-DC circuit receives the voltage feedback signal V_FB.

3. The power-optimized module test apparatus of claim 2, wherein, The non-inverting input of the first operational amplifier U87 is connected to an input current-limiting resistor R493 and an input filter unit. The input filter unit includes an input filter capacitor C469 and an input filter resistor R1096 connected in parallel. One end of the input filter unit is connected between the input current-limiting resistor R493 and the non-inverting input, and the other end is grounded. The positive power supply terminal of the first operational amplifier U87 is connected to the positive power supply VCC5V_OP, and the negative power supply terminal is connected to the negative power supply VCC-3V3_OP. After the inverting input terminal and the output terminal of the first operational amplifier U87 are shorted, the output voltage feedback signal V_FB is given to the DC-DC circuit.

4. The power-optimized module test apparatus of claim 2, wherein The enable pin EN of the DC-DC circuit is connected to the power control chip MCU2. The power control chip MCU2 outputs an enable signal VCC_EN to the DC-DC circuit to enable the DC-DC circuit.

5. The power-optimized module test apparatus of claim 2, wherein, The DC-DC circuit has a DC-DC chip U86. Multiple output capacitors are connected in parallel between the switching node pin PH and the ground pin GND of the DC-DC chip U86. The first end of the multiple output capacitors connected in parallel is connected to the switching node pin PH of the DC-DC chip U86 through the thirteenth inductor L13 and outputs a voltage signal VCC1_OUT. A diode D100 is connected in parallel between the second end of the multiple output capacitors connected in parallel and the input terminal of the thirteenth inductor L13. The positive terminal of the diode D100 is connected to the ground pin GND of the DC-DC chip U86, and the negative terminal is connected to the input terminal of the thirteenth inductor L13. The switching node pin PH is also connected to the bootstrap startup pin BOOT of the DC-DC chip U86 through a fourth filter capacitor C450 and a twelfth resistor R1243 connected in series.

6. The power-optimized module test apparatus of claim 5, wherein, The voltage feedback signal V_FB is connected to the input voltage adjustment pin VSNS through a feedback current limiting resistor R492 and an RC filter unit. One end of the RC filter unit is connected between the feedback current limiting resistor R492 and the input voltage adjustment pin VSNS, and the other end is connected to the first end of a series of multiple output capacitors connected in parallel through a tenth current limiting resistor R1056. The RC filter unit includes a feedback filter resistor R489 and a feedback filter capacitor C463.

7. The power-optimized module test apparatus of claim 5, wherein It also includes a power discharge circuit, which comprises a dual op-amp chip with two op-amp topologies. The dual op-amp chip includes a first op-amp U95A and a second op-amp U95B. The non-inverting input terminal of the first op-amp U95A is connected to VCC1_DISC via a current-limiting resistor R523. The signal is provided, and the inverting input of the first op-amp U95A is connected to the 1.25V comparator power supply CMP_VREF1V25 via a resistor R220, and to the output of the first op-amp U95A via a resistor R221. The output of the first op-amp U95A is connected to the non-inverting input of the second op-amp U95B. The output of the second op-amp U95B is connected to the gate of a discharge switch transistor Q182 via a sixth current-limiting resistor R524. The drain of the discharge switch transistor Q182 is connected to the load power input VCC1_P to achieve fast power supply regulation or discharge. The inverting input of the second op-amp U95B is connected to the source of the discharge switch transistor Q182 via a resistor R525 and grounded via a discharge resistor R527.

8. The power-optimized module test apparatus of claim 1, wherein, The ADC sampling unit has multiple channels, and the sampling cable of each ADC sampling unit is connected to the positive terminal and the ground terminal of the load terminal respectively to directly measure the voltage difference at the load terminal.

9. The power-optimized module test apparatus of claim 8, wherein, Each of the ADC sampling units is processed by a fourth operational amplifier U96 or a fifth operational amplifier U97 and then transmitted to the ADC chip. The non-inverting input of the fourth operational amplifier U96 is connected to the sampling return signal VCC1_BACK. The inverting input of the fourth operational amplifier U96 is shorted to the output, and the processed positive terminal sampling signal VCC1_BACK# is output. The non-inverting input of the fifth operational amplifier U97 is connected to the sampling return signal GND_BACK at the ground terminal. The inverting input of the fifth operational amplifier U97 is shorted to the output, and the processed ground terminal sampling signal GND_BACK# is output.

10. The power-optimized module test apparatus of claim 1, wherein, The DC-DC circuit of the multi-channel power management module adopts a synchronous rectification topology, with each channel having an output current range of 1uA-3A and an output voltage accuracy of ±1%; the ADC sampling unit of the remote feedback adjustment module has a resolution of 16 bits and a sampling frequency of not less than 250kHz.

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