An array substrate, a display panel, and a display device.
By designing grid lines in a three-grid display panel that pass through the central region of the pixel electrode and using multiple common traces to form a dense mesh structure, the problem of large parasitic capacitance changes in the three-grid display panel under process fluctuations is solved, achieving a display effect with high aperture ratio and high resistance to fluctuations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-07-15
- Publication Date
- 2026-07-31
AI Technical Summary
Tri-grid display panels suffer from significant variations in parasitic capacitance between grid lines and pixel electrodes due to process fluctuations, leading to display defects. Furthermore, adding a shielding electrode layer can affect aperture ratio and mass production feasibility.
The array substrate structure is designed so that the gate lines pass through the central region of the pixel electrodes, and through the setting of multiple common traces, including the first common trace and the third common trace, a dense mesh structure is formed that is interconnected, which reduces parasitic capacitance and improves anti-fluctuation capability, while maintaining a high aperture ratio.
It effectively stabilizes the parasitic capacitance between the gate line and the pixel electrode, improves the resistance to process fluctuations, maintains a high aperture ratio, improves display quality, and avoids display defects.
Smart Images
Figure CN224581792U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology
[0002] Thin Film Transistor-Liquid Crystal Displays (TFT-LCDs) have several commonly used display modes, such as Twisted Nematic (TN), Vertically Aligned (VA), Fringe Field Switching (FFS), and In-Plane Switching (IPS). Among these, the VA mode offers better dark-state performance and higher contrast compared to other display modes.
[0003] Triple-gate display panels have become a hot research topic due to their ability to reduce manufacturing costs. However, in current triple-gate display panels, the gate lines are located at the edges of the pixel electrodes. Even slight variations in the manufacturing process can lead to large parasitic capacitances between the gate lines and the pixel electrodes, resulting in numerous display defects. Utility Model Content
[0004] This invention provides an array substrate, a display panel, and a display device to improve the current problems of poor resistance to process fluctuations and large parasitic capacitance between the gate lines and pixel electrodes in tri-gate display panels.
[0005] This utility model embodiment provides an array substrate, wherein:
[0006] Substrate;
[0007] Multiple grid lines, the multiple grid lines extending along a first direction;
[0008] Multiple data lines, the multiple data lines extending along a second direction;
[0009] A plurality of pixel electrodes, wherein the length of the pixel electrodes along the first direction is greater than the length along the second direction, and the orthographic projection of the gate line on the substrate passes through the orthographic projection of the central region of the pixel electrodes on the substrate.
[0010] In one possible implementation, the array substrate further includes: a plurality of first common traces; the first common traces extend along the first direction; and the pixel electrode, in at least a portion of its orthographic projection onto the substrate, is located in the region formed by the intersection of the first common traces and the data lines.
[0011] In one possible implementation, the orthographic projection of the first common trace onto the substrate overlaps with the orthographic projection of the edge portion of the pixel electrode onto the substrate.
[0012] In one possible implementation, the array substrate further includes: a plurality of second common traces, a plurality of third common traces connected to the second common traces, and a plurality of first vias;
[0013] The second common trace extends along the second direction, and the third common trace extends along the first direction and is disconnected at the position where it intersects with the data line; the orthographic projection of the third common trace on the substrate overlaps with the orthographic projection of the first common trace on the substrate, and the third common trace is electrically connected to the first common trace through the first via.
[0014] In one possible implementation, the third common route includes: a first sub-route and a second sub-route connected to the same second common route; the first sub-route and the second sub-route are located on different sides of the second common route, and the first sub-route and the second sub-route are alternately distributed in the second direction.
[0015] In one possible implementation, the same third common route connected to the same second common route extends in the same direction.
[0016] In one possible implementation, the orthographic projection of the second common trace onto the substrate passes through the orthographic projection of the central region of the pixel electrode onto the substrate.
[0017] In one possible implementation, the array substrate further includes: a first transition electrode;
[0018] The third common trace includes: a main portion of the third common trace, and a third common trace overlap portion connected to the end of the main portion of the third common trace; the orthographic projection of the third common trace overlap portion on the substrate overlaps with the orthographic projection of the region between two adjacent pixel electrodes in the first direction on the substrate; and the maximum width of the third common trace overlap portion in the second direction is greater than the maximum width of the main portion of the third common trace in the second direction.
[0019] The first common trace includes: a first common trace main portion and a first common trace overlap portion connected to the first common trace main portion; the orthographic projection of the first common trace overlap portion on the substrate overlaps with the orthographic projection of the region between two adjacent pixel electrodes in the first direction on the substrate; and the maximum width of the first common trace overlap portion in the second direction is greater than the maximum width of the first common trace main portion in the second direction.
[0020] The orthographic projection of the first adapter electrode on the substrate overlaps with the orthographic projections of the third common trace overlap and the first common trace overlap on the substrate, and is connected through the first via at the overlapping position.
[0021] In one possible implementation, the pixel electrode includes: a pixel electrode body, and a pixel electrode overlap portion located on one side of the pixel electrode body;
[0022] The orthographic projection of the first common trace overlaps with the orthographic projection of the first adapter electrode on the substrate, and also overlaps with the orthographic projection of the pixel electrode overlap on the substrate.
[0023] In one possible implementation, the array substrate further includes: a plurality of second vias and a plurality of transistors; the transistors include: a first electrode and a second electrode; the first electrode is connected to the data line; the second electrode is connected to the pixel electrode overlap portion through the second vias;
[0024] The data line includes: a plurality of data line units; each data line unit includes: a first data section extending along the second direction, and a second data section connected to both ends of the first data section and extending along the first direction; two second data sections and the first data section form a recess;
[0025] The first through hole and the second through hole are located in the recessed portion.
[0026] In one possible implementation, the first adapter electrode is in the same layer and made of the same material as the pixel electrode; the first common trace is in the same layer and made of the same material as the gate line; and the second common trace and the third common trace are in the same layer and made of the same material as the data line.
[0027] In one possible implementation, the array substrate further includes: a plurality of transistors and a plurality of pixel electrode columns; two transistors electrically connected to two adjacent pixel electrodes in the same pixel electrode column are located on different sides of the pixel electrode column.
[0028] In one possible implementation, the array substrate further includes a color resist layer; the color resist layer is located between the layer containing the pixel electrode and the layer containing the gate line.
[0029] This application embodiment also provides a display panel, which includes the array substrate as provided in this application embodiment, and further includes a counter substrate disposed opposite to the array substrate; the counter substrate is provided with a common electrode layer.
[0030] This application also provides a display device, which includes the display panel as described in this application embodiment. Attached Figure Description
[0031] Figure 1A This is one of the schematic diagrams of the array substrate provided in the embodiments of this application;
[0032] Figure 1B for Figure 1A Schematic diagram of a single film layer containing the middle gate line;
[0033] Figure 1C for Figure 1A A schematic diagram of the single-film layer containing the data line;
[0034] Figure 1D for Figure 1A A schematic diagram of a single film layer containing the middle pixel electrode;
[0035] Figure 2 for Figure 1A A schematic diagram of the display panel corresponding to the dotted line e1;
[0036] Figure 3A This is a schematic diagram of another array substrate provided in an embodiment of this application;
[0037] Figure 3B for Figure 3A Schematic diagram of a single film layer containing the middle gate line;
[0038] Figure 3C for Figure 3A A schematic diagram of the single-film layer containing the data line;
[0039] Figure 3D for Figure 3A A schematic diagram of a single film layer containing the middle pixel electrode;
[0040] Figure 4A This is a schematic diagram of another array substrate provided in an embodiment of this application;
[0041] Figure 4B for Figure 4A Schematic diagram of a single film layer containing the middle gate line;
[0042] Figure 4C for Figure 4A A schematic diagram of the single-film layer containing the data line;
[0043] Figure 4D for Figure 4A A schematic diagram of a single film layer containing the middle pixel electrode;
[0044] Figure 5 for Figure 4A A schematic diagram of the cross-section at the dashed line e2;
[0045] Figure 6 A cross-sectional schematic diagram of another display panel provided in an embodiment of this application;
[0046] Figure 7 This is a pixel architecture diagram of an array substrate provided in an embodiment of this application. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0049] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.
[0050] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.
[0051] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0052] In conventional triple-gate array substrates, the gate lines are positioned at the edges of the pixel electrodes. To improve aperture ratio, the pixel electrodes and gate lines partially overlap. This type of array substrate structure is weakly resistant to process fluctuations. Even slight process fluctuations can cause significant changes in the parasitic capacitance Cgp between the gate lines and pixel electrodes. This results in severe degradation such as flicker and mura, making mass production impossible. Adding a shielding electrode layer (such as indium tin oxide) to shield the parasitic capacitance Cgp between the gate lines and pixel electrodes leads to a significant decrease in aperture ratio, making it ineffective in meeting specifications and mass production.
[0053] In view of this, see Figures 1A-1D , Figure 2 As shown, where, Figure 1A This is one of the schematic diagrams of the array substrate provided in the embodiments of this application. Figure 1B for Figure 1A A schematic diagram of a single film layer containing the middle gate line. Figure 1C for Figure 1A A schematic diagram of the single-film layer containing the data cable. Figure 1D for Figure 1A A schematic diagram of a single film layer containing the middle pixel electrode. Figure 2 for Figure 1A The schematic diagram of the display panel corresponding to the dotted line e1 in this embodiment of the present invention provides an array substrate, which includes:
[0054] Substrate 1;
[0055] Multiple grid lines 2 extend along the first direction X;
[0056] Multiple data lines 3 extend along the second direction Y;
[0057] Multiple pixel electrodes 4, wherein the length a1 of the pixel electrode 4 along the first direction X is greater than the length a2 along the second direction Y, and the orthographic projection of the gate line 2 onto the substrate 1 passes through the orthographic projection of the central region O of the pixel electrode 4 onto the substrate 1. Optionally, combined with Figure 1D As shown, the pixel electrode 4 includes: a pixel electrode body 40, and a pixel electrode overlap portion 41 located on one side of the pixel electrode body 40. The length a1 of the pixel electrode 4 along the first direction X can be the length of the pixel electrode body 40 along the first direction X, and the length a2 of the pixel electrode 4 along the second direction Y can be the length of the pixel electrode body 40 along the second direction Y. (Refer to...) Figure 1D The pixel electrode can be plate-shaped or include a slit structure; this is not limited here.
[0058] In this embodiment, the length a1 of the pixel electrode 4 along the first direction X is greater than the length a2 along the second direction Y. That is, the array substrate is a Tri Gate array substrate structure. Moreover, the orthogonal projection of the gate line 2 onto the substrate 1 passes through the orthogonal projection of the central region O of the pixel electrode 4 onto the substrate 1, allowing the gate line 2 to run through the middle region or the very center of the pixel electrode 4. Within the process capability range, regardless of the process fluctuations, the parasitic capacitance Cgp between the gate line 2 and the pixel electrode 4 can be guaranteed to be very stable, greatly improving the anti-fluctuation capability, while maintaining the advantages of high aperture ratio and high image quality.
[0059] In conventional Tri-Gate array substrates, the gate line 2 is located at the edge of the pixel electrode 4. To improve the aperture ratio, the pixel electrode 4 and the gate line 2 partially overlap. This type of array substrate structure is weakly resistant to process fluctuations. Even slight process fluctuations can cause significant changes in the parasitic capacitance Cgp between the gate line 2 and the pixel electrode 4. This results in severe degradation such as flicker and mura, making mass production impossible. Adding a shielding electrode layer (such as indium tin oxide) to shield the parasitic capacitance Cgp between the gate line 2 and the pixel electrode 4 would lead to a significant decrease in aperture ratio, making it ineffective in meeting specifications and mass production.
[0060] In one possible implementation, combining Figures 1A-1D , Figure 2 As shown, the array substrate further includes: a plurality of first common traces 51; the first common traces 51 extend along a first direction X; at least a portion of the pixel electrode 4 projected onto the substrate 1 is located in the region formed by the intersection of the first common traces 51 and the data line 3. Exemplarily, the projection of the first common traces 51 onto the substrate 1 overlaps with the projection of the edge portion of the pixel electrode 4 onto the substrate 1.
[0061] In this embodiment of the application, the array substrate further includes: multiple first common traces 51; at least a portion of the pixel electrode 4 projected onto the substrate 1 is located in the area formed by the intersection of the first common traces 51 and the data line 3, that is, the first common traces 51 are disposed at the edge of the pixel electrode 4, which can shield the signal interference between adjacent pixel electrodes 4 and block the light at the edge of the pixel electrode 4 to avoid problems such as pixel color mixing.
[0062] In one possible implementation, combining Figures 1A-1D , Figure 2 As shown, the first common trace 51 can be on the same layer and made of the same material as the gate line 2.
[0063] For example, combined Figures 1A-1D , Figure 2 As shown, the first common trace 51 includes: a main portion 510 of the first common trace, a first common trace overlap portion 511 connected to the main portion 510, and a first common trace branch portion 512 connected to the main portion 510. The orthographic projection of the first common trace overlap portion 511 onto the substrate 1 overlaps with the orthographic projection of the area between two adjacent pixel electrodes 4 in the first direction X onto the substrate 1. Furthermore, the maximum width c2 of the first common trace overlap portion 511 in the second direction Y is greater than the maximum width c1 of the main portion 51 of the first common trace in the second direction Y. The width of the first common trace overlap portion 511 in the first direction X can be greater than the width of the first common trace branch portion 512 in the first direction X. The orthographic projection of the main portion 510 onto the substrate 1 can overlap with the orthographic projection of the lateral edge portion of the pixel electrode 4 onto the substrate 1 to form a storage capacitor. The orthographic projections of the first common trace overlap portion 511 and the first common trace branch portion 512 onto the substrate 1 can overlap with the orthographic projections of the vertical edge portion of the pixel electrode 4 onto the substrate 1 to form a storage capacitor.
[0064] For example, combined Figures 1A-1D , Figure 2 As shown, the array substrate also includes: multiple second vias K2, and multiple transistors T; each transistor T includes: a first electrode TA and a second electrode TB; the first electrode TA is connected to the data line 3; the second electrode TB is connected to the pixel electrode overlap portion 41 through the second vias K2; the data line 3 includes: multiple data line units 30; each data line unit 30 includes: a first data portion 301 extending along the second direction Y, and a second data portion 302 connected to both ends of the first data portion 301 and extending along the first direction X; the two second data portions 302 and the first data portion 301 form a recess Q. The second electrode TB is located in the recess Q, thus, in the second direction Y, two transistors are used to form a recess, and the recess Q accommodates the second electrode, thereby improving the aperture ratio of the display panel.
[0065] For example, combined Figures 1A-1D As shown, the extension lines of the first data sections 301 of two adjacent data line units 30 in the second direction Y can be non-overlapping, thus allowing two transistors to form a recessed portion. For example, combined with... Figures 1A-1D As shown, the extension lines of the first data section 301 of two data line units 30 that are separated in the second direction Y can overlap with each other. For example, the extension line of the first data section 301 of the first data line unit 30 in the second direction Y can overlap with the extension line of the first data section 301 of the third data line unit 30.
[0066] For example, the orthographic projection of the first common trace overlap 511 onto the substrate 1 can cover the orthographic projection of the second via K2 onto the substrate 1, thereby blocking the second via K1 and avoiding display defects at the second via K2.
[0067] For example, the orthographic projection of transistor T onto substrate 1 may be located in the region between two adjacent pixel electrodes 4 in the first direction X within the orthographic projection of substrate 1.
[0068] In one possible implementation, combining Figures 1A-1D , Figure 2 As shown, the display panel may include a counter substrate disposed opposite to the array substrate. The counter substrate may be provided with a counter substrate 90 and a common electrode layer 50 located on the side of the counter substrate 90 facing the array substrate. The voltage applied to the first common trace 51 may be the same as the voltage applied to the common electrode layer 50.
[0069] In one possible implementation, combining Figures 1A-1D , Figure 2 As shown, the array substrate may further include: a gate insulating layer 91 located between the layer where the gate line 2 is located and the layer where the data line 3 is located, a passivation layer 92 located between the layer where the data line 3 is located and the layer where the pixel electrode 4 is located, a planarization layer 93 located between the passivation layer 92 and the layer where the pixel electrode 4 is located, and a first alignment film layer 95 located on the side of the layer where the pixel electrode 4 is located away from the substrate 1.
[0070] The opposing substrate may further include: a color resist layer 7 located between the opposing substrate 90 and the common electrode layer 50, a black matrix 8 located between the color resist layer 7 and the opposing substrate 90, and a second alignment film layer 96 located on the side of the common electrode layer 50 facing away from the opposing substrate 90. The color resist layer 7 may include a first color resist 71, a second color resist 72, and a third color resist 73; the first color resist 71 may be a red color resist, the second color resist 72 may be a green color resist, and the third color resist 73 may be a blue color resist.
[0071] A liquid crystal layer 99 can also be disposed between the array substrate and the opposing substrate.
[0072] See Figures 3A-3D As shown, where, Figure 3A This is a schematic diagram of another array substrate provided in an embodiment of this application. Figure 3B for Figure 3A A schematic diagram of a single film layer containing the middle gate line. Figure 3C for Figure 3A A schematic diagram of the single-film layer containing the data cable. Figure 3D for Figure 3A A schematic diagram of a single film layer where the middle pixel electrode is located. The array substrate also includes: multiple second common traces 52, multiple third common traces 53 connected to the second common traces 52, and multiple first vias K1; the second common traces 52 extend along the second direction Y, the third common traces 53 extend along the first direction X, and are disconnected at the position where they intersect with the data line 3; the orthographic projection of the third common trace 53 on the substrate 1 overlaps with the orthographic projection of the first common trace 51 on the substrate 1, and the third common trace 53 is electrically connected to the first common trace 51 through the first vias K1.
[0073] In this embodiment, the array substrate further includes multiple second common traces 52 and multiple third common traces 53 connected to the second common traces 52. The third common traces 53 are electrically connected to the first common traces 51 through a first via K1, thereby forming a dense mesh structure of interconnected common traces on the array substrate. This helps to reduce the resistance of the common traces, reduce the signal delay on the common traces, effectively improve the uniformity of the common voltage on the common traces, and help to improve crosstalk and further optimize flicker. Moreover, all common traces are located in dark texture areas or light-shielding areas, so they do not affect the transmittance.
[0074] For example, the second common route 52 and the third common route 53 can be on the same layer and made of the same material as the data line 3.
[0075] In one possible implementation, see Figures 3A-3D As shown, the third common route 53 includes: a first sub-route 531 and a second sub-route 532 connected to the same second common route 52; the first sub-route 531 and the second sub-route 532 are located on different sides of the second common route 52, and the first sub-route 531 and the second sub-route 532 are alternately distributed in the second direction Y.
[0076] In this embodiment, the third common trace 53 includes a first sub-trace 531 and a second sub-trace 532 connected to the same second common trace 52. The first sub-trace 531 and the second sub-trace 532 are located on different sides of the second common trace 52, and are alternately distributed in the second direction Y. While achieving electrical connection with the first common trace 51 via drilling, this reduces the overlap area between the third common trace 53 and the first common trace 51, thus reducing the probability of a short circuit between them (for double-layer metal traces, the more overlap there is, the higher the risk of a short circuit in the manufacturing process). Furthermore, it avoids being too close to the data line 3, preventing mutual interference. In addition, double-layer metal traces are prone to light blocking due to alignment deviations. By having the first sub-trace 531 and the second sub-trace 532 alternately distributed in the second direction Y, the risk of increased transmittance due to alignment deviations is reduced.
[0077] In one possible implementation, see Figures 3A-3D As shown, the orthographic projection of the second common trace 52 onto the substrate 1 passes through the orthographic projection of the central region of the pixel electrode 4 onto the substrate 1. This is done so that the second common trace 52 overlaps with the dark areas of the display panel, thus avoiding an increase in the dark areas of the display panel when they do not overlap, which would be detrimental to improving the transmittance of the display panel.
[0078] In one possible implementation, see Figures 3A-3D As shown, the array substrate further includes: a first transition electrode 61; the third common trace 53 includes: a third common trace main portion 530, and a third common trace overlap portion 533 connected to the end of the third common trace main portion 530; the orthographic projection of the third common trace overlap portion 533 on the substrate 1 overlaps with the orthographic projection of the area between two adjacent pixel electrodes 4 in the first direction X on the substrate 1; and the maximum width b2 of the third common trace overlap portion 533 in the second direction Y is greater than the maximum width b1 of the third common trace main portion 530 in the second direction.
[0079] The orthographic projection of the first adapter electrode 61 onto the substrate 1 overlaps with the orthographic projections of the third common trace overlap portion 533 and the first common trace overlap portion 511 onto the substrate 1, and is connected through the first via K1 at the overlapping position.
[0080] In this embodiment, the maximum width b2 of the third common trace overlap portion 533 in the second direction Y is greater than the maximum width b1 of the third common trace main portion 530 in the second direction, so as to facilitate electrical connection with the first adapter electrode 61 through the first via K1; the maximum width c2 of the first common trace overlap portion 511 in the second direction Y is greater than the maximum width c1 of the first common trace main portion 51 in the second direction Y, so as to facilitate electrical connection with the first adapter electrode 61 through the first via K1.
[0081] In one possible implementation, see Figures 3A-3D As shown, the orthographic projection of the first common trace overlap 511 on the substrate 1 overlaps with the orthographic projection of the first transition electrode 61 on the substrate, the orthographic projection of the pixel electrode overlap 41 on the substrate, and the orthographic projection of the second electrode TB on the substrate 1. This is beneficial for improving the aperture ratio of the display panel.
[0082] In one possible implementation, see Figures 3A-3D As shown, the third common trace overlap 533 and the second electrode TB are located in the recessed portion Q. This facilitates an increase in the aperture ratio of the display panel.
[0083] In one possible implementation, see Figures 3A-3D As shown, the first via K1 and the second via K2 are located in the recessed portion Q. That is, in the second direction Y, two transistors are used to form the recessed portion, and the recessed portion Q accommodates the first via K1 and the second via K2, which helps to improve the aperture ratio of the display panel.
[0084] In one possible implementation, the first transition electrode 61 is on the same layer and made of the same material as the pixel electrode 4. Thus, the first transition electrode 61 can be formed simultaneously with the pixel electrode 4, simplifying the fabrication process of the array substrate.
[0085] Understandably, Figures 3A-3D The array substrate structure shown is similar to Figures 1A-1D The main difference in the array substrate structure shown is the provision of a second common trace 52 and a third common trace 53 to achieve electrical connection between the common traces. Figures 3A-3D Other structures of the array substrate shown can be referred to. Figures 1A-1D The specific implementation methods will not be detailed here.
[0086] See Figures 4A-4D and Figure 5 As shown, where, Figure 4A This is a schematic diagram of another array substrate provided in an embodiment of this application. Figure 4B for Figure 4A A schematic diagram of a single film layer containing the middle gate line. Figure 4C for Figure 4A A schematic diagram of the single-film layer containing the data cable. Figure 4D for Figure 4A A schematic diagram of a single film layer containing the middle pixel electrode. Figure 5 for Figure 4AIn the cross-sectional diagram at the dashed line e2, the extension directions of the same third common route 53 connected to the same second common route 52 are the same. In this embodiment, the extension directions of the same third common route 53 connected to the same second common route 52 are the same. That is, the third common route 53 may not have alternating distribution of the first sub-routes 531 and the second sub-routes 532, or it may achieve interconnection of each common route to form a dense mesh structure.
[0087] Understandably, Figures 4A-4D The array substrate structure shown is similar to Figures 3A-3D The main difference in the array substrate structure shown lies in the placement of the third common trace 53. Figures 4A-4D Other structures of the array substrate shown can be referred to. Figures 3A-3D as well as Figures 1A-1D The relevant implementation methods are not detailed here.
[0088] See Figure 6 As shown, Figure 6 This is a cross-sectional schematic diagram of another display panel provided in an embodiment of this application. The array substrate further includes a color resist layer 7; the color resist layer 7 is located between the layer containing the pixel electrode 4 and the layer containing the gate line 2. In this embodiment, the color resist layer 7 can also be an array substrate, which can increase the distance between the gate line 2 and the pixel electrode 4, reduce the load on the gate line 2 and the parasitic capacitance Cgd between the gate line 2 and the pixel electrode 4, and facilitate the achievement of a higher refresh rate.
[0089] See Figure 7 As shown, Figure 7 This application provides a pixel architecture diagram of an array substrate. The array substrate further includes: multiple pixel electrode columns L; and two transistors T electrically connected to two adjacent pixel electrodes 4 in the same pixel electrode column L, located on different sides of the pixel electrode column L. That is, the two transistors T electrically connected to two adjacent pixel electrodes 4 in the same pixel electrode column L are electrically connected to different data lines 3. In other words, this application allows for a Z-shaped connection between the pixel electrodes and transistors, ensuring consistent charging without introducing new risks. This avoids the risk of "head-shaking" patterns that can occur when two transistors T electrically connected to two adjacent pixel electrodes 4 in the same pixel electrode column L are located on the same side of the pixel electrode column L and electrically connected to the same data line 3.
[0090] Based on the same inventive concept, this application also provides a display panel, combined with Figure 2 , Figure 5 , Figure 6 As shown, the display panel includes the array substrate provided in the embodiments of this application, and also includes a counter substrate disposed opposite to the array substrate; the counter substrate is provided with a common electrode layer. Implementation of this display panel can refer to the embodiments of the array substrate described above, and repeated details will not be repeated.
[0091] Based on the same inventive concept, this application also provides a display device, which includes a display panel as provided in the embodiments of this application. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.
[0092] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0093] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0094] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.
Claims
1. An array substrate, wherein, include: Substrate; Multiple grid lines, the multiple grid lines extending along a first direction; Multiple data lines, the multiple data lines extending along a second direction; A plurality of pixel electrodes, wherein the length of the pixel electrodes along the first direction is greater than the length along the second direction, and the orthographic projection of the gate line on the substrate passes through the orthographic projection of the central region of the pixel electrodes on the substrate.
2. The array substrate of claim 1, wherein, The array substrate further includes: a plurality of first common traces; the first common traces extend along the first direction; and at least a portion of the pixel electrode projected onto the substrate is located in the region formed by the intersection of the first common traces and the data lines.
3. The array substrate of claim 2, wherein, The orthographic projection of the first common trace onto the substrate overlaps with the orthographic projection of the edge portion of the pixel electrode onto the substrate.
4. The array substrate as described in claim 2 or 3, wherein, The array substrate further includes: multiple second common traces, multiple third common traces connected to the second common traces, and multiple first vias; The second common trace extends along the second direction, and the third common trace extends along the first direction and is disconnected at the position where it intersects with the data line; the orthographic projection of the third common trace on the substrate overlaps with the orthographic projection of the first common trace on the substrate, and the third common trace is electrically connected to the first common trace through the first via.
5. The array substrate of claim 4, wherein, The third common route includes: a first sub-route and a second sub-route connected to the same second common route; the first sub-route and the second sub-route are located on different sides of the second common route, and the first sub-route and the second sub-route are alternately distributed in the second direction.
6. The array substrate of claim 4, wherein, The third common route connected to the same second common route extends in the same direction.
7. The array substrate of claim 5, wherein, The second common trace is projected onto the substrate through the central region of the pixel electrode.
8. The array substrate of claim 4, wherein, The array substrate further includes: a first transition electrode; The third common trace includes: a main portion of the third common trace, and a third common trace overlap portion connected to the end of the main portion of the third common trace; the orthographic projection of the third common trace overlap portion on the substrate overlaps with the orthographic projection of the region between two adjacent pixel electrodes in the first direction on the substrate; and the maximum width of the third common trace overlap portion in the second direction is greater than the maximum width of the main portion of the third common trace in the second direction. The first common trace includes: a first common trace main portion and a first common trace overlap portion connected to the first common trace main portion; the orthographic projection of the first common trace overlap portion on the substrate overlaps with the orthographic projection of the region between two adjacent pixel electrodes in the first direction on the substrate; and the maximum width of the first common trace overlap portion in the second direction is greater than the maximum width of the first common trace main portion in the second direction. The orthographic projection of the first adapter electrode on the substrate overlaps with the orthographic projections of the third common trace overlap and the first common trace overlap on the substrate, and is connected through the first via at the overlapping position.
9. The array substrate of claim 8, wherein, The pixel electrode includes: a pixel electrode body and a pixel electrode overlap portion located on one side of the pixel electrode body; The orthographic projection of the first common trace overlaps with the orthographic projection of the first adapter electrode on the substrate, and also overlaps with the orthographic projection of the pixel electrode overlap on the substrate.
10. The array substrate of claim 9, wherein, The array substrate further includes: a plurality of second vias and a plurality of transistors; each transistor includes: a first electrode and a second electrode; the first electrode is connected to the data line; the second electrode is connected to the pixel electrode overlap portion through the second vias; The data line includes: a plurality of data line units; each data line unit includes: a first data section extending along the second direction, and a second data section connected to both ends of the first data section and extending along the first direction; two second data sections and the first data section form a recess; The first through hole and the second through hole are located in the recessed portion.
11. The array substrate as claimed in claim 8, wherein, The first adapter electrode is in the same layer and made of the same material as the pixel electrode; the first common trace is in the same layer and made of the same material as the gate line; the second common trace and the third common trace are in the same layer and made of the same material as the data line.
12. The array substrate as claimed in claim 1, wherein, The array substrate further includes: a plurality of transistors and a plurality of pixel electrode columns; two transistors electrically connected to two adjacent pixel electrodes in the same pixel electrode column are located on different sides of the pixel electrode column.
13. The array substrate of claim 1, wherein, The array substrate further includes a color resist layer; the color resist layer is located between the layer containing the pixel electrode and the layer containing the gate line.
14. A display panel, wherein, The array substrate includes the array substrate as described in any one of claims 1-13, and further includes a counter substrate disposed opposite to the array substrate; the counter substrate is provided with a common electrode layer.
15. A display device, wherein, Includes the display panel as described in claim 14.